From nobody Tue May 14 09:04:22 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582073737640964.1473894477485; Tue, 18 Feb 2020 16:55:37 -0800 (PST) Received: from localhost ([::1]:43693 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4DeK-0002nU-7m for importer@patchew.org; Tue, 18 Feb 2020 19:55:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37604) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4DdD-00016g-0U for qemu-devel@nongnu.org; Tue, 18 Feb 2020 19:54:28 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j4DdB-0001Eb-Kg for qemu-devel@nongnu.org; Tue, 18 Feb 2020 19:54:26 -0500 Received: from bilbo.ozlabs.org ([203.11.71.1]:59105 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j4DdA-0001Cl-L9; Tue, 18 Feb 2020 19:54:25 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 48MfPS5XTgz9sRN; Wed, 19 Feb 2020 11:54:20 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1582073660; bh=owSIQ2jSqNFLjR8ApF6Wa6ZPYcUqGtEaeZehoF3bf2U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BSKltC3GJ6gvRjx8cGedm87wIRHXIrr94Skf2aKWTDDUX7/WR4L6xMG0lu5Vm0zrw fTqxj+J2bkGqrAUEtMYDcv0ZXY2l6mEqKk3EpNhf4K7/d7uCNQ8fQtW8FX0St8X2nf tmoE1P0ij5rpIBDhdBkeVP3eh+4VjENg/TIS2T4Y= From: David Gibson To: groug@kaod.org, philmd@redhat.com, qemu-devel@nongnu.org, clg@kaod.org Subject: [PATCH v3 01/12] ppc: Remove stub support for 32-bit hypervisor mode Date: Wed, 19 Feb 2020 11:54:03 +1100 Message-Id: <20200219005414.15635-2-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200219005414.15635-1-david@gibson.dropbear.id.au> References: <20200219005414.15635-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, Mark Cave-Ayland , paulus@samba.org, qemu-ppc@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" a4f30719a8cd, way back in 2007 noted that "PowerPC hypervisor mode is not fundamentally available only for PowerPC 64" and added a 32-bit version of the MSR[HV] bit. But nothing was ever really done with that; there is no meaningful support for 32-bit hypervisor mode 13 years later. Let's stop pretending and just remove the stubs. Signed-off-by: David Gibson Reviewed-by: Fabiano Rosas --- target/ppc/cpu.h | 21 +++++++-------------- target/ppc/translate_init.inc.c | 6 +++--- 2 files changed, 10 insertions(+), 17 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index b283042515..8077fdb068 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -24,8 +24,6 @@ #include "exec/cpu-defs.h" #include "cpu-qom.h" =20 -/* #define PPC_EMULATE_32BITS_HYPV */ - #define TCG_GUEST_DEFAULT_MO 0 =20 #define TARGET_PAGE_BITS_64K 16 @@ -300,13 +298,12 @@ typedef struct ppc_v3_pate_t { #define MSR_SF 63 /* Sixty-four-bit mode hfla= gs */ #define MSR_TAG 62 /* Tag-active mode (POWERx ?) = */ #define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 = */ -#define MSR_SHV 60 /* hypervisor state hfla= gs */ +#define MSR_HV 60 /* hypervisor state hfla= gs */ #define MSR_TS0 34 /* Transactional state, 2 bits (Book3s) = */ #define MSR_TS1 33 #define MSR_TM 32 /* Transactional Memory Available (Book3s) = */ #define MSR_CM 31 /* Computation mode for BookE hfla= gs */ #define MSR_ICM 30 /* Interrupt computation mode for BookE = */ -#define MSR_THV 29 /* hypervisor state for 32 bits PowerPC hfla= gs */ #define MSR_GS 28 /* guest state for BookE = */ #define MSR_UCLE 26 /* User-mode cache lock enable for BookE = */ #define MSR_VR 25 /* altivec available x hfla= gs */ @@ -401,10 +398,13 @@ typedef struct ppc_v3_pate_t { =20 #define msr_sf ((env->msr >> MSR_SF) & 1) #define msr_isf ((env->msr >> MSR_ISF) & 1) -#define msr_shv ((env->msr >> MSR_SHV) & 1) +#if defined(TARGET_PPC64) +#define msr_hv ((env->msr >> MSR_HV) & 1) +#else +#define msr_hv (0) +#endif #define msr_cm ((env->msr >> MSR_CM) & 1) #define msr_icm ((env->msr >> MSR_ICM) & 1) -#define msr_thv ((env->msr >> MSR_THV) & 1) #define msr_gs ((env->msr >> MSR_GS) & 1) #define msr_ucle ((env->msr >> MSR_UCLE) & 1) #define msr_vr ((env->msr >> MSR_VR) & 1) @@ -449,16 +449,9 @@ typedef struct ppc_v3_pate_t { =20 /* Hypervisor bit is more specific */ #if defined(TARGET_PPC64) -#define MSR_HVB (1ULL << MSR_SHV) -#define msr_hv msr_shv -#else -#if defined(PPC_EMULATE_32BITS_HYPV) -#define MSR_HVB (1ULL << MSR_THV) -#define msr_hv msr_thv +#define MSR_HVB (1ULL << MSR_HV) #else #define MSR_HVB (0ULL) -#define msr_hv (0) -#endif #endif =20 /* DSISR */ diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.in= c.c index 53995f62ea..a0d0eaabf2 100644 --- a/target/ppc/translate_init.inc.c +++ b/target/ppc/translate_init.inc.c @@ -8804,7 +8804,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206; pcc->msr_mask =3D (1ull << MSR_SF) | - (1ull << MSR_SHV) | + (1ull << MSR_HV) | (1ull << MSR_TM) | (1ull << MSR_VR) | (1ull << MSR_VSX) | @@ -9017,7 +9017,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL; pcc->msr_mask =3D (1ull << MSR_SF) | - (1ull << MSR_SHV) | + (1ull << MSR_HV) | (1ull << MSR_TM) | (1ull << MSR_VR) | (1ull << MSR_VSX) | @@ -9228,7 +9228,7 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL; pcc->msr_mask =3D (1ull << MSR_SF) | - (1ull << MSR_SHV) | + (1ull << MSR_HV) | (1ull << MSR_TM) | (1ull << MSR_VR) | (1ull << MSR_VSX) | --=20 2.24.1 From nobody Tue May 14 09:04:22 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582073738893475.67084348041953; Tue, 18 Feb 2020 16:55:38 -0800 (PST) Received: from localhost ([::1]:43694 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4DeL-0002pH-Pr for importer@patchew.org; Tue, 18 Feb 2020 19:55:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37606) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4DdC-00016h-Sf for qemu-devel@nongnu.org; Tue, 18 Feb 2020 19:54:28 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j4DdB-0001EU-KZ for qemu-devel@nongnu.org; Tue, 18 Feb 2020 19:54:26 -0500 Received: from bilbo.ozlabs.org ([203.11.71.1]:52855 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j4DdA-0001Cr-NJ; Tue, 18 Feb 2020 19:54:25 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 48MfPS6c5hz9sRl; Wed, 19 Feb 2020 11:54:20 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1582073660; bh=nEJKRLejCEL28rj44HyEzg54TJpnfJdt5dJvRzxAuig=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VZbw0SZWruI+pYdcyYVEJoqC71eaufneWUWbQZAJ0VH8CF0mQ8RVnYMomrUvFggmO aXjOe/xQiWJHcjh6/ta5Vi2U85bLwFrhCxo4WU8ISNVLD2fG8s4nm2CxVS5Uz9oJIH 5k7WRv2TE9MwhH44wA2a/WJmDLm5+ZneRsCke1zc= From: David Gibson To: groug@kaod.org, philmd@redhat.com, qemu-devel@nongnu.org, clg@kaod.org Subject: [PATCH v3 02/12] ppc: Remove stub of PPC970 HID4 implementation Date: Wed, 19 Feb 2020 11:54:04 +1100 Message-Id: <20200219005414.15635-3-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200219005414.15635-1-david@gibson.dropbear.id.au> References: <20200219005414.15635-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, Mark Cave-Ayland , paulus@samba.org, qemu-ppc@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The PowerPC 970 CPU was a cut-down POWER4, which had hypervisor capability. However, it can be (and often was) strapped into "Apple mode", where the hypervisor capabilities were disabled (essentially putting it always in hypervisor mode). That's actually the only mode of the 970 we support in qemu, and we're unlikely to change that any time soon. However, we do have a partial implementation of the 970's HID4 register which affects things only relevant for hypervisor mode. That stub is also really ugly, since it attempts to duplicate the effects of HID4 by re-encoding it into the LPCR register used in newer CPUs, but in a really confusing way. Just get rid of it. Signed-off-by: David Gibson Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Greg Kurz --- target/ppc/mmu-hash64.c | 28 +--------------------------- target/ppc/translate_init.inc.c | 17 ++++++----------- 2 files changed, 7 insertions(+), 38 deletions(-) diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index da8966ccf5..a881876647 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -1091,33 +1091,6 @@ void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong va= l) =20 /* Filter out bits */ switch (env->mmu_model) { - case POWERPC_MMU_64B: /* 970 */ - if (val & 0x40) { - lpcr |=3D LPCR_LPES0; - } - if (val & 0x8000000000000000ull) { - lpcr |=3D LPCR_LPES1; - } - if (val & 0x20) { - lpcr |=3D (0x4ull << LPCR_RMLS_SHIFT); - } - if (val & 0x4000000000000000ull) { - lpcr |=3D (0x2ull << LPCR_RMLS_SHIFT); - } - if (val & 0x2000000000000000ull) { - lpcr |=3D (0x1ull << LPCR_RMLS_SHIFT); - } - env->spr[SPR_RMOR] =3D ((lpcr >> 41) & 0xffffull) << 26; - - /* - * XXX We could also write LPID from HID4 here - * but since we don't tag any translation on it - * it doesn't actually matter - * - * XXX For proper emulation of 970 we also need - * to dig HRMOR out of HID5 - */ - break; case POWERPC_MMU_2_03: /* P5p */ lpcr =3D val & (LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 | @@ -1154,6 +1127,7 @@ void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val) } break; default: + g_assert_not_reached(); ; } env->spr[SPR_LPCR] =3D lpcr; diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.in= c.c index a0d0eaabf2..d7d4f012b8 100644 --- a/target/ppc/translate_init.inc.c +++ b/target/ppc/translate_init.inc.c @@ -7895,25 +7895,20 @@ static void spr_write_lpcr(DisasContext *ctx, int s= prn, int gprn) { gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]); } - -static void spr_write_970_hid4(DisasContext *ctx, int sprn, int gprn) -{ -#if defined(TARGET_PPC64) - spr_write_generic(ctx, sprn, gprn); - gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]); -#endif -} - #endif /* !defined(CONFIG_USER_ONLY) */ =20 static void gen_spr_970_lpar(CPUPPCState *env) { #if !defined(CONFIG_USER_ONLY) /* Logical partitionning */ - /* PPC970: HID4 is effectively the LPCR */ + /* PPC970: HID4 covers things later controlled by the LPCR and + * RMOR in later CPUs, but with a different encoding. We only + * support the 970 in "Apple mode" which has all hypervisor + * facilities disabled by strapping, so we can basically just + * ignore it */ spr_register(env, SPR_970_HID4, "HID4", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_970_hid4, + &spr_read_generic, &spr_write_generic, 0x00000000); #endif } --=20 2.24.1 From nobody Tue May 14 09:04:22 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 158207374075525.19754874882483; Tue, 18 Feb 2020 16:55:40 -0800 (PST) Received: from localhost ([::1]:43696 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4DeN-0002tL-A6 for importer@patchew.org; Tue, 18 Feb 2020 19:55:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37631) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4DdD-00016k-LN for qemu-devel@nongnu.org; Tue, 18 Feb 2020 19:54:29 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j4DdC-0001F1-8n for qemu-devel@nongnu.org; Tue, 18 Feb 2020 19:54:27 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:57369 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j4DdB-0001Ci-Ug; Tue, 18 Feb 2020 19:54:26 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 48MfPT0qFfz9sRt; Wed, 19 Feb 2020 11:54:21 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1582073661; bh=8MpdR9QOB+wpJchmvKQltUcpEnrUwRlC7qih1/K4psQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=l/aGQ+YF6vxQtH0wPAIwRFZHbL+TpT7PxROjFiKF2vqJuXsVhpV1sAz9LOG40QaqL f7eE5xWskLuKjXUfR8YTVaVUflUq/8xvjnMB0TV4X3yqZ+bTRLUNTYE9lwi1ZnStZD OVOXInFNW7u0awJuf6U+OmccmKweeDzHVujfkPQY= From: David Gibson To: groug@kaod.org, philmd@redhat.com, qemu-devel@nongnu.org, clg@kaod.org Subject: [PATCH v3 03/12] target/ppc: Correct handling of real mode accesses with vhyp on hash MMU Date: Wed, 19 Feb 2020 11:54:05 +1100 Message-Id: <20200219005414.15635-4-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200219005414.15635-1-david@gibson.dropbear.id.au> References: <20200219005414.15635-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, Mark Cave-Ayland , paulus@samba.org, qemu-ppc@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" On ppc we have the concept of virtual hypervisor ("vhyp") mode, where we only model the non-hypervisor-privileged parts of the cpu. Essentially we model the hypervisor's behaviour from the point of view of a guest OS, but we don't model the hypervisor's execution. In particular, in this mode, qemu's notion of target physical address is a guest physical address from the vcpu's point of view. So accesses in guest real mode don't require translation. If we were modelling the hypervisor mode, we'd need to translate the guest physical address into a host physical address. Currently, we handle this sloppily: we rely on setting up the virtual LPCR and RMOR registers so that GPAs are simply HPAs plus an offset, which we set to zero. This is already conceptually dubious, since the LPCR and RMOR registers don't exist in the non-hypervisor portion of the CPU. It gets worse with POWER9, where RMOR and LPCR[VPM0] no longer exist at all. Clean this up by explicitly handling the vhyp case. While we're there, remove some unnecessary nesting of if statements that made the logic to select the correct real mode behaviour a bit less clear than it could be. Signed-off-by: David Gibson Reviewed-by: C=C3=A9dric Le Goater --- target/ppc/mmu-hash64.c | 60 ++++++++++++++++++++++++----------------- 1 file changed, 35 insertions(+), 25 deletions(-) diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index a881876647..5fabd93c92 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -789,27 +789,30 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vadd= r eaddr, */ raddr =3D eaddr & 0x0FFFFFFFFFFFFFFFULL; =20 - /* In HV mode, add HRMOR if top EA bit is clear */ - if (msr_hv || !env->has_hv_mode) { + if (cpu->vhyp) { + /* + * In virtual hypervisor mode, there's nothing to do: + * EA =3D=3D GPA =3D=3D qemu guest address + */ + } else if (msr_hv || !env->has_hv_mode) { + /* In HV mode, add HRMOR if top EA bit is clear */ if (!(eaddr >> 63)) { raddr |=3D env->spr[SPR_HRMOR]; } - } else { - /* Otherwise, check VPM for RMA vs VRMA */ - if (env->spr[SPR_LPCR] & LPCR_VPM0) { - slb =3D &env->vrma_slb; - if (slb->sps) { - goto skip_slb_search; - } - /* Not much else to do here */ + } else if (env->spr[SPR_LPCR] & LPCR_VPM0) { + /* Emulated VRMA mode */ + slb =3D &env->vrma_slb; + if (!slb->sps) { + /* Invalid VRMA setup, machine check */ cs->exception_index =3D POWERPC_EXCP_MCHECK; env->error_code =3D 0; return 1; - } else if (raddr < env->rmls) { - /* RMA. Check bounds in RMLS */ - raddr |=3D env->spr[SPR_RMOR]; - } else { - /* The access failed, generate the approriate interrupt */ + } + + goto skip_slb_search; + } else { + /* Emulated old-style RMO mode, bounds check against RMLS */ + if (raddr >=3D env->rmls) { if (rwx =3D=3D 2) { ppc_hash64_set_isi(cs, SRR1_PROTFAULT); } else { @@ -821,6 +824,8 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr = eaddr, } return 1; } + + raddr |=3D env->spr[SPR_RMOR]; } tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MAS= K, PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx, @@ -953,22 +958,27 @@ hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu= , target_ulong addr) /* In real mode the top 4 effective address bits are ignored */ raddr =3D addr & 0x0FFFFFFFFFFFFFFFULL; =20 - /* In HV mode, add HRMOR if top EA bit is clear */ - if ((msr_hv || !env->has_hv_mode) && !(addr >> 63)) { + if (cpu->vhyp) { + /* + * In virtual hypervisor mode, there's nothing to do: + * EA =3D=3D GPA =3D=3D qemu guest address + */ + return raddr; + } else if ((msr_hv || !env->has_hv_mode) && !(addr >> 63)) { + /* In HV mode, add HRMOR if top EA bit is clear */ return raddr | env->spr[SPR_HRMOR]; - } - - /* Otherwise, check VPM for RMA vs VRMA */ - if (env->spr[SPR_LPCR] & LPCR_VPM0) { + } else if (env->spr[SPR_LPCR] & LPCR_VPM0) { + /* Emulated VRMA mode */ slb =3D &env->vrma_slb; if (!slb->sps) { return -1; } - } else if (raddr < env->rmls) { - /* RMA. Check bounds in RMLS */ - return raddr | env->spr[SPR_RMOR]; } else { - return -1; + /* Emulated old-style RMO mode, bounds check against RMLS */ + if (raddr >=3D env->rmls) { + return -1; + } + return raddr | env->spr[SPR_RMOR]; } } else { slb =3D slb_lookup(cpu, addr); --=20 2.24.1 From nobody Tue May 14 09:04:22 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582073737440977.2747149683004; Tue, 18 Feb 2020 16:55:37 -0800 (PST) Received: from localhost ([::1]:43690 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4DeJ-0002kN-1S for importer@patchew.org; Tue, 18 Feb 2020 19:55:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37603) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4DdC-00016f-TR for qemu-devel@nongnu.org; Tue, 18 Feb 2020 19:54:28 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j4DdB-0001ES-KZ for qemu-devel@nongnu.org; Tue, 18 Feb 2020 19:54:26 -0500 Received: from bilbo.ozlabs.org ([203.11.71.1]:53345 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j4DdA-0001Cs-M8; Tue, 18 Feb 2020 19:54:25 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 48MfPT1mzFz9sRm; Wed, 19 Feb 2020 11:54:21 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1582073661; bh=1r4bWFYWIAuZQrBPKJz/xcWTAIH6wSYYGq6f4/Att88=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dzMue/VQYEqit0gKNcUeATaX92/amoYUd68uBAen9HLxSJtKIeNOOOhv2JutrrI80 8T1jEvm6ZsoWdPdHuRZLkpxcxWh+kjeUI+tXir+tFoLRTpg/BR5xR0EqHWoTGD8VgD OdegqbIG6z/BzCdC7gG0N2RPvZEY1zL0p+60rLoE= From: David Gibson To: groug@kaod.org, philmd@redhat.com, qemu-devel@nongnu.org, clg@kaod.org Subject: [PATCH v3 04/12] target/ppc: Introduce ppc_hash64_use_vrma() helper Date: Wed, 19 Feb 2020 11:54:06 +1100 Message-Id: <20200219005414.15635-5-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200219005414.15635-1-david@gibson.dropbear.id.au> References: <20200219005414.15635-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, Mark Cave-Ayland , paulus@samba.org, qemu-ppc@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" When running guests under a hypervisor, the hypervisor obviously needs to be protected from guest accesses even if those are in what the guest considers real mode (translation off). The POWER hardware provides two ways of doing that: The old way has guest real mode accesses simply offset and bounds checked into host addresses. It works, but requires that a significant chunk of the guest's memory - the RMA - be physically contiguous in the host, which is pretty inconvenient. The new way, known as VRMA, has guest real mode accesses translated in roughly the normal way but with some special parameters. In POWER7 and POWER8 the LPCR[VPM0] bit selected between the two modes, but in POWER9 only VRMA mode is supported and LPCR[VPM0] no longer exists. We handle that difference in behaviour in ppc_hash64_set_isi().. but not in other places that we blindly check LPCR[VPM0]. Correct those instances with a new helper to tell if we should be in VRMA mode. Signed-off-by: David Gibson Reviewed-by: C=C3=A9dric Le Goater --- target/ppc/mmu-hash64.c | 41 +++++++++++++++++++---------------------- 1 file changed, 19 insertions(+), 22 deletions(-) diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index 5fabd93c92..d878180df5 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -668,6 +668,19 @@ unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *= cpu, return 0; } =20 +static bool ppc_hash64_use_vrma(CPUPPCState *env) +{ + switch (env->mmu_model) { + case POWERPC_MMU_3_00: + /* ISAv3.0 (POWER9) always uses VRMA, the VPM0 field and RMOR + * register no longer exist */ + return true; + + default: + return !!(env->spr[SPR_LPCR] & LPCR_VPM0); + } +} + static void ppc_hash64_set_isi(CPUState *cs, uint64_t error_code) { CPUPPCState *env =3D &POWERPC_CPU(cs)->env; @@ -676,15 +689,7 @@ static void ppc_hash64_set_isi(CPUState *cs, uint64_t = error_code) if (msr_ir) { vpm =3D !!(env->spr[SPR_LPCR] & LPCR_VPM1); } else { - switch (env->mmu_model) { - case POWERPC_MMU_3_00: - /* Field deprecated in ISAv3.00 - interrupts always go to hype= rv */ - vpm =3D true; - break; - default: - vpm =3D !!(env->spr[SPR_LPCR] & LPCR_VPM0); - break; - } + vpm =3D ppc_hash64_use_vrma(env); } if (vpm && !msr_hv) { cs->exception_index =3D POWERPC_EXCP_HISI; @@ -702,15 +707,7 @@ static void ppc_hash64_set_dsi(CPUState *cs, uint64_t = dar, uint64_t dsisr) if (msr_dr) { vpm =3D !!(env->spr[SPR_LPCR] & LPCR_VPM1); } else { - switch (env->mmu_model) { - case POWERPC_MMU_3_00: - /* Field deprecated in ISAv3.00 - interrupts always go to hype= rv */ - vpm =3D true; - break; - default: - vpm =3D !!(env->spr[SPR_LPCR] & LPCR_VPM0); - break; - } + vpm =3D ppc_hash64_use_vrma(env); } if (vpm && !msr_hv) { cs->exception_index =3D POWERPC_EXCP_HDSI; @@ -799,7 +796,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr = eaddr, if (!(eaddr >> 63)) { raddr |=3D env->spr[SPR_HRMOR]; } - } else if (env->spr[SPR_LPCR] & LPCR_VPM0) { + } else if (ppc_hash64_use_vrma(env)) { /* Emulated VRMA mode */ slb =3D &env->vrma_slb; if (!slb->sps) { @@ -967,7 +964,7 @@ hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, = target_ulong addr) } else if ((msr_hv || !env->has_hv_mode) && !(addr >> 63)) { /* In HV mode, add HRMOR if top EA bit is clear */ return raddr | env->spr[SPR_HRMOR]; - } else if (env->spr[SPR_LPCR] & LPCR_VPM0) { + } else if (ppc_hash64_use_vrma(env)) { /* Emulated VRMA mode */ slb =3D &env->vrma_slb; if (!slb->sps) { @@ -1056,8 +1053,7 @@ static void ppc_hash64_update_vrma(PowerPCCPU *cpu) slb->sps =3D NULL; =20 /* Is VRMA enabled ? */ - lpcr =3D env->spr[SPR_LPCR]; - if (!(lpcr & LPCR_VPM0)) { + if (ppc_hash64_use_vrma(env)) { return; } =20 @@ -1065,6 +1061,7 @@ static void ppc_hash64_update_vrma(PowerPCCPU *cpu) * Make one up. Mostly ignore the ESID which will not be needed * for translation */ + lpcr =3D env->spr[SPR_LPCR]; vsid =3D SLB_VSID_VRMA; vrmasd =3D (lpcr & LPCR_VRMASD) >> LPCR_VRMASD_SHIFT; vsid |=3D (vrmasd << 4) & (SLB_VSID_L | SLB_VSID_LP); --=20 2.24.1 From nobody Tue May 14 09:04:22 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582074065078381.564940952308; Tue, 18 Feb 2020 17:01:05 -0800 (PST) Received: from localhost ([::1]:43790 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4Djb-0002sS-B3 for importer@patchew.org; Tue, 18 Feb 2020 20:01:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37709) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4DdF-00017C-Hc for qemu-devel@nongnu.org; Tue, 18 Feb 2020 19:54:30 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j4DdD-0001I3-VD for qemu-devel@nongnu.org; Tue, 18 Feb 2020 19:54:29 -0500 Received: from bilbo.ozlabs.org ([203.11.71.1]:60085 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j4DdD-0001Eh-JZ; Tue, 18 Feb 2020 19:54:27 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 48MfPT2d3fz9sSD; Wed, 19 Feb 2020 11:54:21 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1582073661; bh=DCPiz3NvafZwM3W2pQ/+Bg7eB+5qhlsfVA7siZfK2O8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HndSlzAXUSZ8a754ahuPs9jzo02tv39en2BpgykJd534cqORq4mmyqcJVmaDe+R5h yO8rgivPceloGTSN+qTz6mi92Rxu/pvmNHL5z8apH23idkhraIY1Xb/0mV20jR6NN9 zDxmaODU7K0XFeOJ4kbayAe5W6nb/PIwFVHrhM38= From: David Gibson To: groug@kaod.org, philmd@redhat.com, qemu-devel@nongnu.org, clg@kaod.org Subject: [PATCH v3 05/12] spapr, ppc: Remove VPM0/RMLS hacks for POWER9 Date: Wed, 19 Feb 2020 11:54:07 +1100 Message-Id: <20200219005414.15635-6-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200219005414.15635-1-david@gibson.dropbear.id.au> References: <20200219005414.15635-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, Mark Cave-Ayland , paulus@samba.org, qemu-ppc@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" For the "pseries" machine, we use "virtual hypervisor" mode where we only model the CPU in non-hypervisor privileged mode. This means that we need guest physical addresses within the modelled cpu to be treated as absolute physical addresses. We used to do that by clearing LPCR[VPM0] and setting LPCR[RMLS] to a high limit so that the old offset based translation for guest mode applied, which does what we need. However, POWER9 has removed support for that translation mode, which meant we had some ugly hacks to keep it working. We now explicitly handle this sort of translation for virtual hypervisor mode, so the hacks aren't necessary. We don't need to set VPM0 and RMLS from the machine type code - they're now ignored in vhyp mode. On the cpu side we don't need to allow LPCR[RMLS] to be set on POWER9 in vhyp mode - that was only there to allow the hack on the machine side. Signed-off-by: David Gibson Reviewed-by: C=C3=A9dric Le Goater --- hw/ppc/spapr_cpu_core.c | 6 +----- target/ppc/mmu-hash64.c | 8 -------- 2 files changed, 1 insertion(+), 13 deletions(-) diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index d09125d9af..ea5e11f1d9 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -58,14 +58,10 @@ static void spapr_reset_vcpu(PowerPCCPU *cpu) * we don't get spurious wakups before an RTAS start-cpu call. * For the same reason, set PSSCR_EC. */ - lpcr &=3D ~(LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | pcc->lpcr_pm= ); + lpcr &=3D ~(LPCR_VPM1 | LPCR_ISL | LPCR_KBV | pcc->lpcr_pm); lpcr |=3D LPCR_LPES0 | LPCR_LPES1; env->spr[SPR_PSSCR] |=3D PSSCR_EC; =20 - /* Set RMLS to the max (ie, 16G) */ - lpcr &=3D ~LPCR_RMLS; - lpcr |=3D 1ull << LPCR_RMLS_SHIFT; - ppc_store_lpcr(cpu, lpcr); =20 /* Set a full AMOR so guest can use the AMR as it sees fit */ diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index d878180df5..d7f9933e6d 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -1124,14 +1124,6 @@ void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong va= l) (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EE= E | LPCR_DEE | LPCR_OEE)) | LPCR_MER | LPCR_GTSE | LPCR_= TC | LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE); - /* - * If we have a virtual hypervisor, we need to bring back RMLS. It - * doesn't exist on an actual P9 but that's all we know how to - * configure with softmmu at the moment - */ - if (cpu->vhyp) { - lpcr |=3D (val & LPCR_RMLS); - } break; default: g_assert_not_reached(); --=20 2.24.1 From nobody Tue May 14 09:04:22 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 158207416086761.65044652098288; Tue, 18 Feb 2020 17:02:40 -0800 (PST) Received: from localhost ([::1]:43828 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4Dl9-0004ij-TB for importer@patchew.org; Tue, 18 Feb 2020 20:02:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37710) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4DdF-00017D-Hv for qemu-devel@nongnu.org; Tue, 18 Feb 2020 19:54:30 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j4DdD-0001Hr-Tz for qemu-devel@nongnu.org; Tue, 18 Feb 2020 19:54:29 -0500 Received: from bilbo.ozlabs.org ([203.11.71.1]:53563 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j4DdD-0001Ei-I2; Tue, 18 Feb 2020 19:54:27 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 48MfPT3NQwz9sSM; Wed, 19 Feb 2020 11:54:21 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1582073661; bh=byQuVVIMAmZuFS15xfowift/6Krq0ZkYrmw4ZB8MNmY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hxil5yL58m9MvryuxYbSmuu7aYhtOOXTsICb12T7n/T4zWToORv+v88iEUTUb0++E cXUohkMsn3NFGeGH3agLiY0b/M2w6k7WyDQsR2vul5vf21jfdUStYDdM+iOz80IgGf /V39KUO0ld+XVpZgI6JyWlCQ5KcyjsuEp2mtwYpY= From: David Gibson To: groug@kaod.org, philmd@redhat.com, qemu-devel@nongnu.org, clg@kaod.org Subject: [PATCH v3 06/12] target/ppc: Remove RMOR register from POWER9 & POWER10 Date: Wed, 19 Feb 2020 11:54:08 +1100 Message-Id: <20200219005414.15635-7-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200219005414.15635-1-david@gibson.dropbear.id.au> References: <20200219005414.15635-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, Mark Cave-Ayland , paulus@samba.org, qemu-ppc@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Currently we create the Real Mode Offset Register (RMOR) on all Book3S cpus from POWER7 onwards. However the translation mode which the RMOR controls is no longer supported in POWER9, and so the register has been removed from the architecture. Remove it from our model on POWER9 and POWER10. Signed-off-by: David Gibson Reviewed-by: C=C3=A9dric Le Goater --- target/ppc/translate_init.inc.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.in= c.c index d7d4f012b8..c5629d8ba9 100644 --- a/target/ppc/translate_init.inc.c +++ b/target/ppc/translate_init.inc.c @@ -8014,12 +8014,16 @@ static void gen_spr_book3s_ids(CPUPPCState *env) SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); - spr_register_hv(env, SPR_RMOR, "RMOR", + spr_register_hv(env, SPR_HRMOR, "HRMOR", SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); - spr_register_hv(env, SPR_HRMOR, "HRMOR", +} + +static void gen_spr_rmor(CPUPPCState *env) +{ + spr_register_hv(env, SPR_RMOR, "RMOR", SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, @@ -8534,6 +8538,7 @@ static void init_proc_POWER7(CPUPPCState *env) =20 /* POWER7 Specific Registers */ gen_spr_book3s_ids(env); + gen_spr_rmor(env); gen_spr_amr(env); gen_spr_book3s_purr(env); gen_spr_power5p_common(env); @@ -8675,6 +8680,7 @@ static void init_proc_POWER8(CPUPPCState *env) =20 /* POWER8 Specific Registers */ gen_spr_book3s_ids(env); + gen_spr_rmor(env); gen_spr_amr(env); gen_spr_iamr(env); gen_spr_book3s_purr(env); --=20 2.24.1 From nobody Tue May 14 09:04:22 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582074379520451.65476311634086; Tue, 18 Feb 2020 17:06:19 -0800 (PST) Received: from localhost ([::1]:43866 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4Doe-0007ea-RF for importer@patchew.org; Tue, 18 Feb 2020 20:06:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37763) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4DdG-00017t-Fq for qemu-devel@nongnu.org; Tue, 18 Feb 2020 19:54:32 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j4DdE-0001IX-47 for qemu-devel@nongnu.org; Tue, 18 Feb 2020 19:54:30 -0500 Received: from bilbo.ozlabs.org ([203.11.71.1]:45385 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j4DdD-0001Eq-OZ; Tue, 18 Feb 2020 19:54:28 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 48MfPT45vmz9sSH; Wed, 19 Feb 2020 11:54:21 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1582073661; bh=I4eibHJfLuUsTN0S6GpL1yuZlmO0vlNKneFhcNlR7DI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=N1KAmBm42gQAbMlRiUNem91YhUsp4qIf+VvbnmKkLWgREyO1ByqSajgHoh4rRE8bm sgkbgXY9ZaJZvgYVg5Nmbwtw9751Nh7jVmpZO3FCWvGw8BDA15ck5SR85EURSNID8d kvUTuzV3acs7n+unUUqgufF38lZ8YU9fh2F87c+E= From: David Gibson To: groug@kaod.org, philmd@redhat.com, qemu-devel@nongnu.org, clg@kaod.org Subject: [PATCH v3 07/12] target/ppc: Use class fields to simplify LPCR masking Date: Wed, 19 Feb 2020 11:54:09 +1100 Message-Id: <20200219005414.15635-8-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200219005414.15635-1-david@gibson.dropbear.id.au> References: <20200219005414.15635-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, Mark Cave-Ayland , paulus@samba.org, qemu-ppc@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" When we store the Logical Partitioning Control Register (LPCR) we have a big switch statement to work out which are valid bits for the cpu model we're emulating. As well as being ugly, this isn't really conceptually correct, since it is based on the mmu_model variable, whereas the LPCR isn't (only) about the MMU, so mmu_model is basically just acting as a proxy for the cpu model. Handle this in a simpler way, by adding a suitable lpcr_mask to the QOM class. Signed-off-by: David Gibson Reviewed-by: C=C3=A9dric Le Goater --- target/ppc/cpu-qom.h | 1 + target/ppc/mmu-hash64.c | 37 ++------------------------------- target/ppc/translate_init.inc.c | 27 ++++++++++++++++++++---- 3 files changed, 26 insertions(+), 39 deletions(-) diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index e499575dc8..15d6b54a7d 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -177,6 +177,7 @@ typedef struct PowerPCCPUClass { uint64_t insns_flags; uint64_t insns_flags2; uint64_t msr_mask; + uint64_t lpcr_mask; /* Available bits in the LPCR */ uint64_t lpcr_pm; /* Power-saving mode Exit Cause Enable bit= s */ powerpc_mmu_t mmu_model; powerpc_excp_t excp_model; diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index d7f9933e6d..127b7250ae 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -1093,43 +1093,10 @@ static void ppc_hash64_update_vrma(PowerPCCPU *cpu) =20 void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val) { + PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cpu); CPUPPCState *env =3D &cpu->env; - uint64_t lpcr =3D 0; =20 - /* Filter out bits */ - switch (env->mmu_model) { - case POWERPC_MMU_2_03: /* P5p */ - lpcr =3D val & (LPCR_RMLS | LPCR_ILE | - LPCR_LPES0 | LPCR_LPES1 | - LPCR_RMI | LPCR_HDICE); - break; - case POWERPC_MMU_2_06: /* P7 */ - lpcr =3D val & (LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD | - LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | - LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 | - LPCR_MER | LPCR_TC | - LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE); - break; - case POWERPC_MMU_2_07: /* P8 */ - lpcr =3D val & (LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | - LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | - LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 | - LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 | - LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE); - break; - case POWERPC_MMU_3_00: /* P9 */ - lpcr =3D val & (LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | - (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL= | - LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_L= D | - (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EE= E | - LPCR_DEE | LPCR_OEE)) | LPCR_MER | LPCR_GTSE | LPCR_= TC | - LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE); - break; - default: - g_assert_not_reached(); - ; - } - env->spr[SPR_LPCR] =3D lpcr; + env->spr[SPR_LPCR] =3D val & pcc->lpcr_mask; ppc_hash64_update_rmls(cpu); ppc_hash64_update_vrma(cpu); } diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.in= c.c index c5629d8ba9..823c3c7b54 100644 --- a/target/ppc/translate_init.inc.c +++ b/target/ppc/translate_init.inc.c @@ -8475,6 +8475,8 @@ POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) (1ull << MSR_DR) | (1ull << MSR_PMM) | (1ull << MSR_RI); + pcc->lpcr_mask =3D LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 | + LPCR_RMI | LPCR_HDICE; pcc->mmu_model =3D POWERPC_MMU_2_03; #if defined(CONFIG_SOFTMMU) pcc->handle_mmu_fault =3D ppc_hash64_handle_mmu_fault; @@ -8652,6 +8654,12 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) (1ull << MSR_PMM) | (1ull << MSR_RI) | (1ull << MSR_LE); + pcc->lpcr_mask =3D LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD | + LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | + LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 | + LPCR_MER | LPCR_TC | + LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE; + pcc->lpcr_pm =3D LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2; pcc->mmu_model =3D POWERPC_MMU_2_06; #if defined(CONFIG_SOFTMMU) pcc->handle_mmu_fault =3D ppc_hash64_handle_mmu_fault; @@ -8668,7 +8676,6 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) pcc->l1_dcache_size =3D 0x8000; pcc->l1_icache_size =3D 0x8000; pcc->interrupts_big_endian =3D ppc_cpu_interrupts_big_endian_lpcr; - pcc->lpcr_pm =3D LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2; } =20 static void init_proc_POWER8(CPUPPCState *env) @@ -8824,6 +8831,13 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) (1ull << MSR_TS0) | (1ull << MSR_TS1) | (1ull << MSR_LE); + pcc->lpcr_mask =3D LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | + LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | + LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 | + LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 | + LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE; + pcc->lpcr_pm =3D LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 | + LPCR_P8_PECE3 | LPCR_P8_PECE4; pcc->mmu_model =3D POWERPC_MMU_2_07; #if defined(CONFIG_SOFTMMU) pcc->handle_mmu_fault =3D ppc_hash64_handle_mmu_fault; @@ -8841,8 +8855,6 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) pcc->l1_dcache_size =3D 0x8000; pcc->l1_icache_size =3D 0x8000; pcc->interrupts_big_endian =3D ppc_cpu_interrupts_big_endian_lpcr; - pcc->lpcr_pm =3D LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 | - LPCR_P8_PECE3 | LPCR_P8_PECE4; } =20 #ifdef CONFIG_SOFTMMU @@ -9035,6 +9047,14 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) (1ull << MSR_PMM) | (1ull << MSR_RI) | (1ull << MSR_LE); + pcc->lpcr_mask =3D LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | + (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | + LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | + (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | + LPCR_DEE | LPCR_OEE)) + | LPCR_MER | LPCR_GTSE | LPCR_TC | + LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; + pcc->lpcr_pm =3D LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OE= E; pcc->mmu_model =3D POWERPC_MMU_3_00; #if defined(CONFIG_SOFTMMU) pcc->handle_mmu_fault =3D ppc64_v3_handle_mmu_fault; @@ -9054,7 +9074,6 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) pcc->l1_dcache_size =3D 0x8000; pcc->l1_icache_size =3D 0x8000; pcc->interrupts_big_endian =3D ppc_cpu_interrupts_big_endian_lpcr; - pcc->lpcr_pm =3D LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OE= E; } =20 #ifdef CONFIG_SOFTMMU --=20 2.24.1 From nobody Tue May 14 09:04:22 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582074439656571.19388956927; Tue, 18 Feb 2020 17:07:19 -0800 (PST) Received: from localhost ([::1]:43880 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4Dpe-0000YS-Bc for importer@patchew.org; Tue, 18 Feb 2020 20:07:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37739) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4DdF-00017L-TU for qemu-devel@nongnu.org; Tue, 18 Feb 2020 19:54:31 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j4DdE-0001II-1D for qemu-devel@nongnu.org; Tue, 18 Feb 2020 19:54:29 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:56181 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j4DdD-0001El-MF; Tue, 18 Feb 2020 19:54:27 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 48MfPT6FCqz9sSQ; Wed, 19 Feb 2020 11:54:21 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1582073661; bh=WAzB++OU3ECxg/iZAuNfJVH7X/ausKU0fefBATUm37w=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XG4/ffTLrvM4EXtocrtdY4isHEvGPWlvynKJrRaO58WXqCjakujEy9+qwUb6iZ1Vv 0fAW78eBsMdVpUvxW1JMbd65mt0VcTtk8uDApONnrKLPc9BaUAlPr4P0PM3GVH/ICZ CAMLvTKltGjmsJ8rd2zsScZTGOYxZTzeGhbItg8k= From: David Gibson To: groug@kaod.org, philmd@redhat.com, qemu-devel@nongnu.org, clg@kaod.org Subject: [PATCH v3 08/12] target/ppc: Streamline calculation of RMA limit from LPCR[RMLS] Date: Wed, 19 Feb 2020 11:54:10 +1100 Message-Id: <20200219005414.15635-9-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200219005414.15635-1-david@gibson.dropbear.id.au> References: <20200219005414.15635-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, Mark Cave-Ayland , paulus@samba.org, qemu-ppc@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Currently we use a big switch statement in ppc_hash64_update_rmls() to work out what the right RMA limit is based on the LPCR[RMLS] field. There's no formula for this - it's just an arbitrary mapping defined by the existing CPU implementations - but we can make it a bit more readable by using a lookup table rather than a switch. In addition we can use the MiB/GiB symbols to make it a bit clearer. While there we add a bit of clarity and rationale to the comment about what happens if the LPCR[RMLS] doesn't contain a valid value. Signed-off-by: David Gibson Reviewed-by: C=C3=A9dric Le Goater --- target/ppc/mmu-hash64.c | 71 ++++++++++++++++++++--------------------- 1 file changed, 35 insertions(+), 36 deletions(-) diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index 127b7250ae..bb9ebeaf48 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -18,6 +18,7 @@ * License along with this library; if not, see . */ #include "qemu/osdep.h" +#include "qemu/units.h" #include "cpu.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" @@ -755,6 +756,39 @@ static void ppc_hash64_set_c(PowerPCCPU *cpu, hwaddr p= tex, uint64_t pte1) stb_phys(CPU(cpu)->as, base + offset, (pte1 & 0xff) | 0x80); } =20 +static target_ulong rmls_limit(PowerPCCPU *cpu) +{ + CPUPPCState *env =3D &cpu->env; + /* + * This is the full 4 bits encoding of POWER8. Previous + * CPUs only support a subset of these but the filtering + * is done when writing LPCR + */ + const target_ulong rma_sizes[] =3D { + [0] =3D 0, + [1] =3D 16 * GiB, + [2] =3D 1 * GiB, + [3] =3D 64 * MiB, + [4] =3D 256 * MiB, + [5] =3D 0, + [6] =3D 0, + [7] =3D 128 * MiB, + [8] =3D 32 * MiB, + }; + target_ulong rmls =3D (env->spr[SPR_LPCR] & LPCR_RMLS) >> LPCR_RMLS_SH= IFT; + + if (rmls < ARRAY_SIZE(rma_sizes)) { + return rma_sizes[rmls]; + } else { + /* + * Bad value, so the OS has shot itself in the foot. Return a + * 0-sized RMA which we expect to trigger an immediate DSI or + * ISI + */ + return 0; + } +} + int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx, int mmu_idx) { @@ -1004,41 +1038,6 @@ void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, targ= et_ulong ptex, cpu->env.tlb_need_flush =3D TLB_NEED_GLOBAL_FLUSH | TLB_NEED_LOCAL_FLU= SH; } =20 -static void ppc_hash64_update_rmls(PowerPCCPU *cpu) -{ - CPUPPCState *env =3D &cpu->env; - uint64_t lpcr =3D env->spr[SPR_LPCR]; - - /* - * This is the full 4 bits encoding of POWER8. Previous - * CPUs only support a subset of these but the filtering - * is done when writing LPCR - */ - switch ((lpcr & LPCR_RMLS) >> LPCR_RMLS_SHIFT) { - case 0x8: /* 32MB */ - env->rmls =3D 0x2000000ull; - break; - case 0x3: /* 64MB */ - env->rmls =3D 0x4000000ull; - break; - case 0x7: /* 128MB */ - env->rmls =3D 0x8000000ull; - break; - case 0x4: /* 256MB */ - env->rmls =3D 0x10000000ull; - break; - case 0x2: /* 1GB */ - env->rmls =3D 0x40000000ull; - break; - case 0x1: /* 16GB */ - env->rmls =3D 0x400000000ull; - break; - default: - /* What to do here ??? */ - env->rmls =3D 0; - } -} - static void ppc_hash64_update_vrma(PowerPCCPU *cpu) { CPUPPCState *env =3D &cpu->env; @@ -1097,7 +1096,7 @@ void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val) CPUPPCState *env =3D &cpu->env; =20 env->spr[SPR_LPCR] =3D val & pcc->lpcr_mask; - ppc_hash64_update_rmls(cpu); + env->rmls =3D rmls_limit(cpu); ppc_hash64_update_vrma(cpu); } =20 --=20 2.24.1 From nobody Tue May 14 09:04:22 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 158207432674128.172027113417244; Tue, 18 Feb 2020 17:05:26 -0800 (PST) Received: from localhost ([::1]:43844 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4Dnp-0006g0-Oq for importer@patchew.org; Tue, 18 Feb 2020 20:05:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37719) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4DdF-00017E-LI for qemu-devel@nongnu.org; Tue, 18 Feb 2020 19:54:30 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j4DdE-0001Ie-56 for qemu-devel@nongnu.org; Tue, 18 Feb 2020 19:54:29 -0500 Received: from bilbo.ozlabs.org ([203.11.71.1]:41267 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j4DdD-0001Ep-Q5; Tue, 18 Feb 2020 19:54:28 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 48MfPV2P6Qz9sSV; Wed, 19 Feb 2020 11:54:22 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1582073662; bh=QTAn3MwHqVdDYPUONyaaLwm+fOR67MMTI3JuQNUu9KM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PhNZdIz3T2SzmAlS7LMhzPT+20criArbsZCKDz7+tpIDx5881JHtEpr0AKJyPfE8O 7i0cZsKP65jPqyIrFl5AYUVwT1BEDKstrixfNWCqOlTenWT4Q2VQ5q7iTouRWjGzMk agNeANyNYbaxnuooEQS9l3tqWoxmhzgFrGxbApLw= From: David Gibson To: groug@kaod.org, philmd@redhat.com, qemu-devel@nongnu.org, clg@kaod.org Subject: [PATCH v3 09/12] target/ppc: Correct RMLS table Date: Wed, 19 Feb 2020 11:54:11 +1100 Message-Id: <20200219005414.15635-10-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200219005414.15635-1-david@gibson.dropbear.id.au> References: <20200219005414.15635-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, Mark Cave-Ayland , paulus@samba.org, qemu-ppc@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The table of RMA limits based on the LPCR[RMLS] field is slightly wrong. We're missing the RMLS =3D=3D 0 =3D> 256 GiB RMA option, which is available= on POWER8, so add that. The comment that goes with the table is much more wrong. We *don't* filter invalid RMLS values when writing the LPCR, and there's not really a sensible way to do so. Furthermore, while in theory the set of RMLS values is implementation dependent, it seems in practice the same set has been available since around POWER4+ up until POWER8, the last model which supports RMLS at all. So, correct that as well. Signed-off-by: David Gibson Reviewed-by: C=C3=A9dric Le Goater --- target/ppc/mmu-hash64.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index bb9ebeaf48..e6f24be93e 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -760,12 +760,12 @@ static target_ulong rmls_limit(PowerPCCPU *cpu) { CPUPPCState *env =3D &cpu->env; /* - * This is the full 4 bits encoding of POWER8. Previous - * CPUs only support a subset of these but the filtering - * is done when writing LPCR + * In theory the meanings of RMLS values are implementation + * dependent. In practice, this seems to have been the set from + * POWER4+..POWER8, and RMLS is no longer supported in POWER9. */ const target_ulong rma_sizes[] =3D { - [0] =3D 0, + [0] =3D 256 * GiB, [1] =3D 16 * GiB, [2] =3D 1 * GiB, [3] =3D 64 * MiB, --=20 2.24.1 From nobody Tue May 14 09:04:22 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582073828611493.2453403555702; Tue, 18 Feb 2020 16:57:08 -0800 (PST) Received: from localhost ([::1]:43732 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4Dfn-0005wD-JY for importer@patchew.org; Tue, 18 Feb 2020 19:57:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37725) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4DdF-00017F-OO for qemu-devel@nongnu.org; Tue, 18 Feb 2020 19:54:31 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j4DdE-0001Il-7D for qemu-devel@nongnu.org; Tue, 18 Feb 2020 19:54:29 -0500 Received: from bilbo.ozlabs.org ([203.11.71.1]:45041 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j4DdD-0001Et-Rc; Tue, 18 Feb 2020 19:54:28 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 48MfPV3qstz9sSR; Wed, 19 Feb 2020 11:54:22 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1582073662; bh=HirC5LnAA2uH/j722kBhQYsc7XAq/CG4RjWXhAM+wiE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IuAHvI0sUnj0MVnGCGbqXWx7VQq+OlAQhcTrLfUgVf14v3J1uhByBG3JuPHUUoWJq kJRJz1I0dWarIH97w272e2/AtL8vzzfU1LdkEsUUGAyrLDXDIlRpnL3tzMNUyBcgkZ S3bO00SnwMKLuhtXb7l+YloLNiFygKZO96u6XR+8= From: David Gibson To: groug@kaod.org, philmd@redhat.com, qemu-devel@nongnu.org, clg@kaod.org Subject: [PATCH v3 10/12] target/ppc: Only calculate RMLS derived RMA limit on demand Date: Wed, 19 Feb 2020 11:54:12 +1100 Message-Id: <20200219005414.15635-11-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200219005414.15635-1-david@gibson.dropbear.id.au> References: <20200219005414.15635-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, Mark Cave-Ayland , paulus@samba.org, qemu-ppc@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" When the LPCR is written, we update the env->rmls field with the RMA limit it implies. Simplify things by just calculating the value directly from the LPCR value when we need it. It's possible this is a little slower, but it's unlikely to be significant, since this is only for real mode accesses in a translation configuration that's not used very often, and the whole thing is behind the qemu TLB anyway. Therefore, keeping the number of state variables down and not having to worry about making sure it's always in sync seems the better option. Signed-off-by: David Gibson Reviewed-by: C=C3=A9dric Le Goater --- target/ppc/cpu.h | 1 - target/ppc/mmu-hash64.c | 8 +++++--- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 8077fdb068..f9871b1233 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1046,7 +1046,6 @@ struct CPUPPCState { uint64_t insns_flags2; #if defined(TARGET_PPC64) ppc_slb_t vrma_slb; - target_ulong rmls; #endif =20 int error_code; diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index e6f24be93e..170a78bd2e 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -842,8 +842,10 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr= eaddr, =20 goto skip_slb_search; } else { + target_ulong limit =3D rmls_limit(cpu); + /* Emulated old-style RMO mode, bounds check against RMLS */ - if (raddr >=3D env->rmls) { + if (raddr >=3D limit) { if (rwx =3D=3D 2) { ppc_hash64_set_isi(cs, SRR1_PROTFAULT); } else { @@ -1005,8 +1007,9 @@ hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu= , target_ulong addr) return -1; } } else { + target_ulong limit =3D rmls_limit(cpu); /* Emulated old-style RMO mode, bounds check against RMLS */ - if (raddr >=3D env->rmls) { + if (raddr >=3D limit) { return -1; } return raddr | env->spr[SPR_RMOR]; @@ -1096,7 +1099,6 @@ void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val) CPUPPCState *env =3D &cpu->env; =20 env->spr[SPR_LPCR] =3D val & pcc->lpcr_mask; - env->rmls =3D rmls_limit(cpu); ppc_hash64_update_vrma(cpu); } =20 --=20 2.24.1 From nobody Tue May 14 09:04:22 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 15820742599613.5702817409808176; Tue, 18 Feb 2020 17:04:19 -0800 (PST) Received: from localhost ([::1]:43834 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4Dmk-0005k7-U7 for importer@patchew.org; Tue, 18 Feb 2020 20:04:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37727) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4DdF-00017G-P1 for qemu-devel@nongnu.org; Tue, 18 Feb 2020 19:54:31 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j4DdE-0001Ir-9g for qemu-devel@nongnu.org; Tue, 18 Feb 2020 19:54:29 -0500 Received: from bilbo.ozlabs.org ([203.11.71.1]:56125 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j4DdD-0001Ev-Tx; Tue, 18 Feb 2020 19:54:28 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 48MfPV5vDXz9sSX; Wed, 19 Feb 2020 11:54:22 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1582073662; bh=+jNmPKQFwt6qcFTEPaXoxgeQZgx5X3I9Q0aV8FzdT9Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=p58SB0+yXgCDBD/TflqfiWMbkZ8wQv87uiQtkn1ELXxUIZsYDGjObu+xaAlFE+Qwy 2El8U3lglyJK975Sn4MfCD06aQmvqz6fMBmDVvNICsAUjDPJUIn0hYOa7GpXqrglFd or9XsYtKOTjnTpH3Us4INVuaFo6Db1+Wsqov2a3M= From: David Gibson To: groug@kaod.org, philmd@redhat.com, qemu-devel@nongnu.org, clg@kaod.org Subject: [PATCH v3 11/12] target/ppc: Streamline construction of VRMA SLB entry Date: Wed, 19 Feb 2020 11:54:13 +1100 Message-Id: <20200219005414.15635-12-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200219005414.15635-1-david@gibson.dropbear.id.au> References: <20200219005414.15635-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, Mark Cave-Ayland , paulus@samba.org, qemu-ppc@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" When in VRMA mode (i.e. a guest thinks it has the MMU off, but the hypervisor is still applying translation) we use a special SLB entry, rather than looking up an SLBE by address as we do when guest translation is on. We build that special entry in ppc_hash64_update_vrma() along with some logic for handling some non-VRMA cases. Split the actual build of the VRMA SLBE into a separate helper and streamline it a bit. Signed-off-by: David Gibson --- target/ppc/mmu-hash64.c | 79 ++++++++++++++++++++--------------------- 1 file changed, 38 insertions(+), 41 deletions(-) diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index 170a78bd2e..06cfff9860 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -789,6 +789,39 @@ static target_ulong rmls_limit(PowerPCCPU *cpu) } } =20 +static int build_vrma_slbe(PowerPCCPU *cpu, ppc_slb_t *slb) +{ + CPUPPCState *env =3D &cpu->env; + target_ulong lpcr =3D env->spr[SPR_LPCR]; + uint32_t vrmasd =3D (lpcr & LPCR_VRMASD) >> LPCR_VRMASD_SHIFT; + target_ulong vsid =3D SLB_VSID_VRMA | ((vrmasd << 4) & SLB_VSID_LLP_MA= SK); + int i; + + /* + * Make one up. Mostly ignore the ESID which will not be needed + * for translation + */ + for (i =3D 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { + const PPCHash64SegmentPageSizes *sps =3D &cpu->hash64_opts->sps[i]; + + if (!sps->page_shift) { + break; + } + + if ((vsid & SLB_VSID_LLP_MASK) =3D=3D sps->slb_enc) { + slb->esid =3D SLB_ESID_V; + slb->vsid =3D vsid; + slb->sps =3D sps; + return 0; + } + } + + error_report("Bad page size encoding in LPCR[VRMASD]; LPCR=3D0x" + TARGET_FMT_lx"\n", lpcr); + + return -1; +} + int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx, int mmu_idx) { @@ -1044,53 +1077,17 @@ void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, tar= get_ulong ptex, static void ppc_hash64_update_vrma(PowerPCCPU *cpu) { CPUPPCState *env =3D &cpu->env; - const PPCHash64SegmentPageSizes *sps =3D NULL; - target_ulong esid, vsid, lpcr; ppc_slb_t *slb =3D &env->vrma_slb; - uint32_t vrmasd; - int i; - - /* First clear it */ - slb->esid =3D slb->vsid =3D 0; - slb->sps =3D NULL; =20 /* Is VRMA enabled ? */ if (ppc_hash64_use_vrma(env)) { - return; - } - - /* - * Make one up. Mostly ignore the ESID which will not be needed - * for translation - */ - lpcr =3D env->spr[SPR_LPCR]; - vsid =3D SLB_VSID_VRMA; - vrmasd =3D (lpcr & LPCR_VRMASD) >> LPCR_VRMASD_SHIFT; - vsid |=3D (vrmasd << 4) & (SLB_VSID_L | SLB_VSID_LP); - esid =3D SLB_ESID_V; - - for (i =3D 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { - const PPCHash64SegmentPageSizes *sps1 =3D &cpu->hash64_opts->sps[i= ]; - - if (!sps1->page_shift) { - break; - } - - if ((vsid & SLB_VSID_LLP_MASK) =3D=3D sps1->slb_enc) { - sps =3D sps1; - break; - } - } - - if (!sps) { - error_report("Bad page size encoding esid 0x"TARGET_FMT_lx - " vsid 0x"TARGET_FMT_lx, esid, vsid); - return; + if (build_vrma_slbe(cpu, slb) =3D=3D 0) + return; } =20 - slb->vsid =3D vsid; - slb->esid =3D esid; - slb->sps =3D sps; + /* Otherwise, clear it to indicate error */ + slb->esid =3D slb->vsid =3D 0; + slb->sps =3D NULL; } =20 void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val) --=20 2.24.1 From nobody Tue May 14 09:04:22 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582073939297124.25851477727349; Tue, 18 Feb 2020 16:58:59 -0800 (PST) Received: from localhost ([::1]:43752 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4Dha-0000oO-9P for importer@patchew.org; Tue, 18 Feb 2020 19:58:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37756) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4DdG-00017o-Cp for qemu-devel@nongnu.org; Tue, 18 Feb 2020 19:54:31 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j4DdE-0001JU-Uj for qemu-devel@nongnu.org; Tue, 18 Feb 2020 19:54:30 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:43469 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j4DdE-0001FY-HP; Tue, 18 Feb 2020 19:54:28 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 48MfPV6njYz9sSY; Wed, 19 Feb 2020 11:54:22 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1582073662; bh=WcopKWbeJrTfAJK2is2PCME4szvJP+9rw9WA+6Ed6OY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HkNQMOxChb01BQDZmxNaCFH5p9Wco1zkyTey78x0zK2MvO8kffJq1N9964sPvKuLd EoruMPCULVDUosPRvU92oQmG1AO4Fwz0+z5LejT/xmfUVZblj7CpRKxK4XLpLiOi0R D+8FgaRMz+s1N3go7yv7AFAq7VWBiFb0TnLgrjs4= From: David Gibson To: groug@kaod.org, philmd@redhat.com, qemu-devel@nongnu.org, clg@kaod.org Subject: [PATCH v3 12/12] target/ppc: Don't store VRMA SLBE persistently Date: Wed, 19 Feb 2020 11:54:14 +1100 Message-Id: <20200219005414.15635-13-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200219005414.15635-1-david@gibson.dropbear.id.au> References: <20200219005414.15635-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, Mark Cave-Ayland , paulus@samba.org, qemu-ppc@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Currently, we construct the SLBE used for VRMA translations when the LPCR is written (which controls some bits in the SLBE), then use it later for translations. This is a bit complex and confusing - simplify it by simply constructing the SLBE directly from the LPCR when we need it. Signed-off-by: David Gibson --- target/ppc/cpu.h | 3 --- target/ppc/mmu-hash64.c | 27 ++++++--------------------- 2 files changed, 6 insertions(+), 24 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index f9871b1233..5a55fb02bd 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1044,9 +1044,6 @@ struct CPUPPCState { uint32_t flags; uint64_t insns_flags; uint64_t insns_flags2; -#if defined(TARGET_PPC64) - ppc_slb_t vrma_slb; -#endif =20 int error_code; uint32_t pending_interrupts; diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index 06cfff9860..d93dcf3a08 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -827,6 +827,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr = eaddr, { CPUState *cs =3D CPU(cpu); CPUPPCState *env =3D &cpu->env; + ppc_slb_t vrma_slbe; ppc_slb_t *slb; unsigned apshift; hwaddr ptex; @@ -865,8 +866,8 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr = eaddr, } } else if (ppc_hash64_use_vrma(env)) { /* Emulated VRMA mode */ - slb =3D &env->vrma_slb; - if (!slb->sps) { + slb =3D &vrma_slbe; + if (build_vrma_slbe(cpu, slb) !=3D 0) { /* Invalid VRMA setup, machine check */ cs->exception_index =3D POWERPC_EXCP_MCHECK; env->error_code =3D 0; @@ -1014,6 +1015,7 @@ skip_slb_search: hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr) { CPUPPCState *env =3D &cpu->env; + ppc_slb_t vrma_slbe; ppc_slb_t *slb; hwaddr ptex, raddr; ppc_hash_pte64_t pte; @@ -1035,8 +1037,8 @@ hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu= , target_ulong addr) return raddr | env->spr[SPR_HRMOR]; } else if (ppc_hash64_use_vrma(env)) { /* Emulated VRMA mode */ - slb =3D &env->vrma_slb; - if (!slb->sps) { + slb =3D &vrma_slbe; + if (build_vrma_slbe(cpu, slb) !=3D 0) { return -1; } } else { @@ -1074,29 +1076,12 @@ void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, tar= get_ulong ptex, cpu->env.tlb_need_flush =3D TLB_NEED_GLOBAL_FLUSH | TLB_NEED_LOCAL_FLU= SH; } =20 -static void ppc_hash64_update_vrma(PowerPCCPU *cpu) -{ - CPUPPCState *env =3D &cpu->env; - ppc_slb_t *slb =3D &env->vrma_slb; - - /* Is VRMA enabled ? */ - if (ppc_hash64_use_vrma(env)) { - if (build_vrma_slbe(cpu, slb) =3D=3D 0) - return; - } - - /* Otherwise, clear it to indicate error */ - slb->esid =3D slb->vsid =3D 0; - slb->sps =3D NULL; -} - void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val) { PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cpu); CPUPPCState *env =3D &cpu->env; =20 env->spr[SPR_LPCR] =3D val & pcc->lpcr_mask; - ppc_hash64_update_vrma(cpu); } =20 void helper_store_lpcr(CPUPPCState *env, target_ulong val) --=20 2.24.1