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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id i68sm5139399pfe.173.2020.02.18.11.10.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Feb 2020 11:10:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=macsUf7RwNXBE0fmKKCjQlSCUWHuv/3Gu30XsvyGcpY=; b=ap0lFfBawvYsao7AIava1O4L4J8JPIPlsgvKjLKk/m5K5/K6dRHpWbzlRkGL52Tr1l jYY/jCvZR2BGfEwmRv1iecNjZ19mAJA7O0zP5UdSsdv3yvWZQilzWwqSM+NcE/dss3y9 RPjuQ8zG6DiR4KK6YDpdFD6qnBY8uwkwnIhJsLVVvlGcCAW0TNwsmjeGXUA0E8gly8li XnNfswl1eAgkgWM0AqbkaWhtK2Xh0kfA5GLG/utz9bvhge95lWk9Q+ZHf/DjqASJsq9o Pclnq9mSd2dcKuGTuajCSJqo2mNjY6h5QMES8U4ylqvI/OT0ihUVCy31I+ufZdYtSJd+ DbGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=macsUf7RwNXBE0fmKKCjQlSCUWHuv/3Gu30XsvyGcpY=; b=Yo0pi1GITZLwDGvVTLWUgLDbwEQvc1KPot6RQd3Ci59lnvwoKpV8+k9QFBn1T+H/4q nu0LzHj/qSD0hW4Kz18ZhEBRxHZqSTaKFh71Uxpv6CFAx9s6bAF5k2MVQso1Sk9KbieF 7arooNuSqIw26TYSOAhkGc8RkqTyNb4Fumc7LrC6lOFjl6ODHjqDU3eIGISSORRHEPZn FWLanuYWAQZFcFGmStemxi+axFAUIeY1UzrhGGfvT9DjwbHsrY+UjZZ7pPr3UBW2dK7o uJcpt4EzxFdIObG6fCjMlHdbGuegEZZ84snv54FssK6l4rGd8BTN8lUdAmNydZ0YXAlG fX0w== X-Gm-Message-State: APjAAAVtr1r57L0oXHKJDtWonaeFQw0oj3lbniPJrr7aLgMgv7WFlYni l4FYlpkm7DrkrmAzHLhkrVBL1ZYpAZc= X-Google-Smtp-Source: APXvYqzH8k4Ah+pjVnB7hJ6NAis1rFo0mgIAAOzKA+kivGUT4336d3QE8iYPFKFftdUAwcPx2xo5xA== X-Received: by 2002:a17:90a:5285:: with SMTP id w5mr4470243pjh.77.1582053006040; Tue, 18 Feb 2020 11:10:06 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 4/7] target/arm: Honor the HCR_EL2.TACR bit Date: Tue, 18 Feb 2020 11:09:55 -0800 Message-Id: <20200218190958.745-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200218190958.745-1-richard.henderson@linaro.org> References: <20200218190958.745-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1042 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" This bit traps EL1 access to the auxiliary control registers. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index dc99ee5d18..52b6e68659 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -553,6 +553,16 @@ static CPAccessResult access_tsw(CPUARMState *env, con= st ARMCPRegInfo *ri, return CP_ACCESS_OK; } =20 +/* Check for traps from EL1 due to HCR_EL2.TACR. */ +static CPAccessResult access_tacr(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + if (arm_current_el(env) =3D=3D 1 && (arm_hcr_el2_eff(env) & HCR_TACR))= { + return CP_ACCESS_TRAP_EL2; + } + return CP_ACCESS_OK; +} + static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t = value) { ARMCPU *cpu =3D env_archcpu(env); @@ -6911,8 +6921,8 @@ static const ARMCPRegInfo ats1cp_reginfo[] =3D { static const ARMCPRegInfo actlr2_hactlr2_reginfo[] =3D { { .name =3D "ACTLR2", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 =3D 3, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, + .access =3D PL1_RW, .accessfn =3D access_tacr, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "HACTLR2", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 4, .crn =3D 1, .crm =3D 0, .opc2 =3D 3, .access =3D PL2_RW, .type =3D ARM_CP_CONST, @@ -7668,8 +7678,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) ARMCPRegInfo auxcr_reginfo[] =3D { { .name =3D "ACTLR_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 =3D = 1, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D cpu->reset_auxcr }, + .access =3D PL1_RW, .accessfn =3D access_tacr, + .type =3D ARM_CP_CONST, .resetvalue =3D cpu->reset_auxcr }, { .name =3D "ACTLR_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 0, .opc2 =3D = 1, .access =3D PL2_RW, .type =3D ARM_CP_CONST, --=20 2.20.1