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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id i68sm5139399pfe.173.2020.02.18.11.10.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Feb 2020 11:10:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/9wXoDEsxSRqmYUkdBOvS37ZtLP9FiINAczvKHAmVVI=; b=aEHSaFmaqt9CFosgT/kRgfwaWvMLlgf5q66LGeQpwPZ5HnyvrtsdP4PSUY/eK+UwRW P+JG2oHhdfvb2Gmcrr1BjAMmtV8STZL9o3ulG10eNKdXLq1DYg8Vklo2chMa0bGln01Z 07oT1VwpjM76KnjAy9OODZ8XpoBg2VzICDjTjVp3hzh7But+dFfk1ex/5SLhrwtSOL58 UsSWjkJnMMJB7yVmbRPP9OV/dMwbTspDbcfh1HBbo6yBEgttNDktUdqyuPgHdG9nzZLi SYuxaf/Zd96gCUeB45PeX/pBHwtDYpjdwGLpeE3eijJfEosEbx0AvuHztjX45A2l6Bwd G75g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/9wXoDEsxSRqmYUkdBOvS37ZtLP9FiINAczvKHAmVVI=; b=exHpOPpeAzFmus7h9XF21XXoS8z8mOURGbpixWf6TcBpLSUFaICtO2BY+2Aum7VaeN ZnOTvdNEEUl2Z24wc7iubfM5fdpRC/t6X3yH3Ds3Vg48bUTVR3ukrTnnZQawx6cWI9bT D30kfplgexpIfx+/dghnZR8Lm1zwEjlOio+U9f4oTV6lNb4lCN43FAGViIc3q2x7BZGj GuGxPFbmWfleq72zjy0tK1Xo1adWZwuzI4NROD1JAHQ2Dnl/0dJ9w2KDqOhYRbrHBHGC LZGMN71ri4skA8TNt6gzDYLKaovMPtrXRpckN6X69d/RUUONaaEnt1C7j3ygbmo4/wIb eGRw== X-Gm-Message-State: APjAAAVtedhv+7RP4jBnn4DE4ehxZRd9dtrsCKnOKOyEurR4eGCIV8uE vtBrnt4C0t+/ISlOloOcQ7bQKupwfQc= X-Google-Smtp-Source: APXvYqw78+9JNq5dLj/70koAtgEhQWjUo19WlAolc4YYqKQDmXz7fJEobq20fRNUZFpa14eAA1iVqg== X-Received: by 2002:a62:6409:: with SMTP id y9mr22994459pfb.30.1582053002266; Tue, 18 Feb 2020 11:10:02 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 1/7] target/arm: Set ID_MMFR4.HPDS for aarch64_max_initfn Date: Tue, 18 Feb 2020 11:09:52 -0800 Message-Id: <20200218190958.745-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200218190958.745-1-richard.henderson@linaro.org> References: <20200218190958.745-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" We had set this for aarch32-only in arm_max_initfn, but failed to set the same bit for aarch64. Signed-off-by: Richard Henderson --- target/arm/cpu64.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 32cf8ee98b..32c3e24a3d 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -704,6 +704,7 @@ static void aarch64_max_initfn(Object *obj) cpu->isar.id_mmfr3 =3D u; =20 u =3D cpu->isar.id_mmfr4; + u =3D FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */ u =3D FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 implemen= ted */ cpu->isar.id_mmfr4 =3D u; =20 --=20 2.20.1 From nobody Thu Nov 13 17:44:03 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582053556842218.54141264044745; Tue, 18 Feb 2020 11:19:16 -0800 (PST) Received: from localhost ([::1]:40652 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j48Op-0000AQ-PB for importer@patchew.org; Tue, 18 Feb 2020 14:19:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46780) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j48Fz-0004vh-D9 for qemu-devel@nongnu.org; Tue, 18 Feb 2020 14:10:09 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j48Fx-0001nd-D6 for qemu-devel@nongnu.org; Tue, 18 Feb 2020 14:10:07 -0500 Received: from mail-pf1-x443.google.com ([2607:f8b0:4864:20::443]:46949) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j48Fx-0001m8-5f for qemu-devel@nongnu.org; Tue, 18 Feb 2020 14:10:05 -0500 Received: by mail-pf1-x443.google.com with SMTP id k29so11103541pfp.13 for ; Tue, 18 Feb 2020 11:10:05 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id i68sm5139399pfe.173.2020.02.18.11.10.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Feb 2020 11:10:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FW5hSe916aupkvtDNQI+gZPx6BhoZSiZ4PytdS9WQ+4=; b=quiu2gw525H+gdDWWgK2j93Bg3hyUPi1l+l14rwpRmY7jp/fQzQ29G/+1Tw6WOCzKY 1Oo11Ph4nDZ6oconIFHQdmd6XGlWGb+r5bFXjbEfzGcO0wrhJk3KSzfA0ms6OMsUH7LV OPCcMjvUChNw4z+vZDr1zjBYux97HGcJOkYmH+9jFSDSE4/5Bf50xkoXnaD47fEQm0fp YnNdGOA6tmRHnOhogA4aKMhIPCkiKxNZJNmLGo79CKPQtazk2QUl2KYuMR0DV15BRBLT muMUWjwQ2GKfRjyb0ffNWUlIolpof1Yo5eLHalT5DGhQjTtOWI7+ri+YV05mjkICFjH9 B6gA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FW5hSe916aupkvtDNQI+gZPx6BhoZSiZ4PytdS9WQ+4=; b=fPVuX2QFdPqxBGQdsT/65P1Cty0QpTqQqp/Q+0hv8+LMFnoKyrB6Sr4mEGEhhNQQ/c StI2ZQeegLccwmHJ7aPvHpkpQROBq695fjeHrSWc9DoRlFoPjxhiICQEsVIHeYz59EUY O4h+Hr4TLELTaQ3Ga1duqvzopp5cHj0Sq+iNHKmB/o71EadTZVc8SUuPQRKJNc9TVmpK 7WggqvZIXIndUp1Pm1tUYiv2QaN0UnXK1xQyfI1PYTPeiUvaBk6lCdFD1gznkYdHi5MX NywlV+KY+6YisSGlG1r1SB2RuQoBx/Q5cBtjk2OfgK6ZBcgrmzmv+XYyEwyxYZWbGFSM /+1w== X-Gm-Message-State: APjAAAWJhTAhcIzBX9Me+y0uwNzoGJ9Aj0caBjy7zlbEpl0oSs2JHAIC w9qBdciSwSFGdslW2hdoeg7VNGPjiMA= X-Google-Smtp-Source: APXvYqzfNsCmVeuccvPR4ZKP3utam2upouwyfW8w+KW/oCyxH13UBjFN08Vg2S5kbmRuDb04OSp46g== X-Received: by 2002:a63:ba43:: with SMTP id l3mr25364582pgu.120.1582053003565; Tue, 18 Feb 2020 11:10:03 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 2/7] target/arm: Honor the HCR_EL2.{TVM,TRVM} bits Date: Tue, 18 Feb 2020 11:09:53 -0800 Message-Id: <20200218190958.745-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200218190958.745-1-richard.henderson@linaro.org> References: <20200218190958.745-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" These bits trap EL1 access to various virtual memory controls. Buglink: https://bugs.launchpad.net/bugs/1855072 Signed-off-by: Richard Henderson --- v2: Include TTBCR. --- target/arm/helper.c | 77 ++++++++++++++++++++++++++++++--------------- 1 file changed, 52 insertions(+), 25 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 513f4edbb4..8abbc4e991 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -530,6 +530,19 @@ static CPAccessResult access_tpm(CPUARMState *env, con= st ARMCPRegInfo *ri, return CP_ACCESS_OK; } =20 +/* Check for traps from EL1 due to HCR_EL2.TVM and HCR_EL2.TRVM. */ +static CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo= *ri, + bool isread) +{ + if (arm_current_el(env) =3D=3D 1) { + uint64_t trap =3D isread ? HCR_TRVM : HCR_TVM; + if (arm_hcr_el2_eff(env) & trap) { + return CP_ACCESS_TRAP_EL2; + } + } + return CP_ACCESS_OK; +} + static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t = value) { ARMCPU *cpu =3D env_archcpu(env); @@ -785,7 +798,8 @@ static const ARMCPRegInfo cp_reginfo[] =3D { */ { .name =3D "CONTEXTIDR_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 13, .crm =3D 0, .opc2 =3D 1, - .access =3D PL1_RW, .secure =3D ARM_CP_SECSTATE_NS, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .secure =3D ARM_CP_SECSTATE_NS, .fieldoffset =3D offsetof(CPUARMState, cp15.contextidr_el[1]), .resetvalue =3D 0, .writefn =3D contextidr_write, .raw_writefn =3D r= aw_write, }, { .name =3D "CONTEXTIDR_S", .state =3D ARM_CP_STATE_AA32, @@ -877,9 +891,11 @@ static const ARMCPRegInfo not_v7_cp_reginfo[] =3D { .opc1 =3D CP_ANY, .opc2 =3D 3, .access =3D PL1_W, .writefn =3D tlbim= vaa_write, .type =3D ARM_CP_NO_RAW }, { .name =3D "PRRR", .cp =3D 15, .crn =3D 10, .crm =3D 2, - .opc1 =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .type =3D ARM_CP_NOP }, + .opc1 =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_t= vm_trvm, + .type =3D ARM_CP_NOP }, { .name =3D "NMRR", .cp =3D 15, .crn =3D 10, .crm =3D 2, - .opc1 =3D 0, .opc2 =3D 1, .access =3D PL1_RW, .type =3D ARM_CP_NOP }, + .opc1 =3D 0, .opc2 =3D 1, .access =3D PL1_RW, .accessfn =3D access_t= vm_trvm, + .type =3D ARM_CP_NOP }, REGINFO_SENTINEL }; =20 @@ -997,7 +1013,7 @@ static const ARMCPRegInfo v6_cp_reginfo[] =3D { { .name =3D "DMB", .cp =3D 15, .crn =3D 7, .crm =3D 10, .opc1 =3D 0, .= opc2 =3D 5, .access =3D PL0_W, .type =3D ARM_CP_NOP }, { .name =3D "IFAR", .cp =3D 15, .crn =3D 6, .crm =3D 0, .opc1 =3D 0, .= opc2 =3D 2, - .access =3D PL1_RW, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ifar_s), offsetof(CPUARMState, cp15.ifar_ns) }, .resetvalue =3D 0, }, @@ -2209,16 +2225,19 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { */ { .name =3D "AFSR0_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 5, .crm =3D 1, .opc2 =3D 0, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "AFSR1_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 5, .crm =3D 1, .opc2 =3D 1, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, /* MAIR can just read-as-written because we don't implement caches * and so don't need to care about memory attributes. */ { .name =3D "MAIR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 2, .opc2 =3D 0, - .access =3D PL1_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.mair= _el[1]), + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .fieldoffset =3D offsetof(CPUARMState, cp15.mair_el[1]), .resetvalue =3D 0 }, { .name =3D "MAIR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 10, .crm =3D 2, .opc2 =3D 0, @@ -2232,12 +2251,14 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { * handled in the field definitions. */ { .name =3D "MAIR0", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 0, .crn =3D 10, .crm =3D 2, .opc2 =3D 0, .acce= ss =3D PL1_RW, + .cp =3D 15, .opc1 =3D 0, .crn =3D 10, .crm =3D 2, .opc2 =3D 0, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.mair0_s), offsetof(CPUARMState, cp15.mair0_ns) }, .resetfn =3D arm_cp_reset_ignore }, { .name =3D "MAIR1", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 0, .crn =3D 10, .crm =3D 2, .opc2 =3D 1, .acce= ss =3D PL1_RW, + .cp =3D 15, .opc1 =3D 0, .crn =3D 10, .crm =3D 2, .opc2 =3D 1, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.mair1_s), offsetof(CPUARMState, cp15.mair1_ns) }, .resetfn =3D arm_cp_reset_ignore }, @@ -3887,20 +3908,21 @@ static void vttbr_write(CPUARMState *env, const ARM= CPRegInfo *ri, =20 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] =3D { { .name =3D "DFSR", .cp =3D 15, .crn =3D 5, .crm =3D 0, .opc1 =3D 0, .= opc2 =3D 0, - .access =3D PL1_RW, .type =3D ARM_CP_ALIAS, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .type =3D ARM_CP_= ALIAS, .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.dfsr_s), offsetoflow32(CPUARMState, cp15.dfsr_ns) }, }, { .name =3D "IFSR", .cp =3D 15, .crn =3D 5, .crm =3D 0, .opc1 =3D 0, .= opc2 =3D 1, - .access =3D PL1_RW, .resetvalue =3D 0, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .resetvalue =3D 0, .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.ifsr_s), offsetoflow32(CPUARMState, cp15.ifsr_ns) } }, { .name =3D "DFAR", .cp =3D 15, .opc1 =3D 0, .crn =3D 6, .crm =3D 0, .= opc2 =3D 0, - .access =3D PL1_RW, .resetvalue =3D 0, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .resetvalue =3D 0, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.dfar_s), offsetof(CPUARMState, cp15.dfar_ns) } }, { .name =3D "FAR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .crn =3D 6, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 0, - .access =3D PL1_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.far_= el[1]), + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .fieldoffset =3D offsetof(CPUARMState, cp15.far_el[1]), .resetvalue =3D 0, }, REGINFO_SENTINEL }; @@ -3908,25 +3930,29 @@ static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = =3D { static const ARMCPRegInfo vmsa_cp_reginfo[] =3D { { .name =3D "ESR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .crn =3D 5, .crm =3D 2, .opc1 =3D 0, .opc2 =3D 0, - .access =3D PL1_RW, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .fieldoffset =3D offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = =3D 0, }, { .name =3D "TTBR0_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 0, .opc2 =3D 0, - .access =3D PL1_RW, .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr0_s), offsetof(CPUARMState, cp15.ttbr0_ns) } }, { .name =3D "TTBR1_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 0, .opc2 =3D 1, - .access =3D PL1_RW, .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr1_s), offsetof(CPUARMState, cp15.ttbr1_ns) } }, { .name =3D "TCR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .crn =3D 2, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 2, - .access =3D PL1_RW, .writefn =3D vmsa_tcr_el12_write, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .writefn =3D vmsa_tcr_el12_write, .resetfn =3D vmsa_ttbcr_reset, .raw_writefn =3D raw_write, .fieldoffset =3D offsetof(CPUARMState, cp15.tcr_el[1]) }, { .name =3D "TTBCR", .cp =3D 15, .crn =3D 2, .crm =3D 0, .opc1 =3D 0, = .opc2 =3D 2, - .access =3D PL1_RW, .type =3D ARM_CP_ALIAS, .writefn =3D vmsa_ttbcr_= write, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .type =3D ARM_CP_ALIAS, .writefn =3D vmsa_ttbcr_write, .raw_writefn =3D vmsa_ttbcr_raw_write, .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.tcr_el[3]), offsetoflow32(CPUARMState, cp15.tcr_el[1])} }, @@ -3938,7 +3964,8 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] =3D { */ static const ARMCPRegInfo ttbcr2_reginfo =3D { .name =3D "TTBCR2", .cp =3D 15, .opc1 =3D 0, .crn =3D 2, .crm =3D 0, .= opc2 =3D 3, - .access =3D PL1_RW, .type =3D ARM_CP_ALIAS, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .type =3D ARM_CP_ALIAS, .bank_fieldoffsets =3D { offsetofhigh32(CPUARMState, cp15.tcr_el[3]), offsetofhigh32(CPUARMState, cp15.tcr_el[1]) }, }; @@ -4158,12 +4185,12 @@ static const ARMCPRegInfo lpae_cp_reginfo[] =3D { /* NOP AMAIR0/1 */ { .name =3D "AMAIR0", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 10, .crm =3D 3, .opc1 =3D 0, .opc2 =3D 0, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, /* AMAIR1 is mapped to AMAIR_EL1[63:32] */ { .name =3D "AMAIR1", .cp =3D 15, .crn =3D 10, .crm =3D 3, .opc1 =3D 0= , .opc2 =3D 1, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "PAR", .cp =3D 15, .crm =3D 7, .opc1 =3D 0, .access =3D PL1_RW, .type =3D ARM_CP_64BIT, .resetvalue =3D 0, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.par_s), @@ -4889,7 +4916,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .type =3D ARM_CP_NOP, .access =3D PL1_W }, /* MMU Domain access control / MPU write buffer control */ { .name =3D "DACR", .cp =3D 15, .opc1 =3D 0, .crn =3D 3, .crm =3D 0, .= opc2 =3D 0, - .access =3D PL1_RW, .resetvalue =3D 0, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .resetvalue =3D 0, .writefn =3D dacr_write, .raw_writefn =3D raw_write, .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.dacr_s), offsetoflow32(CPUARMState, cp15.dacr_ns) } }, @@ -7716,7 +7743,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) ARMCPRegInfo sctlr =3D { .name =3D "SCTLR", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 =3D 0, - .access =3D PL1_RW, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.sctlr_s), offsetof(CPUARMState, cp15.sctlr_ns) }, .writefn =3D sctlr_write, .resetvalue =3D cpu->reset_sctlr, --=20 2.20.1 From nobody Thu Nov 13 17:44:03 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id i68sm5139399pfe.173.2020.02.18.11.10.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Feb 2020 11:10:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=aT+wiWpglSLXunTwVoN4RPF1V0ishR6Qd0crZF3h7bM=; b=v8QubRibTLDCjL+qLjfh4h5/fAFDbGbXAy+5GhWoynru3nPS/7itzgaySkz1lo+GyN mTGRwKAbgDSCkvdEcncMXlvGPg4uyjmFTQmI6adYie4q3gPeTQnroRKNAKEFBUMZQpbV TPMawS9kxVptSWmGKWyD/n4io81KMAyehUuuOCxm6kGpgUeXN+1U0GSgIBCeixvvKYiS yisNbxm9QIqfN1KL0+WEPlLaII5qR1bGAirvYjmUllO5+rziLR+Ymuui0MwPbUZgluBp XrFejTmOqHnqQF0arcbtMI8a6LnHcL7Q1qkpIS5fCrPqfrJsvaHiRzR3uwHWkaj904r1 +Wow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aT+wiWpglSLXunTwVoN4RPF1V0ishR6Qd0crZF3h7bM=; b=k0VC4UzoqsFa2O+ZIWNjf3yywIj2fkJoqXb8oJND+tFjYujWXHWjqrzRyr1+f988S3 50at6s3tN9HfSTGlLHkjRtTjRPxXP7Utim1u4wWXJEjm8ypwg4PSW8ht6VhpCIoZu753 3tCgVrZi7FmP7E9nVAveL7Z9xhxkOCqnm+Zq3/nEmEinQi6WeE346oz+kFe1d1YDMKGh /O9rIEtZomu4AMZJLmu/GKzS9IPFYb3PPrH6+0/mg//Dpn8n4le28IfLHPBxWgULDfmz p+8AMsP8vNzqx/srwpyBErQGdSC+GERzrozD4UTKJy/slM6afjJhcAIuheAZfYNwscMS 1DFA== X-Gm-Message-State: APjAAAULjkJunFR8+rBJC0rSdJjfOQAdcQ2X9kgk3Y2uSmgvKOO2VObg da56EkhtNW11SZtHAr7VMP4poCfrLD0= X-Google-Smtp-Source: APXvYqw9lMmpHB+AuvsnhQK/a7smajrUmpW8r9J8QMP0nG+5jc58Yshk6fgwLpiIgNRIDf0qAdE9pA== X-Received: by 2002:a17:90a:fa8d:: with SMTP id cu13mr4328683pjb.68.1582053004856; Tue, 18 Feb 2020 11:10:04 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 3/7] target/arm: Honor the HCR_EL2.TSW bit Date: Tue, 18 Feb 2020 11:09:54 -0800 Message-Id: <20200218190958.745-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200218190958.745-1-richard.henderson@linaro.org> References: <20200218190958.745-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1041 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" These bits trap EL1 access to set/way cache maintenance insns. Buglink: https://bugs.launchpad.net/bugs/1863685 Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.c | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 8abbc4e991..dc99ee5d18 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -543,6 +543,16 @@ static CPAccessResult access_tvm_trvm(CPUARMState *env= , const ARMCPRegInfo *ri, return CP_ACCESS_OK; } =20 +/* Check for traps from EL1 due to HCR_EL2.TSW. */ +static CPAccessResult access_tsw(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + if (arm_current_el(env) =3D=3D 1 && (arm_hcr_el2_eff(env) & HCR_TSW)) { + return CP_ACCESS_TRAP_EL2; + } + return CP_ACCESS_OK; +} + static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t = value) { ARMCPU *cpu =3D env_archcpu(env); @@ -4704,14 +4714,14 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .access =3D PL1_W, .type =3D ARM_CP_NOP }, { .name =3D "DC_ISW", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 2, - .access =3D PL1_W, .type =3D ARM_CP_NOP }, + .access =3D PL1_W, .accessfn =3D access_tsw, .type =3D ARM_CP_NOP }, { .name =3D "DC_CVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 10, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NOP, .accessfn =3D aa64_cacheop_access }, { .name =3D "DC_CSW", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 10, .opc2 =3D 2, - .access =3D PL1_W, .type =3D ARM_CP_NOP }, + .access =3D PL1_W, .accessfn =3D access_tsw, .type =3D ARM_CP_NOP }, { .name =3D "DC_CVAU", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 11, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NOP, @@ -4722,7 +4732,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .accessfn =3D aa64_cacheop_access }, { .name =3D "DC_CISW", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 14, .opc2 =3D 2, - .access =3D PL1_W, .type =3D ARM_CP_NOP }, + .access =3D PL1_W, .accessfn =3D access_tsw, .type =3D ARM_CP_NOP }, /* TLBI operations */ { .name =3D "TLBI_VMALLE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 0, @@ -4903,17 +4913,17 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { { .name =3D "DCIMVAC", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 6= , .opc2 =3D 1, .type =3D ARM_CP_NOP, .access =3D PL1_W }, { .name =3D "DCISW", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, = .opc2 =3D 2, - .type =3D ARM_CP_NOP, .access =3D PL1_W }, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, { .name =3D "DCCMVAC", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 1= 0, .opc2 =3D 1, .type =3D ARM_CP_NOP, .access =3D PL1_W }, { .name =3D "DCCSW", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 10,= .opc2 =3D 2, - .type =3D ARM_CP_NOP, .access =3D PL1_W }, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, { .name =3D "DCCMVAU", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 1= 1, .opc2 =3D 1, .type =3D ARM_CP_NOP, .access =3D PL1_W }, { .name =3D "DCCIMVAC", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D = 14, .opc2 =3D 1, .type =3D ARM_CP_NOP, .access =3D PL1_W }, { .name =3D "DCCISW", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 14= , .opc2 =3D 2, - .type =3D ARM_CP_NOP, .access =3D PL1_W }, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, /* MMU Domain access control / MPU write buffer control */ { .name =3D "DACR", .cp =3D 15, .opc1 =3D 0, .crn =3D 3, .crm =3D 0, .= opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .resetvalue =3D 0, --=20 2.20.1 From nobody Thu Nov 13 17:44:03 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id i68sm5139399pfe.173.2020.02.18.11.10.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Feb 2020 11:10:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=macsUf7RwNXBE0fmKKCjQlSCUWHuv/3Gu30XsvyGcpY=; b=ap0lFfBawvYsao7AIava1O4L4J8JPIPlsgvKjLKk/m5K5/K6dRHpWbzlRkGL52Tr1l jYY/jCvZR2BGfEwmRv1iecNjZ19mAJA7O0zP5UdSsdv3yvWZQilzWwqSM+NcE/dss3y9 RPjuQ8zG6DiR4KK6YDpdFD6qnBY8uwkwnIhJsLVVvlGcCAW0TNwsmjeGXUA0E8gly8li XnNfswl1eAgkgWM0AqbkaWhtK2Xh0kfA5GLG/utz9bvhge95lWk9Q+ZHf/DjqASJsq9o Pclnq9mSd2dcKuGTuajCSJqo2mNjY6h5QMES8U4ylqvI/OT0ihUVCy31I+ufZdYtSJd+ DbGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=macsUf7RwNXBE0fmKKCjQlSCUWHuv/3Gu30XsvyGcpY=; b=Yo0pi1GITZLwDGvVTLWUgLDbwEQvc1KPot6RQd3Ci59lnvwoKpV8+k9QFBn1T+H/4q nu0LzHj/qSD0hW4Kz18ZhEBRxHZqSTaKFh71Uxpv6CFAx9s6bAF5k2MVQso1Sk9KbieF 7arooNuSqIw26TYSOAhkGc8RkqTyNb4Fumc7LrC6lOFjl6ODHjqDU3eIGISSORRHEPZn FWLanuYWAQZFcFGmStemxi+axFAUIeY1UzrhGGfvT9DjwbHsrY+UjZZ7pPr3UBW2dK7o uJcpt4EzxFdIObG6fCjMlHdbGuegEZZ84snv54FssK6l4rGd8BTN8lUdAmNydZ0YXAlG fX0w== X-Gm-Message-State: APjAAAVtr1r57L0oXHKJDtWonaeFQw0oj3lbniPJrr7aLgMgv7WFlYni l4FYlpkm7DrkrmAzHLhkrVBL1ZYpAZc= X-Google-Smtp-Source: APXvYqzH8k4Ah+pjVnB7hJ6NAis1rFo0mgIAAOzKA+kivGUT4336d3QE8iYPFKFftdUAwcPx2xo5xA== X-Received: by 2002:a17:90a:5285:: with SMTP id w5mr4470243pjh.77.1582053006040; Tue, 18 Feb 2020 11:10:06 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 4/7] target/arm: Honor the HCR_EL2.TACR bit Date: Tue, 18 Feb 2020 11:09:55 -0800 Message-Id: <20200218190958.745-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200218190958.745-1-richard.henderson@linaro.org> References: <20200218190958.745-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1042 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" This bit traps EL1 access to the auxiliary control registers. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index dc99ee5d18..52b6e68659 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -553,6 +553,16 @@ static CPAccessResult access_tsw(CPUARMState *env, con= st ARMCPRegInfo *ri, return CP_ACCESS_OK; } =20 +/* Check for traps from EL1 due to HCR_EL2.TACR. */ +static CPAccessResult access_tacr(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + if (arm_current_el(env) =3D=3D 1 && (arm_hcr_el2_eff(env) & HCR_TACR))= { + return CP_ACCESS_TRAP_EL2; + } + return CP_ACCESS_OK; +} + static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t = value) { ARMCPU *cpu =3D env_archcpu(env); @@ -6911,8 +6921,8 @@ static const ARMCPRegInfo ats1cp_reginfo[] =3D { static const ARMCPRegInfo actlr2_hactlr2_reginfo[] =3D { { .name =3D "ACTLR2", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 =3D 3, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, + .access =3D PL1_RW, .accessfn =3D access_tacr, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "HACTLR2", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 4, .crn =3D 1, .crm =3D 0, .opc2 =3D 3, .access =3D PL2_RW, .type =3D ARM_CP_CONST, @@ -7668,8 +7678,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) ARMCPRegInfo auxcr_reginfo[] =3D { { .name =3D "ACTLR_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 =3D = 1, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D cpu->reset_auxcr }, + .access =3D PL1_RW, .accessfn =3D access_tacr, + .type =3D ARM_CP_CONST, .resetvalue =3D cpu->reset_auxcr }, { .name =3D "ACTLR_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 0, .opc2 =3D = 1, .access =3D PL2_RW, .type =3D ARM_CP_CONST, --=20 2.20.1 From nobody Thu Nov 13 17:44:03 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582053678693759.7099712226977; Tue, 18 Feb 2020 11:21:18 -0800 (PST) Received: from localhost ([::1]:40704 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j48Qn-0002ws-Iq for importer@patchew.org; Tue, 18 Feb 2020 14:21:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47087) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j48G3-00054E-Rh for qemu-devel@nongnu.org; Tue, 18 Feb 2020 14:10:13 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j48G1-0001yw-Dt for qemu-devel@nongnu.org; Tue, 18 Feb 2020 14:10:11 -0500 Received: from mail-pf1-x442.google.com ([2607:f8b0:4864:20::442]:34547) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j48G1-0001x4-6r for qemu-devel@nongnu.org; Tue, 18 Feb 2020 14:10:09 -0500 Received: by mail-pf1-x442.google.com with SMTP id i6so11138768pfc.1 for ; Tue, 18 Feb 2020 11:10:09 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id i68sm5139399pfe.173.2020.02.18.11.10.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Feb 2020 11:10:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5k7tlvEB9/rsMbuI3aToULa8WUIjX1E0iDo+FSiobiY=; b=GXQTHFae6PA4ZmF7WMXLg+OhuuEv40//FDA0oPWididXI2Twdh/xJ3wlzSIMF8yvI0 X/A6rXSCnI7RFv8KXc9MIF+qnqU5CSTJw8IsHqvl+ahBd3yP77C3Kaq8Fag26oAAyZ8P 9EqTaLH8ExANR8bEartWhJeVxWdwFqr9gv0cwncFCQ9elT+N/smaXJ9YiaEKWVFCyoob Uij33shXnhWd40f/vn5TBZKTzAXvbvxoqM7cU4eslexAv+6m5VncCNsEAu+qoocWq2US UT5bfoSJbBp+SAGmSRf0n8Cm+iYL8JNWox47kqCls+CW0rbcwOgn5XjWbch6hln15Zs7 GLnQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5k7tlvEB9/rsMbuI3aToULa8WUIjX1E0iDo+FSiobiY=; b=kWpyjsyG7Vjcs72NKOdVJ4bFsujLVjgam3qzDo10aoLY2yGNHSOUYvcVmsROD/Orhr 2VOmgOjyT0HxsW2mqHE1V6LSAR6UyLnPsPhET/W0bCFOCLVStjPpOJ/W7bNGY9ptX5mr os2BNO2HNpzUVz67OVkeoW7hy4QTYbw+bIivV5nT+68ZjEb76QrQjZ8eeeuwYu6UBacj Dph2e38ynCkLXKiqVtQu7CjBfOq9xwrw9drigrzkNTU+HasPNxxV/Mb/R81kuVw93GD7 cVntvUYfAL/O9/cGe5+bq1NV49Z3SnkztLTzI4SS9bHD4PjR3nyeuINcTAgBqcwRs4c4 A4Lw== X-Gm-Message-State: APjAAAVZUi95qakKBAxIGDXep7uc4bavi9mIdCLZI9KOkbgT0Q90lpya yt6erGuxqGnInkE/LqmlfeoJb2yqfXk= X-Google-Smtp-Source: APXvYqxVTISRphPBB9JPw4QZ4d+q+MPyjrtw/FU+dLV+vcqhj/5sOaOGINFNYxafAeg7Xr3wXQS7nA== X-Received: by 2002:a63:5345:: with SMTP id t5mr23936562pgl.254.1582053007849; Tue, 18 Feb 2020 11:10:07 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 5/7] target/arm: Honor the HCR_EL2.TPCP bit Date: Tue, 18 Feb 2020 11:09:56 -0800 Message-Id: <20200218190958.745-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200218190958.745-1-richard.henderson@linaro.org> References: <20200218190958.745-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" This bit traps EL1 access to cache maintenance insns that operate to the point of coherency or persistence. Signed-off-by: Richard Henderson --- target/arm/helper.c | 39 +++++++++++++++++++++++++++++++-------- 1 file changed, 31 insertions(+), 8 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 52b6e68659..ed34d4200f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4314,6 +4314,28 @@ static CPAccessResult aa64_cacheop_access(CPUARMStat= e *env, return CP_ACCESS_OK; } =20 +static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env, + const ARMCPRegInfo *ri, + bool isread) +{ + /* Cache invalidate/clean to Point of Coherency or Persistence... */ + switch (arm_current_el(env)) { + case 0: + /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */ + if (!(arm_sctlr(env, 0) & SCTLR_UCI)) { + return CP_ACCESS_TRAP; + } + break; + case 1: + /* ... EL1 must trap to EL2 if HCR_EL2.TPCP is set. */ + if (arm_hcr_el2_eff(env) & HCR_TPCP) { + return CP_ACCESS_TRAP_EL2; + } + break; + } + return CP_ACCESS_OK; +} + /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instru= ctions * Page D4-1736 (DDI0487A.b) */ @@ -4721,14 +4743,15 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .accessfn =3D aa64_cacheop_access }, { .name =3D "DC_IVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 1, - .access =3D PL1_W, .type =3D ARM_CP_NOP }, + .access =3D PL1_W, .accessfn =3D aa64_cacheop_poc_access, + .type =3D ARM_CP_NOP }, { .name =3D "DC_ISW", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 2, .access =3D PL1_W, .accessfn =3D access_tsw, .type =3D ARM_CP_NOP }, { .name =3D "DC_CVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 10, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NOP, - .accessfn =3D aa64_cacheop_access }, + .accessfn =3D aa64_cacheop_poc_access }, { .name =3D "DC_CSW", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 10, .opc2 =3D 2, .access =3D PL1_W, .accessfn =3D access_tsw, .type =3D ARM_CP_NOP }, @@ -4739,7 +4762,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { { .name =3D "DC_CIVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 14, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NOP, - .accessfn =3D aa64_cacheop_access }, + .accessfn =3D aa64_cacheop_poc_access }, { .name =3D "DC_CISW", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 14, .opc2 =3D 2, .access =3D PL1_W, .accessfn =3D access_tsw, .type =3D ARM_CP_NOP }, @@ -4921,17 +4944,17 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { { .name =3D "BPIMVA", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 5,= .opc2 =3D 7, .type =3D ARM_CP_NOP, .access =3D PL1_W }, { .name =3D "DCIMVAC", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 6= , .opc2 =3D 1, - .type =3D ARM_CP_NOP, .access =3D PL1_W }, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D aa64_cacheop_= poc_access }, { .name =3D "DCISW", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, = .opc2 =3D 2, .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, { .name =3D "DCCMVAC", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 1= 0, .opc2 =3D 1, - .type =3D ARM_CP_NOP, .access =3D PL1_W }, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D aa64_cacheop_= poc_access }, { .name =3D "DCCSW", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 10,= .opc2 =3D 2, .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, { .name =3D "DCCMVAU", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 1= 1, .opc2 =3D 1, .type =3D ARM_CP_NOP, .access =3D PL1_W }, { .name =3D "DCCIMVAC", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D = 14, .opc2 =3D 1, - .type =3D ARM_CP_NOP, .access =3D PL1_W }, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D aa64_cacheop_= poc_access }, { .name =3D "DCCISW", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 14= , .opc2 =3D 2, .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, /* MMU Domain access control / MPU write buffer control */ @@ -6715,7 +6738,7 @@ static const ARMCPRegInfo dcpop_reg[] =3D { { .name =3D "DC_CVAP", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 12, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, - .accessfn =3D aa64_cacheop_access, .writefn =3D dccvap_writefn }, + .accessfn =3D aa64_cacheop_poc_access, .writefn =3D dccvap_writefn }, REGINFO_SENTINEL }; =20 @@ -6723,7 +6746,7 @@ static const ARMCPRegInfo dcpodp_reg[] =3D { { .name =3D "DC_CVADP", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 13, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, - .accessfn =3D aa64_cacheop_access, .writefn =3D dccvap_writefn }, + .accessfn =3D aa64_cacheop_poc_access, .writefn =3D dccvap_writefn }, REGINFO_SENTINEL }; #endif /*CONFIG_USER_ONLY*/ --=20 2.20.1 From nobody Thu Nov 13 17:44:03 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582053381914410.4704533675143; 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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id i68sm5139399pfe.173.2020.02.18.11.10.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Feb 2020 11:10:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=d8VQKU6rv4Pu6l3hpA5VgoL0EnHokMCgM3rMhYXv+l4=; b=iSdVw9rzE92iebe/A9OrratQX/Vu8tbEoCAedhD6vLfuzXejm1whRjBMyWODOhtgs2 xD/UJpV4xLSNmGYHHdQxr3WpNxoT10JUjgLHLcDGk8u+REBMn9f3cMF9Sh3dDLOsfGEY 38/5i24t8saybaahzI27wnpv3CmwguwslFjSdeXV4b5MLQ8CzlvPciLvb4UcSE0mZFaY IsbZwU2wXMOgeCjCGK2guLsUSYCnYIQLLkOTDILSvcaWKYNmhUGKWUM2wAbOeVEerya8 NGaWW8nDC6FRm0P0JubQiYifvj/0Nhzc+JZweDRftopftU3fXYUei3PCZwcpo15axo6n hG4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=d8VQKU6rv4Pu6l3hpA5VgoL0EnHokMCgM3rMhYXv+l4=; b=XBrsBqEBeydIGZKpYDeYiQJGeE/2GrsYTsHR38nqcsHtioiKo9jpwFzU9O9HB9ygtO KYoOHtCzqUGQGAVMRplT4J0U8EkLoOhtc3O9rVeuzOwNcveRw+7rCh0oHlSYUWTNwgPy /5BVDLCD6/Bzrh018QI55PvvjmLSaylAIY5ShJqHACH1JflJBAbNscG91wNQlYF7Dxjo Ws8hzSXUksqQb6EtpmJfHw3ke2Za3t2YZIhbLDEUGAThOHsyyuf/HV6g3JN7zOPaK4RI lAlZyZjpt5WRukJF3ElEOhNALnwsAR+3N+jWk9enEeUoxCyvXVBJ/eRex1c0/bXBnRGd dAJg== X-Gm-Message-State: APjAAAW5RwYXOceCbKUTH8OupCpuk6En3O6Dug3lqjFjR1ZT7ybYICfD TZrOVuSk4E4Rj+up7FwzONpZ1t5L0/M= X-Google-Smtp-Source: APXvYqywdbldvwsrBoy65Is2wfJZzLcn2vYvA/XkrQpzyMPMdYVC78KXHbZ6ii3ujEu1vrYVRMOZLg== X-Received: by 2002:a62:7681:: with SMTP id r123mr22675100pfc.169.1582053009053; Tue, 18 Feb 2020 11:10:09 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 6/7] target/arm: Honor the HCR_EL2.TPU bit Date: Tue, 18 Feb 2020 11:09:57 -0800 Message-Id: <20200218190958.745-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200218190958.745-1-richard.henderson@linaro.org> References: <20200218190958.745-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" This bit traps EL1 access to cache maintenance insns that operate to the point of unification. There are no longer any references to plain aa64_cacheop_access, so remove it. Signed-off-by: Richard Henderson --- target/arm/helper.c | 53 +++++++++++++++++++++++++++------------------ 1 file changed, 32 insertions(+), 21 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index ed34d4200f..21ee9cf7de 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4301,19 +4301,6 @@ static const ARMCPRegInfo uao_reginfo =3D { .readfn =3D aa64_uao_read, .writefn =3D aa64_uao_write }; =20 -static CPAccessResult aa64_cacheop_access(CPUARMState *env, - const ARMCPRegInfo *ri, - bool isread) -{ - /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless - * SCTLR_EL1.UCI is set. - */ - if (arm_current_el(env) =3D=3D 0 && !(arm_sctlr(env, 0) & SCTLR_UCI)) { - return CP_ACCESS_TRAP; - } - return CP_ACCESS_OK; -} - static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) @@ -4336,6 +4323,28 @@ static CPAccessResult aa64_cacheop_poc_access(CPUARM= State *env, return CP_ACCESS_OK; } =20 +static CPAccessResult aa64_cacheop_pou_access(CPUARMState *env, + const ARMCPRegInfo *ri, + bool isread) +{ + /* Cache invalidate/clean to Point of Unification... */ + switch (arm_current_el(env)) { + case 0: + /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */ + if (!(arm_sctlr(env, 0) & SCTLR_UCI)) { + return CP_ACCESS_TRAP; + } + break; + case 1: + /* ... EL1 must trap to EL2 if HCR_EL2.TPU is set. */ + if (arm_hcr_el2_eff(env) & HCR_TPU) { + return CP_ACCESS_TRAP_EL2; + } + break; + } + return CP_ACCESS_OK; +} + /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instru= ctions * Page D4-1736 (DDI0487A.b) */ @@ -4733,14 +4742,16 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { /* Cache ops: all NOPs since we don't emulate caches */ { .name =3D "IC_IALLUIS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 1, .opc2 =3D 0, - .access =3D PL1_W, .type =3D ARM_CP_NOP }, + .access =3D PL1_W, .type =3D ARM_CP_NOP, + .accessfn =3D aa64_cacheop_pou_access }, { .name =3D "IC_IALLU", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 5, .opc2 =3D 0, - .access =3D PL1_W, .type =3D ARM_CP_NOP }, + .access =3D PL1_W, .type =3D ARM_CP_NOP, + .accessfn =3D aa64_cacheop_pou_access }, { .name =3D "IC_IVAU", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 5, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NOP, - .accessfn =3D aa64_cacheop_access }, + .accessfn =3D aa64_cacheop_pou_access }, { .name =3D "DC_IVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 1, .access =3D PL1_W, .accessfn =3D aa64_cacheop_poc_access, @@ -4758,7 +4769,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { { .name =3D "DC_CVAU", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 11, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NOP, - .accessfn =3D aa64_cacheop_access }, + .accessfn =3D aa64_cacheop_pou_access }, { .name =3D "DC_CIVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 14, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NOP, @@ -4932,13 +4943,13 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .writefn =3D tlbiipas2_is_write }, /* 32 bit cache operations */ { .name =3D "ICIALLUIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D= 1, .opc2 =3D 0, - .type =3D ARM_CP_NOP, .access =3D PL1_W }, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D aa64_cacheop_= pou_access }, { .name =3D "BPIALLUIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D= 1, .opc2 =3D 6, .type =3D ARM_CP_NOP, .access =3D PL1_W }, { .name =3D "ICIALLU", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 5= , .opc2 =3D 0, - .type =3D ARM_CP_NOP, .access =3D PL1_W }, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D aa64_cacheop_= pou_access }, { .name =3D "ICIMVAU", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 5= , .opc2 =3D 1, - .type =3D ARM_CP_NOP, .access =3D PL1_W }, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D aa64_cacheop_= pou_access }, { .name =3D "BPIALL", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 5,= .opc2 =3D 6, .type =3D ARM_CP_NOP, .access =3D PL1_W }, { .name =3D "BPIMVA", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 5,= .opc2 =3D 7, @@ -4952,7 +4963,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { { .name =3D "DCCSW", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 10,= .opc2 =3D 2, .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, { .name =3D "DCCMVAU", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 1= 1, .opc2 =3D 1, - .type =3D ARM_CP_NOP, .access =3D PL1_W }, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D aa64_cacheop_= pou_access }, { .name =3D "DCCIMVAC", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D = 14, .opc2 =3D 1, .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D aa64_cacheop_= poc_access }, { .name =3D "DCCISW", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 14= , .opc2 =3D 2, --=20 2.20.1 From nobody Thu Nov 13 17:44:03 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id i68sm5139399pfe.173.2020.02.18.11.10.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Feb 2020 11:10:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nhoZN+6W0yWgtc6EACu9ulVuQ0nYIKeOYAuOPcONJJc=; b=S8bGvkeeSkkxZdAk501M7LROquguS4xuyhQqnKvP620ZaHKJ5ObgnzeERm0BJl0G34 fkiRo0sWMS0mMo7E91pZju/H99ZlJOS5CCFshJb82nqt/pPrYidygBymakS09nLfl7R8 GspJBPU6YvmgXdy+0YZYPQXYWvxPH58JhXU/4EtgBomwHrDCWsU3Eq9sR2sj+OWJfi5A QcKAsPfab5U0xVB3yCCqlcBVLOJ2+Js8wV6HSiIYG9gEFq2/CETcBiSk3rf2+ji54b/P FRGBUOsj+rnraHV6P5a/Snw5r8+g3rlsfzqy+8RB0Pf+5Ba/yFi6b8X2x4XSzx1Yr8hj kxyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nhoZN+6W0yWgtc6EACu9ulVuQ0nYIKeOYAuOPcONJJc=; b=ZiqnAbNyzjs6bCkV+QBVUQtHXfH6zf8y7yPdHiaEXzeKHcZF995n0mFCq8Nr+wOCkK RPpuskfrZDXT4Swpr+54WtNqhrL4lvngmtAj7YcqxCQoZYuf9xVE/u1A7jnzpmFRq9/8 w8sZwTK5KbwtSPD9nTUp3R1cVZ7JNVSvVdy5f6sK+Db6UcIZycoztSyJrpdRS+FZhtCM 6N38Br4XckiDnAR4oxic7FBU5AbSrv+LqjJ36yEGjzsr1eYn4o6/5HNARziVWhtZa5DO SonKwtoLYzy8rK8zP6hh9PrAwFnBLjSBWkSkbXbcqiKxTnsDEcOXAd9j2fATUxqDaJl6 rQ4g== X-Gm-Message-State: APjAAAU9tvu1c8aP1jegz+ASPvRrUQakkBxJLxIeCf8nZjuWCDDMEPdz yHpbVlCoz2IPOUkgGPUNKjl/h5VWjF0= X-Google-Smtp-Source: APXvYqwqBSYuhwKH1iGHjzSxsj0CiQcbaWMViDqXr/3KPXJUwSUjgkbKjdl1Jr89gAiRT4jldg3vsw== X-Received: by 2002:a63:34e:: with SMTP id 75mr25160468pgd.286.1582053010300; Tue, 18 Feb 2020 11:10:10 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 7/7] target/arm: Honor the HCR_EL2.TTLB bit Date: Tue, 18 Feb 2020 11:09:58 -0800 Message-Id: <20200218190958.745-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200218190958.745-1-richard.henderson@linaro.org> References: <20200218190958.745-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" This bit traps EL1 access to tlb maintenance insns. Signed-off-by: Richard Henderson --- target/arm/helper.c | 85 +++++++++++++++++++++++++++++---------------- 1 file changed, 55 insertions(+), 30 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 21ee9cf7de..87c0cf4a96 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -563,6 +563,16 @@ static CPAccessResult access_tacr(CPUARMState *env, co= nst ARMCPRegInfo *ri, return CP_ACCESS_OK; } =20 +/* Check for traps from EL1 due to HCR_EL2.TTLB. */ +static CPAccessResult access_ttlb(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + if (arm_current_el(env) =3D=3D 1 && (arm_hcr_el2_eff(env) & HCR_TTLB))= { + return CP_ACCESS_TRAP_EL2; + } + return CP_ACCESS_OK; +} + static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t = value) { ARMCPU *cpu =3D env_archcpu(env); @@ -2287,41 +2297,53 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .type =3D ARM_CP_NO_RAW, .access =3D PL1_R, .readfn =3D isr_read }, /* 32 bit ITLB invalidates */ { .name =3D "ITLBIALL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 5, .opc2 =3D 0, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbiall_wri= te }, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbiall_write }, { .name =3D "ITLBIMVA", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 5, .opc2 =3D 1, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbimva_wri= te }, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbimva_write }, { .name =3D "ITLBIASID", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D= 5, .opc2 =3D 2, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbiasid_wr= ite }, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbiasid_write }, /* 32 bit DTLB invalidates */ { .name =3D "DTLBIALL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 6, .opc2 =3D 0, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbiall_wri= te }, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbiall_write }, { .name =3D "DTLBIMVA", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 6, .opc2 =3D 1, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbimva_wri= te }, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbimva_write }, { .name =3D "DTLBIASID", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D= 6, .opc2 =3D 2, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbiasid_wr= ite }, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbiasid_write }, /* 32 bit TLB invalidates */ { .name =3D "TLBIALL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D 7= , .opc2 =3D 0, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbiall_wri= te }, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbiall_write }, { .name =3D "TLBIMVA", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D 7= , .opc2 =3D 1, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbimva_wri= te }, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbimva_write }, { .name =3D "TLBIASID", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 7, .opc2 =3D 2, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbiasid_wr= ite }, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbiasid_write }, { .name =3D "TLBIMVAA", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 7, .opc2 =3D 3, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbimvaa_wr= ite }, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbimvaa_write }, REGINFO_SENTINEL }; =20 static const ARMCPRegInfo v7mp_cp_reginfo[] =3D { /* 32 bit TLB invalidates, Inner Shareable */ { .name =3D "TLBIALLIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D= 3, .opc2 =3D 0, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbiall_is_= write }, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbiall_is_write }, { .name =3D "TLBIMVAIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D= 3, .opc2 =3D 1, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbimva_is_= write }, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbimva_is_write }, { .name =3D "TLBIASIDIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm = =3D 3, .opc2 =3D 2, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, .writefn =3D tlbiasid_is_write }, { .name =3D "TLBIMVAAIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm = =3D 3, .opc2 =3D 3, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, .writefn =3D tlbimvaa_is_write }, REGINFO_SENTINEL }; @@ -4780,51 +4802,51 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { /* TLBI operations */ { .name =3D "TLBI_VMALLE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 0, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, .writefn =3D tlbi_aa64_vmalle1is_write }, { .name =3D "TLBI_VAE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 1, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, .writefn =3D tlbi_aa64_vae1is_write }, { .name =3D "TLBI_ASIDE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 2, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, .writefn =3D tlbi_aa64_vmalle1is_write }, { .name =3D "TLBI_VAAE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 3, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, .writefn =3D tlbi_aa64_vae1is_write }, { .name =3D "TLBI_VALE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 5, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, .writefn =3D tlbi_aa64_vae1is_write }, { .name =3D "TLBI_VAALE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 7, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, .writefn =3D tlbi_aa64_vae1is_write }, { .name =3D "TLBI_VMALLE1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 0, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, .writefn =3D tlbi_aa64_vmalle1_write }, { .name =3D "TLBI_VAE1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 1, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, .writefn =3D tlbi_aa64_vae1_write }, { .name =3D "TLBI_ASIDE1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 2, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, .writefn =3D tlbi_aa64_vmalle1_write }, { .name =3D "TLBI_VAAE1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 3, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, .writefn =3D tlbi_aa64_vae1_write }, { .name =3D "TLBI_VALE1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 5, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, .writefn =3D tlbi_aa64_vae1_write }, { .name =3D "TLBI_VAALE1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 7, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, .writefn =3D tlbi_aa64_vae1_write }, { .name =3D "TLBI_IPAS2E1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 1, @@ -4910,14 +4932,17 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { #endif /* TLB invalidate last level of translation table walk */ { .name =3D "TLBIMVALIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm = =3D 3, .opc2 =3D 5, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbimva_is_= write }, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbimva_is_write }, { .name =3D "TLBIMVAALIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm = =3D 3, .opc2 =3D 7, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, .writefn =3D tlbimvaa_is_write }, { .name =3D "TLBIMVAL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 7, .opc2 =3D 5, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbimva_wri= te }, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbimva_write }, { .name =3D "TLBIMVAAL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D= 7, .opc2 =3D 7, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbimvaa_wr= ite }, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbimvaa_write }, { .name =3D "TLBIMVALH", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D= 7, .opc2 =3D 5, .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, .writefn =3D tlbimva_hyp_write }, --=20 2.20.1