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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id d73sm4858392pfd.109.2020.02.18.08.47.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Feb 2020 08:47:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=sJagifWpn6uhasrVbYbX7C8kWfDQ+S6CVHfZbQrfkHs=; b=QJSG3rhH9S1wrjdjW64CkJvV++hHpPqB+EctHzO0VvbJe6RI9CD6aVoa7G2sWIv2uY Wh1QbumYpgq0slfdLLjrGi+zdiysK3QdI5l2DASxADrgwATNNLClQ4MnUrJcp6btme+D pbLZ0Z1PgyIjsg83kx5J+3Jqvq2ezMomPKPxFP/2r6XFfD8u9u/ZSG2O0rLI7gBqIGhI rnbmCHm1cQcJvtJjJhAHhIRU2Ow7p8TJmjhgU3hxWaUhiRkvi+c4Jnj8kxKifg2tXmW2 58xshMWBlOSEjoDxS1b7uOpmIigPG4ubmI997ZrhYYR+U6VbN9NhOXw1XjHdNKUtp7lF BXSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=sJagifWpn6uhasrVbYbX7C8kWfDQ+S6CVHfZbQrfkHs=; b=tUT6DG1lArk2urXFtnndKT74o7DY/nG+Z0eTehQJa9jxV0eSQ+Iw7uTlHCH2U1kcXL nBbL2nslod+auxEUfXHrvBoou2xAIzaHF0yFkcIH5S27FuXDZU9m5MDtFj9HZlc/W58G W8qGzs51yn7j1Qnb7kAdr4p+1FI740usCyQahGW9qjHNmHIw2vYVhO/5oIkTsZBUL5uv Yxio17A0eV3pIiH7/STeknBMOqhZ4pcWM+zca2gJimhvSBNzfUThqlqf/ocWI57rocZl f3p84GjdymOFAZMfMaa5/gfgm/WdPcvWSzSY7PUpcG2T6drHDvZ1q19I9LMkZNc/Uyzo RAMA== X-Gm-Message-State: APjAAAVImotR17lCObLQZlMo8XA4P/PJ3Sr1OBRO1vj4WLp4Vg67S7LN 4N+zvfeUB/oAeWeQV6AlyZrbEyFQ5IM= X-Google-Smtp-Source: APXvYqwqTdouuOyuBYsfaTRanY2oh2xvJJdK3zhVi5IlXwauNnBVq8uCssYKWDPmHuR/Ev0fkVDFHg== X-Received: by 2002:a17:90a:fa8d:: with SMTP id cu13mr3642788pjb.68.1582044439626; Tue, 18 Feb 2020 08:47:19 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH] target/arm: Honor the HCR_EL2.TSW bit Date: Tue, 18 Feb 2020 08:47:17 -0800 Message-Id: <20200218164717.12842-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1041 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" These bits trap EL1 access to set/way cache maintenance insns. Buglink: https://bugs.launchpad.net/bugs/1863685 Signed-off-by: Richard Henderson --- Based-on: <20200218152844.29351-1-richard.henderson@linaro.org> ("target/arm: Honor the HCR_EL2.{TVM,TRVM} bits") Not really dependent on the above, but there will be a trivial patch conflict without it. r~ --- target/arm/helper.c | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 69946a57f8..b87518b97a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -542,6 +542,16 @@ static CPAccessResult access_tvm_trvm(CPUARMState *env= , const ARMCPRegInfo *ri, return CP_ACCESS_OK; } =20 +/* Check for traps from EL1 due to HCR_EL2.TSW. */ +static CPAccessResult access_tsw(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + if (arm_current_el(env) =3D=3D 1 && (arm_hcr_el2_eff(env) & HCR_TSW)) { + return CP_ACCESS_TRAP_EL2; + } + return CP_ACCESS_OK; +} + static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t = value) { ARMCPU *cpu =3D env_archcpu(env); @@ -4659,14 +4669,14 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .access =3D PL1_W, .type =3D ARM_CP_NOP }, { .name =3D "DC_ISW", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 2, - .access =3D PL1_W, .type =3D ARM_CP_NOP }, + .access =3D PL1_W, .accessfn =3D access_tsw, .type =3D ARM_CP_NOP }, { .name =3D "DC_CVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 10, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NOP, .accessfn =3D aa64_cacheop_access }, { .name =3D "DC_CSW", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 10, .opc2 =3D 2, - .access =3D PL1_W, .type =3D ARM_CP_NOP }, + .access =3D PL1_W, .accessfn =3D access_tsw, .type =3D ARM_CP_NOP }, { .name =3D "DC_CVAU", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 11, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NOP, @@ -4677,7 +4687,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .accessfn =3D aa64_cacheop_access }, { .name =3D "DC_CISW", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 14, .opc2 =3D 2, - .access =3D PL1_W, .type =3D ARM_CP_NOP }, + .access =3D PL1_W, .accessfn =3D access_tsw, .type =3D ARM_CP_NOP }, /* TLBI operations */ { .name =3D "TLBI_VMALLE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 0, @@ -4858,17 +4868,17 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { { .name =3D "DCIMVAC", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 6= , .opc2 =3D 1, .type =3D ARM_CP_NOP, .access =3D PL1_W }, { .name =3D "DCISW", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, = .opc2 =3D 2, - .type =3D ARM_CP_NOP, .access =3D PL1_W }, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, { .name =3D "DCCMVAC", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 1= 0, .opc2 =3D 1, .type =3D ARM_CP_NOP, .access =3D PL1_W }, { .name =3D "DCCSW", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 10,= .opc2 =3D 2, - .type =3D ARM_CP_NOP, .access =3D PL1_W }, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, { .name =3D "DCCMVAU", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 1= 1, .opc2 =3D 1, .type =3D ARM_CP_NOP, .access =3D PL1_W }, { .name =3D "DCCIMVAC", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D = 14, .opc2 =3D 1, .type =3D ARM_CP_NOP, .access =3D PL1_W }, { .name =3D "DCCISW", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 14= , .opc2 =3D 2, - .type =3D ARM_CP_NOP, .access =3D PL1_W }, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, /* MMU Domain access control / MPU write buffer control */ { .name =3D "DACR", .cp =3D 15, .opc1 =3D 0, .crn =3D 3, .crm =3D 0, .= opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .resetvalue =3D 0, --=20 2.20.1