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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id e26sm1140338pfl.59.2020.02.17.09.38.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Feb 2020 09:38:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=iqRDxwhGitXGaxwS+nF4P1weqSN/U9gDo8XE2cwDJVE=; b=oDUK3VDoo5YZp8JjNnHhwn9ScWKCXMwy+nowHtZ9k6xYjvLxdQ8/uSLwkNT33/Ueyi xeDTbDzUTRFDoLkYh4VqlYrGhlanK3qf7d1R/FhwZfQeXM1WFD6P4h34cqEtn1cVC8ov k3VdLz37IWLywT7YYv7B6wQJwTwx09CWFDDJ+n/Iz/+iT0LUs+kHxquxK9e7kapKMKkc Jo6ZsnHyqWvP/kcJu01pTtKgXfG9CogccFVEbTCC+NKjIuDwg+bhwUb20+WV8EJ46k7I er43PSRGoEEILLUiBEyn1WOWZ6O1ko/EOHPcOB7ZhvrDNLRYaMc91cBREhQgRIBT2oZP 7tJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=iqRDxwhGitXGaxwS+nF4P1weqSN/U9gDo8XE2cwDJVE=; b=ZIM3naR/E7qSGrFAbLeHWsDNdRahHxnPT2Ne90SJiQGazFFsUbB3roUZxLZKfHkOS9 XieaYN7ZvbPk1GhAuGgX4hl2hxaxydLQ0Sa/95CQNUxon5NCDkx7mV8HOdPZMNkG4khG e2AuxudJlrAcY6C2u6vjlnHonulSvNKkgArCQuu/lxjKFzcFaxw5iE8pYCMl1Q41ezg1 o427yv83xDUpZQTMVT2Ggl0gHORVg4RMe+JDIjHb12yz2nPzJlgfqxoBygDAq7Ojksy+ 2dQBJEcE7ZCMgGVtB52CpaUCvED2H0XB1oJ8Zr2lshhCl6zqjEt6gauw8La+inwsr6B6 oqsQ== X-Gm-Message-State: APjAAAWA2vdD80S4eihqSTdaBbsObshyk1Nu2t8NvsRdZw4uU1zOpdSF F92ieMrd0YQS7/1LIbXJOM/ng0rVWAM= X-Google-Smtp-Source: APXvYqyZNDD+yuzQkpWfS9iIDT0aTcllPrgyDmVobCBjTJjOg9+GWvdxKbBtrnsluRQpvDtCrEGxFw== X-Received: by 2002:aa7:9145:: with SMTP id 5mr17551993pfi.74.1581961128042; Mon, 17 Feb 2020 09:38:48 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH] target/arm: Honor the HCR_EL2.{TVM,TRVM} bits Date: Mon, 17 Feb 2020 09:38:46 -0800 Message-Id: <20200217173846.2803-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" These bits trap EL1 access to various virtual memory controls. Buglink: https://bugs.launchpad.net/bugs/1855072 Signed-off-by: Richard Henderson --- I guess this is a feature used by Xen? The Linux kernel only uses this for a Cavium errata workaround. I'm still looking into how to test this. r~ --- target/arm/helper.c | 74 ++++++++++++++++++++++++++++++--------------- 1 file changed, 50 insertions(+), 24 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 366dbcf460..24b2b5dd55 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -529,6 +529,19 @@ static CPAccessResult access_tpm(CPUARMState *env, con= st ARMCPRegInfo *ri, return CP_ACCESS_OK; } =20 +/* Check for traps from EL1 due to HCR_EL2.TVM and HCR_EL2.TRVM. */ +static CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo= *ri, + bool isread) +{ + if (arm_current_el(env) =3D=3D 1) { + uint64_t trap =3D isread ? HCR_TRVM : HCR_TVM; + if (arm_hcr_el2_eff(env) & trap) { + return CP_ACCESS_TRAP_EL2; + } + } + return CP_ACCESS_OK; +} + static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t = value) { ARMCPU *cpu =3D env_archcpu(env); @@ -784,7 +797,8 @@ static const ARMCPRegInfo cp_reginfo[] =3D { */ { .name =3D "CONTEXTIDR_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 13, .crm =3D 0, .opc2 =3D 1, - .access =3D PL1_RW, .secure =3D ARM_CP_SECSTATE_NS, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .secure =3D ARM_CP_SECSTATE_NS, .fieldoffset =3D offsetof(CPUARMState, cp15.contextidr_el[1]), .resetvalue =3D 0, .writefn =3D contextidr_write, .raw_writefn =3D r= aw_write, }, { .name =3D "CONTEXTIDR_S", .state =3D ARM_CP_STATE_AA32, @@ -876,9 +890,11 @@ static const ARMCPRegInfo not_v7_cp_reginfo[] =3D { .opc1 =3D CP_ANY, .opc2 =3D 3, .access =3D PL1_W, .writefn =3D tlbim= vaa_write, .type =3D ARM_CP_NO_RAW }, { .name =3D "PRRR", .cp =3D 15, .crn =3D 10, .crm =3D 2, - .opc1 =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .type =3D ARM_CP_NOP }, + .opc1 =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_t= vm_trvm, + .type =3D ARM_CP_NOP }, { .name =3D "NMRR", .cp =3D 15, .crn =3D 10, .crm =3D 2, - .opc1 =3D 0, .opc2 =3D 1, .access =3D PL1_RW, .type =3D ARM_CP_NOP }, + .opc1 =3D 0, .opc2 =3D 1, .access =3D PL1_RW, .accessfn =3D access_t= vm_trvm, + .type =3D ARM_CP_NOP }, REGINFO_SENTINEL }; =20 @@ -996,7 +1012,7 @@ static const ARMCPRegInfo v6_cp_reginfo[] =3D { { .name =3D "DMB", .cp =3D 15, .crn =3D 7, .crm =3D 10, .opc1 =3D 0, .= opc2 =3D 5, .access =3D PL0_W, .type =3D ARM_CP_NOP }, { .name =3D "IFAR", .cp =3D 15, .crn =3D 6, .crm =3D 0, .opc1 =3D 0, .= opc2 =3D 2, - .access =3D PL1_RW, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ifar_s), offsetof(CPUARMState, cp15.ifar_ns) }, .resetvalue =3D 0, }, @@ -2164,16 +2180,19 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { */ { .name =3D "AFSR0_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 5, .crm =3D 1, .opc2 =3D 0, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "AFSR1_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 5, .crm =3D 1, .opc2 =3D 1, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, /* MAIR can just read-as-written because we don't implement caches * and so don't need to care about memory attributes. */ { .name =3D "MAIR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 2, .opc2 =3D 0, - .access =3D PL1_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.mair= _el[1]), + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .fieldoffset =3D offsetof(CPUARMState, cp15.mair_el[1]), .resetvalue =3D 0 }, { .name =3D "MAIR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 10, .crm =3D 2, .opc2 =3D 0, @@ -2187,12 +2206,14 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { * handled in the field definitions. */ { .name =3D "MAIR0", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 0, .crn =3D 10, .crm =3D 2, .opc2 =3D 0, .acce= ss =3D PL1_RW, + .cp =3D 15, .opc1 =3D 0, .crn =3D 10, .crm =3D 2, .opc2 =3D 0, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.mair0_s), offsetof(CPUARMState, cp15.mair0_ns) }, .resetfn =3D arm_cp_reset_ignore }, { .name =3D "MAIR1", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 0, .crn =3D 10, .crm =3D 2, .opc2 =3D 1, .acce= ss =3D PL1_RW, + .cp =3D 15, .opc1 =3D 0, .crn =3D 10, .crm =3D 2, .opc2 =3D 1, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.mair1_s), offsetof(CPUARMState, cp15.mair1_ns) }, .resetfn =3D arm_cp_reset_ignore }, @@ -3842,20 +3863,21 @@ static void vttbr_write(CPUARMState *env, const ARM= CPRegInfo *ri, =20 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] =3D { { .name =3D "DFSR", .cp =3D 15, .crn =3D 5, .crm =3D 0, .opc1 =3D 0, .= opc2 =3D 0, - .access =3D PL1_RW, .type =3D ARM_CP_ALIAS, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .type =3D ARM_CP_= ALIAS, .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.dfsr_s), offsetoflow32(CPUARMState, cp15.dfsr_ns) }, }, { .name =3D "IFSR", .cp =3D 15, .crn =3D 5, .crm =3D 0, .opc1 =3D 0, .= opc2 =3D 1, - .access =3D PL1_RW, .resetvalue =3D 0, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .resetvalue =3D 0, .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.ifsr_s), offsetoflow32(CPUARMState, cp15.ifsr_ns) } }, { .name =3D "DFAR", .cp =3D 15, .opc1 =3D 0, .crn =3D 6, .crm =3D 0, .= opc2 =3D 0, - .access =3D PL1_RW, .resetvalue =3D 0, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .resetvalue =3D 0, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.dfar_s), offsetof(CPUARMState, cp15.dfar_ns) } }, { .name =3D "FAR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .crn =3D 6, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 0, - .access =3D PL1_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.far_= el[1]), + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .fieldoffset =3D offsetof(CPUARMState, cp15.far_el[1]), .resetvalue =3D 0, }, REGINFO_SENTINEL }; @@ -3863,21 +3885,24 @@ static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = =3D { static const ARMCPRegInfo vmsa_cp_reginfo[] =3D { { .name =3D "ESR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .crn =3D 5, .crm =3D 2, .opc1 =3D 0, .opc2 =3D 0, - .access =3D PL1_RW, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .fieldoffset =3D offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = =3D 0, }, { .name =3D "TTBR0_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 0, .opc2 =3D 0, - .access =3D PL1_RW, .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr0_s), offsetof(CPUARMState, cp15.ttbr0_ns) } }, { .name =3D "TTBR1_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 0, .opc2 =3D 1, - .access =3D PL1_RW, .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr1_s), offsetof(CPUARMState, cp15.ttbr1_ns) } }, { .name =3D "TCR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .crn =3D 2, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 2, - .access =3D PL1_RW, .writefn =3D vmsa_tcr_el12_write, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .writefn =3D vmsa_tcr_el12_write, .resetfn =3D vmsa_ttbcr_reset, .raw_writefn =3D raw_write, .fieldoffset =3D offsetof(CPUARMState, cp15.tcr_el[1]) }, { .name =3D "TTBCR", .cp =3D 15, .crn =3D 2, .crm =3D 0, .opc1 =3D 0, = .opc2 =3D 2, @@ -3893,7 +3918,8 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] =3D { */ static const ARMCPRegInfo ttbcr2_reginfo =3D { .name =3D "TTBCR2", .cp =3D 15, .opc1 =3D 0, .crn =3D 2, .crm =3D 0, .= opc2 =3D 3, - .access =3D PL1_RW, .type =3D ARM_CP_ALIAS, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .type =3D ARM_CP_ALIAS, .bank_fieldoffsets =3D { offsetofhigh32(CPUARMState, cp15.tcr_el[3]), offsetofhigh32(CPUARMState, cp15.tcr_el[1]) }, }; @@ -4113,12 +4139,12 @@ static const ARMCPRegInfo lpae_cp_reginfo[] =3D { /* NOP AMAIR0/1 */ { .name =3D "AMAIR0", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 10, .crm =3D 3, .opc1 =3D 0, .opc2 =3D 0, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, /* AMAIR1 is mapped to AMAIR_EL1[63:32] */ { .name =3D "AMAIR1", .cp =3D 15, .crn =3D 10, .crm =3D 3, .opc1 =3D 0= , .opc2 =3D 1, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "PAR", .cp =3D 15, .crm =3D 7, .opc1 =3D 0, .access =3D PL1_RW, .type =3D ARM_CP_64BIT, .resetvalue =3D 0, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.par_s), @@ -4844,7 +4870,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .type =3D ARM_CP_NOP, .access =3D PL1_W }, /* MMU Domain access control / MPU write buffer control */ { .name =3D "DACR", .cp =3D 15, .opc1 =3D 0, .crn =3D 3, .crm =3D 0, .= opc2 =3D 0, - .access =3D PL1_RW, .resetvalue =3D 0, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .resetvalue =3D 0, .writefn =3D dacr_write, .raw_writefn =3D raw_write, .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.dacr_s), offsetoflow32(CPUARMState, cp15.dacr_ns) } }, @@ -7652,7 +7678,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) ARMCPRegInfo sctlr =3D { .name =3D "SCTLR", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 =3D 0, - .access =3D PL1_RW, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.sctlr_s), offsetof(CPUARMState, cp15.sctlr_ns) }, .writefn =3D sctlr_write, .resetvalue =3D cpu->reset_sctlr, --=20 2.20.1