From nobody Mon Feb 9 20:31:32 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581704530421167.87179507685778; Fri, 14 Feb 2020 10:22:10 -0800 (PST) Received: from localhost ([::1]:43676 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2fbN-0008Lh-6B for importer@patchew.org; Fri, 14 Feb 2020 13:22:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60832) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2fVP-0004LD-1L for qemu-devel@nongnu.org; Fri, 14 Feb 2020 13:16:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j2fVN-00006I-GB for qemu-devel@nongnu.org; Fri, 14 Feb 2020 13:15:58 -0500 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:44087) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j2fVN-00005y-9p for qemu-devel@nongnu.org; Fri, 14 Feb 2020 13:15:57 -0500 Received: by mail-pg1-x543.google.com with SMTP id g3so5208354pgs.11 for ; Fri, 14 Feb 2020 10:15:57 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id i3sm7525123pfg.94.2020.02.14.10.15.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Feb 2020 10:15:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bLNTrgdvvZF7PnSY+r2yk4nJu3Fd25nqdhwKgVxP4y8=; b=GYKE089kTv91kmETyK0jyL74T8rE1zGRPjFKDuqFK8x9NzrPETSanVvoPuwszh31Qd DYH0f2BzDma5lvrDsxbW/qo5QHMoq98SXd5BE9hxCz4QhG2s3RmsySrQ/A6639kLyqkV wOXnN/9z77VRB4xks2cayOhzcySgt3hSD5KpYkPDS/HX+ABuC3emLNWzwauHFs+wLB5h D0t0aN59cZBO6Yj+ze09kLd37i8dmkxaDJQ0zLxiEPANyeJIBQTs+1R3/xPnYesUo3mi tQgT0nVXebtfJfw8NwTT+w9+vX5OcmI5rjB0/ZRbPCyAyeujbEujodmrVU8dkWkx2HW3 HPZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bLNTrgdvvZF7PnSY+r2yk4nJu3Fd25nqdhwKgVxP4y8=; b=fWt4oPGEqkJgZg3aXYfoE5+cvUp2JNBMQX9bhjw7MOsX8OhV6jD7MuCGbBku1G+YGL 3zY7FDdMEy/SNNPfsrxUKfb4kzYFhrIipHFtvwmgot2Ev3XxnCJWaeMShKaQyipVXpKo xaY3Muy7sYF0P9NvmyamP2sFWp5FPM+FwHngmDk0luYb6VzvE432n+Lq5E38GdgMEr9U M5/gTLCNwe+rAAIW/AS/Q4tBfy0SJ9tlBWzja2Gj+m5nrZW+uPqZjHXM4d4t7sNm/VQc /2O/T+ZR/cv57+oULeN4iJLmjlnSVzrcby6l36TH3UnbOGqXen/X3VHynGLJdjIvfVSS NVoA== X-Gm-Message-State: APjAAAVVZSU9DZd3ysyAcu6yPTK5X89TSl14wK/VZif8CazBjK6aeM6Z I9PS46mqWSQoSYO67xWoLiq0s6+CNWc= X-Google-Smtp-Source: APXvYqw3x3UjxGmwNCl2/4Gd92AQHYyZfRgVgmNMG3ZtoeYuSY9UgLMiw4vhyTvhDpRzmWxQmstvhw== X-Received: by 2002:a63:9257:: with SMTP id s23mr5037458pgn.0.1581704155908; Fri, 14 Feb 2020 10:15:55 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 06/19] target/arm: Rename isar_feature_aa32_fpdp_v2 Date: Fri, 14 Feb 2020 10:15:34 -0800 Message-Id: <20200214181547.21408-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200214181547.21408-1-richard.henderson@linaro.org> References: <20200214181547.21408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The old name, isar_feature_aa32_fpdp, does not reflect that the test includes VFPv2. We will introduce another feature tests for VFPv3. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpu.h | 4 ++-- target/arm/translate-vfp.inc.c | 40 +++++++++++++++++----------------- 2 files changed, 22 insertions(+), 22 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 85b90eaed2..5f08cbd2d8 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3429,9 +3429,9 @@ static inline bool isar_feature_aa32_fpshvec(const AR= MISARegisters *id) return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0; } =20 -static inline bool isar_feature_aa32_fpdp(const ARMISARegisters *id) +static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id) { - /* Return true if CPU supports double precision floating point */ + /* Return true if CPU supports double precision floating point, VFPv2 = */ return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0; } =20 diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 96a1d727c6..5290828d0d 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -206,7 +206,7 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) return false; } =20 - if (dp && !dc_isar_feature(aa32_fpdp, s)) { + if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -339,7 +339,7 @@ static bool trans_VMINMAXNM(DisasContext *s, arg_VMINMA= XNM *a) return false; } =20 - if (dp && !dc_isar_feature(aa32_fpdp, s)) { + if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -425,7 +425,7 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a) return false; } =20 - if (dp && !dc_isar_feature(aa32_fpdp, s)) { + if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -488,7 +488,7 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) return false; } =20 - if (dp && !dc_isar_feature(aa32_fpdp, s)) { + if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -1313,7 +1313,7 @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpD= PFn *fn, return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -1462,7 +1462,7 @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpD= PFn *fn, int vd, int vm) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -1826,7 +1826,7 @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp = *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -1925,7 +1925,7 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VM= OV_imm_dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2069,7 +2069,7 @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_d= p *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2142,7 +2142,7 @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_V= CVT_f64_f16 *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2208,7 +2208,7 @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_V= CVT_f16_f64 *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2268,7 +2268,7 @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRIN= TR_dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2329,7 +2329,7 @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRIN= TZ_dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2388,7 +2388,7 @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRIN= TX_dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2416,7 +2416,7 @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_s= p *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2444,7 +2444,7 @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_d= p *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2498,7 +2498,7 @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_VC= VT_int_dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2538,7 +2538,7 @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2631,7 +2631,7 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VC= VT_fix_dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2727,7 +2727,7 @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VC= VT_dp_int *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 --=20 2.20.1