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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id i3sm7525123pfg.94.2020.02.14.10.15.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Feb 2020 10:15:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WVNZD9ad+przMHF0OKz5odOrKHpFBH9KJ8cJLa9N9Zg=; b=KT9j2MfjOXeXJVi7VqQjJ+K0N41/v9gusJAx9FpN1q/USdFibu9jrzKIfZM0v4a2Ok p2eySqyoiz7Yiri6CiPyvpxk3JDU9HKC0D452cUFpm+mk6/vfGiBRvbdaGRze4ih7+B4 UFfVJtA0PM45PmHV0uFOEWHXmTEzR6ScLf6BS6zAo8LWv23q1vHsigLr00ahcDX4mhVv ZkO2cJZv4RC4QlzNNtGsTV+BpxuHVjss7Lyoq7JiZ0hjzPJlP3QRWkVK+3wshi7pSUuy IQxR5g5P5y9cBOVLB5jEfuY1uIePXS8MN9MPPmLTAXC8sQr7w30P9MPCsSszHPpPZK4F /zcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WVNZD9ad+przMHF0OKz5odOrKHpFBH9KJ8cJLa9N9Zg=; b=GsEGPIMnjym9xZK39gVAI3jx85OYvWwsVu0ToyZVDtjVzcVxZQd+5+gxO1UIvBfM0F XGEJkUGR3Nk6rO2hkS5Z5PQF9S12eEVoinRka6XCCbPsBebFRzCFdqFStavKU1AjbV9I fgR4kEOSEh6t+2vncHXQ0VB7INAgE/IZAfoDilyJyJuzZAq27OQf4u+lXJVmdOjtJeuE Mx3LAD26Pyo/51pOAAdz6qY1q4qTqRPbmZtbG0bQp8leoxUZ+QSFBq44mM8vrWKZE5l9 LnNKjkp069ONAeQmtuvVP5gy3gDolkU8GAdb+V9+5kav1QXT742pWuf4Ip9WRqnBpQI9 E00A== X-Gm-Message-State: APjAAAVjhJyeJu+HsxZFbX88+9yKSis1FD1IZjViAArL7ffr3PICzkPL 6fZcZutBcxnqZXxWR1DAyYYVieieXnc= X-Google-Smtp-Source: APXvYqwQAirYuZYjjvW7i4TGK7e292EzW0GG9p4Kvwps/XyExe3/N6ftiWo5dg8nxlUGO8ec3XU41A== X-Received: by 2002:a17:902:6ac7:: with SMTP id i7mr4479347plt.66.1581704153452; Fri, 14 Feb 2020 10:15:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 04/19] target/arm: Set MVFR0.FPSP for ARMv5 cpus Date: Fri, 14 Feb 2020 10:15:32 -0800 Message-Id: <20200214181547.21408-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200214181547.21408-1-richard.henderson@linaro.org> References: <20200214181547.21408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" We are going to convert FEATURE tests to ISAR tests, so FPSP needs to be set for these cpus, like we have already for FPDP. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index f0bd419dd8..92006e56c8 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1869,10 +1869,11 @@ static void arm926_initfn(Object *obj) */ cpu->isar.id_isar1 =3D FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELL= E, 1); /* - * Similarly, we need to set MVFR0 fields to enable double precision - * and short vector support even though ARMv5 doesn't have this regist= er. + * Similarly, we need to set MVFR0 fields to enable vfp and short vect= or + * support even though ARMv5 doesn't have this register. */ cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); + cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1); cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1); } =20 @@ -1911,10 +1912,11 @@ static void arm1026_initfn(Object *obj) */ cpu->isar.id_isar1 =3D FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELL= E, 1); /* - * Similarly, we need to set MVFR0 fields to enable double precision - * and short vector support even though ARMv5 doesn't have this regist= er. + * Similarly, we need to set MVFR0 fields to enable vfp and short vect= or + * support even though ARMv5 doesn't have this register. */ cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); + cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1); cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1); =20 { --=20 2.20.1