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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id i3sm7525123pfg.94.2020.02.14.10.15.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Feb 2020 10:15:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RVsYrCWRH15jUkV+nOTPRiB+8FHjPwEImYNiw048qj0=; b=kaX2BiSmMPf/dfANlgf46MUoRKKJDjpVu6h1ilLmhlQBV4XnDzZZWN9aBQNbaFjb4O /J4/zU3BOhvSmsgPTaR+FW3TMwszwTCJjT6AW9m8TjuYtPNNO/bunaoEs9QOThwbzYeF v8aZ1dyAXdI5lZGbb2bKLgMPJlZ8RQwdAjNtUdgRDZsfvd2Lw66BoI7cUigQFSMRWlOp mzm93p2rYHQypeJPShBHctNU9eRYN03cIDsAU/9FDYFucEJm/hEyznn8ZDWkw7GAzGik xX9PBH8w/pdnVXzALsg0QWNrktrWW9MS/+H7vZzChZhyKeIyUugB+CdDIQVY7B1LmJ1E bDyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RVsYrCWRH15jUkV+nOTPRiB+8FHjPwEImYNiw048qj0=; b=rJVat+HxPp0VL4GYSdL72N2q4lrv88Gd7nxrNYrhF9pPlOqcpTf4XTASMC0o/eRQvN i6SeRMa5BaGC6XeZy/ErBmmKr+Cc+Asik3+V/w6+glzcPPMs9CZ+L+R12mRbYKT8jo0R /ZIoTHrkdyD/31PueQqythagrX0STzIztx0iwbhQL8Wyzjl3lCqPijX5rRB2omZ5iEEL 3Gj10cnuY6fbEUcCr3o3TvH7w5cyZvJObohqOlJhBb26i+RcVUXE9F4C4/xzSt6aiLTq wWzJO8MrCaldAP/wVO3LWYw9FscaYfXfQxg+d2e+eJXH2DuwTDkteJg2eZwFuXYFPDo8 GD1g== X-Gm-Message-State: APjAAAV1gLByxS1F/+dV2SmDJmff+KD18nevOrVp9+WkZMtOcB5r91f5 1muFIHf+nSzEQ1kwQNEwHVlwa+vWyfQ= X-Google-Smtp-Source: APXvYqyKdviVyFbFySrHUtnJbmNWIzOfTuf4gND+ozEmjKTqwzZmtF6Y3DC0MQcRPDDyH0NO4i4tAA== X-Received: by 2002:a17:902:b116:: with SMTP id q22mr4689987plr.324.1581704149957; Fri, 14 Feb 2020 10:15:49 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 01/19] target/arm: Fix field extract from MVFR[0-2] Date: Fri, 14 Feb 2020 10:15:29 -0800 Message-Id: <20200214181547.21408-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200214181547.21408-1-richard.henderson@linaro.org> References: <20200214181547.21408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1043 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" These registers are 32-bits wide. Cut and paste used FIELD_EX64 instead of the more proper FIELD_EX32. In practice all this did was use an unnecessary 64-bit operation, producing correct results. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpu.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e943ffe8a9..28cb2be6fc 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3415,18 +3415,18 @@ static inline bool isar_feature_aa32_fp16_arith(con= st ARMISARegisters *id) static inline bool isar_feature_aa32_fp_d32(const ARMISARegisters *id) { /* Return true if D16-D31 are implemented */ - return FIELD_EX64(id->mvfr0, MVFR0, SIMDREG) >=3D 2; + return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) >=3D 2; } =20 static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id) { - return FIELD_EX64(id->mvfr0, MVFR0, FPSHVEC) > 0; + return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0; } =20 static inline bool isar_feature_aa32_fpdp(const ARMISARegisters *id) { /* Return true if CPU supports double precision floating point */ - return FIELD_EX64(id->mvfr0, MVFR0, FPDP) > 0; + return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0; } =20 /* @@ -3436,32 +3436,32 @@ static inline bool isar_feature_aa32_fpdp(const ARM= ISARegisters *id) */ static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id) { - return FIELD_EX64(id->mvfr1, MVFR1, FPHP) > 0; + return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 0; } =20 static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id) { - return FIELD_EX64(id->mvfr1, MVFR1, FPHP) > 1; + return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1; } =20 static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id) { - return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >=3D 1; + return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >=3D 1; } =20 static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id) { - return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >=3D 2; + return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >=3D 2; } =20 static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id) { - return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >=3D 3; + return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >=3D 3; } =20 static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id) { - return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >=3D 4; + return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >=3D 4; } =20 static inline bool isar_feature_aa32_pan(const ARMISARegisters *id) --=20 2.20.1 From nobody Fri Mar 29 00:38:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581704361617813.5894659370814; Fri, 14 Feb 2020 10:19:21 -0800 (PST) Received: from localhost ([::1]:43554 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2fYe-0001Q4-7P for importer@patchew.org; Fri, 14 Feb 2020 13:19:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60770) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2fVK-0004Du-Fu for qemu-devel@nongnu.org; Fri, 14 Feb 2020 13:15:56 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j2fVI-0008VC-QV for qemu-devel@nongnu.org; Fri, 14 Feb 2020 13:15:54 -0500 Received: from mail-pl1-x641.google.com ([2607:f8b0:4864:20::641]:36870) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j2fVI-0008Up-IV for qemu-devel@nongnu.org; Fri, 14 Feb 2020 13:15:52 -0500 Received: by mail-pl1-x641.google.com with SMTP id c23so4018197plz.4 for ; Fri, 14 Feb 2020 10:15:52 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id i3sm7525123pfg.94.2020.02.14.10.15.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Feb 2020 10:15:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NUF6GFUiKTx14rAhTmcqLDxmnGq1A1fKejGqoveF2Lc=; b=cVrQCDHFGN60z+AcOJDcrqN52UvAmXhlhWhM7f8XzcL9OyJeoSH/YlH63GXx0yxZbu g9DFvLbRbAjoiqZEANi8Fat2RparP5X+w6vDo6BNrKRryv1+YeMHZ0Gb18xWiNAPrpkq F4TxXapjBRDmWpMjDYuVuXadFC1TPfzvXTHikfmKy8iqNVL25sj5Yw+53f1c17Ugf1eZ Zdm1BzfaZbAq++GWXs3jJaGypYNFLCopasG7NfQ7wzDQ3MZnNyWawI46END2f4b4zKMs EzM7Hfl9+6glifyGJtYYE3MrTFl7jk8fghHe9JaB2NCE44vzJufyINgFCIv+mVmgRoi3 TAxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NUF6GFUiKTx14rAhTmcqLDxmnGq1A1fKejGqoveF2Lc=; b=T1ENW4PTC3a2uAwm2wZ0OyXFQO9Cn//vSMf90AD93v/BIX6aLlJ2ZmbZMyKf5Zc9ut xpJ9jfL5tNozKjqoT9gj2tzAIv1w8zYZh0V1imJCYT/Xe49qAPeUph+wXopNxGuTceMr oCXen8eaxhRi9W8d5x1YJ4ljxpARteyhjNCJ0nZVlWDABh24cV579AVNrkLhPrFKar1w nvXSg5zXg6TRa4laBl9ApgKAiRYliCPEDWhCabr082Yeo+V3bdaPJHCMOgqeON6GJFJ1 eWC+2GEtfC8+r32f3lvOjtBEioet2Lsp+GT7n3Nc2m5tbT1DKS1jVoAIcW3GtoyElJ2s 2YFg== X-Gm-Message-State: APjAAAWMmPomzkdRpZfdCVGnGpYHiF2hf+okD3mLzltBs4fq6lx2udYT h6xrC6X6keoRYM4npYx9xAaU9D6o8CI= X-Google-Smtp-Source: APXvYqwBsEH53EWgOTUGzhPfGyzUCA+J8ZUe9/f1Vvo/8z0dHWfglCGkp089Ysx1y/MW6718gUPwGw== X-Received: by 2002:a17:902:9b8a:: with SMTP id y10mr4357682plp.114.1581704151005; Fri, 14 Feb 2020 10:15:51 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 02/19] target/arm: Rename isar_feature_aa32_simd_r32 Date: Fri, 14 Feb 2020 10:15:30 -0800 Message-Id: <20200214181547.21408-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200214181547.21408-1-richard.henderson@linaro.org> References: <20200214181547.21408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The old name, isar_feature_aa32_fp_d32, does not reflect the MVFR0 field name, SIMDReg. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpu.h | 2 +- target/arm/translate-vfp.inc.c | 52 +++++++++++++++++----------------- 2 files changed, 27 insertions(+), 27 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 28cb2be6fc..f7139db02d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3412,7 +3412,7 @@ static inline bool isar_feature_aa32_fp16_arith(const= ARMISARegisters *id) return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) =3D=3D 1; } =20 -static inline bool isar_feature_aa32_fp_d32(const ARMISARegisters *id) +static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id) { /* Return true if D16-D31 are implemented */ return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) >=3D 2; diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index bf90ac0e5b..96a1d727c6 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -201,7 +201,7 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist */ - if (dp && !dc_isar_feature(aa32_fp_d32, s) && + if (dp && !dc_isar_feature(aa32_simd_r32, s) && ((a->vm | a->vn | a->vd) & 0x10)) { return false; } @@ -334,7 +334,7 @@ static bool trans_VMINMAXNM(DisasContext *s, arg_VMINMA= XNM *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist */ - if (dp && !dc_isar_feature(aa32_fp_d32, s) && + if (dp && !dc_isar_feature(aa32_simd_r32, s) && ((a->vm | a->vn | a->vd) & 0x10)) { return false; } @@ -420,7 +420,7 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist */ - if (dp && !dc_isar_feature(aa32_fp_d32, s) && + if (dp && !dc_isar_feature(aa32_simd_r32, s) && ((a->vm | a->vd) & 0x10)) { return false; } @@ -484,7 +484,7 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist */ - if (dp && !dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) { + if (dp && !dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { return false; } =20 @@ -556,7 +556,7 @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_= to_gp *a) uint32_t offset; =20 /* UNDEF accesses to D16-D31 if they don't exist */ - if (!dc_isar_feature(aa32_fp_d32, s) && (a->vn & 0x10)) { + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) { return false; } =20 @@ -615,7 +615,7 @@ static bool trans_VMOV_from_gp(DisasContext *s, arg_VMO= V_from_gp *a) uint32_t offset; =20 /* UNDEF accesses to D16-D31 if they don't exist */ - if (!dc_isar_feature(aa32_fp_d32, s) && (a->vn & 0x10)) { + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) { return false; } =20 @@ -662,7 +662,7 @@ static bool trans_VDUP(DisasContext *s, arg_VDUP *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist */ - if (!dc_isar_feature(aa32_fp_d32, s) && (a->vn & 0x10)) { + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) { return false; } =20 @@ -912,7 +912,7 @@ static bool trans_VMOV_64_dp(DisasContext *s, arg_VMOV_= 64_dp *a) */ =20 /* UNDEF accesses to D16-D31 if they don't exist */ - if (!dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) { + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { return false; } =20 @@ -978,7 +978,7 @@ static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_VLD= R_VSTR_dp *a) TCGv_i64 tmp; =20 /* UNDEF accesses to D16-D31 if they don't exist */ - if (!dc_isar_feature(aa32_fp_d32, s) && (a->vd & 0x10)) { + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { return false; } =20 @@ -1101,7 +1101,7 @@ static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_V= LDM_VSTM_dp *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist */ - if (!dc_isar_feature(aa32_fp_d32, s) && (a->vd + n) > 16) { + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd + n) > 16) { return false; } =20 @@ -1309,7 +1309,7 @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpD= PFn *fn, TCGv_ptr fpst; =20 /* UNDEF accesses to D16-D31 if they don't exist */ - if (!dc_isar_feature(aa32_fp_d32, s) && ((vd | vn | vm) & 0x10)) { + if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vn | vm) & 0x10)) { return false; } =20 @@ -1458,7 +1458,7 @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpD= PFn *fn, int vd, int vm) TCGv_i64 f0, fd; =20 /* UNDEF accesses to D16-D31 if they don't exist */ - if (!dc_isar_feature(aa32_fp_d32, s) && ((vd | vm) & 0x10)) { + if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vm) & 0x10)) { return false; } =20 @@ -1822,7 +1822,7 @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp = *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_fp_d32, s) && ((a->vd | a->vn | a->vm) & 0x1= 0)) { + if (!dc_isar_feature(aa32_simd_r32, s) && ((a->vd | a->vn | a->vm) & 0= x10)) { return false; } =20 @@ -1921,7 +1921,7 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VM= OV_imm_dp *a) vd =3D a->vd; =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_fp_d32, s) && (vd & 0x10)) { + if (!dc_isar_feature(aa32_simd_r32, s) && (vd & 0x10)) { return false; } =20 @@ -2065,7 +2065,7 @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_d= p *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_fp_d32, s) && ((a->vd | a->vm) & 0x10)) { + if (!dc_isar_feature(aa32_simd_r32, s) && ((a->vd | a->vm) & 0x10)) { return false; } =20 @@ -2138,7 +2138,7 @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_V= CVT_f64_f16 *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_fp_d32, s) && (a->vd & 0x10)) { + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { return false; } =20 @@ -2204,7 +2204,7 @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_V= CVT_f16_f64 *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) { + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { return false; } =20 @@ -2264,7 +2264,7 @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRIN= TR_dp *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_fp_d32, s) && ((a->vd | a->vm) & 0x10)) { + if (!dc_isar_feature(aa32_simd_r32, s) && ((a->vd | a->vm) & 0x10)) { return false; } =20 @@ -2325,7 +2325,7 @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRIN= TZ_dp *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_fp_d32, s) && ((a->vd | a->vm) & 0x10)) { + if (!dc_isar_feature(aa32_simd_r32, s) && ((a->vd | a->vm) & 0x10)) { return false; } =20 @@ -2384,7 +2384,7 @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRIN= TX_dp *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_fp_d32, s) && ((a->vd | a->vm) & 0x10)) { + if (!dc_isar_feature(aa32_simd_r32, s) && ((a->vd | a->vm) & 0x10)) { return false; } =20 @@ -2412,7 +2412,7 @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_s= p *a) TCGv_i32 vm; =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_fp_d32, s) && (a->vd & 0x10)) { + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { return false; } =20 @@ -2440,7 +2440,7 @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_d= p *a) TCGv_i32 vd; =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) { + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { return false; } =20 @@ -2494,7 +2494,7 @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_VC= VT_int_dp *a) TCGv_ptr fpst; =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_fp_d32, s) && (a->vd & 0x10)) { + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { return false; } =20 @@ -2534,7 +2534,7 @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) { + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { return false; } =20 @@ -2627,7 +2627,7 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VC= VT_fix_dp *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_fp_d32, s) && (a->vd & 0x10)) { + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { return false; } =20 @@ -2723,7 +2723,7 @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VC= VT_dp_int *a) TCGv_ptr fpst; =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) { + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { return false; } =20 --=20 2.20.1 From nobody Fri Mar 29 00:38:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id i3sm7525123pfg.94.2020.02.14.10.15.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Feb 2020 10:15:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5fLn0UXMjSHE5U0IwLqHf4IaIEWWE0KQrcA+POHthnY=; b=do1S7mngwHwsUTsAmswxZIjWpSdFYZnLCYR1NddDX+iS1/Gw+R31l747vG8/0z7ORB IEajb831aH8oM3BStDZawaBfh9s8jYBzxWVfQ1qEqNrrQyxpNANIWHcFJuL9izQpaHAi Wew71zSPptaqJuawcYh9Oi4NpZ+9Y2bY09cGHQzyPM/5ilGYWDZQ2+D/xQ9KF+EiaCli 1MGfjVyOEjHrFY6Ru+vnZfmUctubMIEVgNwjXyCaRuG/WRXuWeLyiRuwLpafwJ9IsfLe Z7rTnHQnt4lofiG5POoPUS2SKzZ2iXdOk7oUZf29ZdQH7ej/XxfOqs3eR0mSbrdnI8Hh RhrA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5fLn0UXMjSHE5U0IwLqHf4IaIEWWE0KQrcA+POHthnY=; b=nzaQXBDLE9Uj8AyEiXzpil6kKUrGXtNTZxYuBBxzgoK0IbYeV/2UgC/52IAHMt9lO5 zK65ApjMcS4Ug59Tb+/JOjP88IIbtpiD2erkv2jTwlNFSqbljf5jAm7KTEwS++JNDHtf LT3z1rVViWFmFKeYzKHQMCmCjCrMVXz7aec9QwaBJyupeQeQfxIRl1EHxgZoKmaR8b8y XOEvOZt4UNQKQiZn1xnfT8Ld44+n14gn02mEDSuCpixSdoGQce6eB5frM/pRNOY9fGvl HcwgoiTE9/CQ1dcEWQ7F5r3X45EU8ggfmCzOU7t/hbkpwKy8EBMubDf8cuFFV8B3hcJC eo3A== X-Gm-Message-State: APjAAAUDtLrxa+CSs+w0kS/4OAccIgJ1EbkVeT0NoAAqL23kz4nxL3N0 ZecrfBTwlsgZgZuP5T4mdF3PT5nfXsE= X-Google-Smtp-Source: APXvYqwLbc8YXcfB7C15m9rsmQ0pDfhW0V+dK+DrGBl8c9b00IZ1txzhMUYWR4Vt7zuH32WJjp6gyA== X-Received: by 2002:a17:902:8f94:: with SMTP id z20mr4695199plo.62.1581704152332; Fri, 14 Feb 2020 10:15:52 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 03/19] target/arm: Use isar_feature_aa32_simd_r32 more places Date: Fri, 14 Feb 2020 10:15:31 -0800 Message-Id: <20200214181547.21408-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200214181547.21408-1-richard.henderson@linaro.org> References: <20200214181547.21408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1043 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Many uses of ARM_FEATURE_VFP3 are testing for the number of simd registers implemented. Use the proper test vs MVCR0.SIMDReg. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.c | 9 ++++----- target/arm/helper.c | 13 ++++++------- target/arm/translate.c | 2 +- 3 files changed, 11 insertions(+), 13 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index de733aceeb..f0bd419dd8 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1009,11 +1009,10 @@ static void arm_cpu_dump_state(CPUState *cs, FILE *= f, int flags) =20 if (flags & CPU_DUMP_FPU) { int numvfpregs =3D 0; - if (arm_feature(env, ARM_FEATURE_VFP)) { - numvfpregs +=3D 16; - } - if (arm_feature(env, ARM_FEATURE_VFP3)) { - numvfpregs +=3D 16; + if (cpu_isar_feature(aa32_simd_r32, cpu)) { + numvfpregs =3D 32; + } else if (arm_feature(env, ARM_FEATURE_VFP)) { + numvfpregs =3D 16; } for (i =3D 0; i < numvfpregs; i++) { uint64_t v =3D *aa32_vfp_dreg(env, i); diff --git a/target/arm/helper.c b/target/arm/helper.c index 366dbcf460..0eeedc3c18 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -49,10 +49,10 @@ static void switch_mode(CPUARMState *env, int mode); =20 static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) { - int nregs; + ARMCPU *cpu =3D env_archcpu(env); + int nregs =3D cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16; =20 /* VFP data registers are always little-endian. */ - nregs =3D arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; if (reg < nregs) { stq_le_p(buf, *aa32_vfp_dreg(env, reg)); return 8; @@ -77,9 +77,9 @@ static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf= , int reg) =20 static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) { - int nregs; + ARMCPU *cpu =3D env_archcpu(env); + int nregs =3D cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16; =20 - nregs =3D arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; if (reg < nregs) { *aa32_vfp_dreg(env, reg) =3D ldq_le_p(buf); return 8; @@ -905,8 +905,7 @@ static void cpacr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, /* VFPv3 and upwards with NEON implement 32 double precision * registers (D0-D31). */ - if (!arm_feature(env, ARM_FEATURE_NEON) || - !arm_feature(env, ARM_FEATURE_VFP3)) { + if (!cpu_isar_feature(aa32_simd_r32, env_archcpu(env))) { /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */ value |=3D (1 << 30); } @@ -7755,7 +7754,7 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *c= pu) } else if (arm_feature(env, ARM_FEATURE_NEON)) { gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, 51, "arm-neon.xml", 0); - } else if (arm_feature(env, ARM_FEATURE_VFP3)) { + } else if (cpu_isar_feature(aa32_simd_r32, cpu)) { gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, 35, "arm-vfp3.xml", 0); } else if (arm_feature(env, ARM_FEATURE_VFP)) { diff --git a/target/arm/translate.c b/target/arm/translate.c index 20f89ace2f..3b9bf13933 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -2612,7 +2612,7 @@ static int disas_dsp_insn(DisasContext *s, uint32_t i= nsn) #define VFP_SREG(insn, bigbit, smallbit) \ ((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1)) #define VFP_DREG(reg, insn, bigbit, smallbit) do { \ - if (arm_dc_feature(s, ARM_FEATURE_VFP3)) { \ + if (dc_isar_feature(aa32_simd_r32, s)) { \ reg =3D (((insn) >> (bigbit)) & 0x0f) \ | (((insn) >> ((smallbit) - 4)) & 0x10); \ } else { \ --=20 2.20.1 From nobody Fri Mar 29 00:38:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581704448679748.6350844312549; Fri, 14 Feb 2020 10:20:48 -0800 (PST) Received: from localhost ([::1]:43633 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2fa3-0004t0-EE for importer@patchew.org; Fri, 14 Feb 2020 13:20:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60794) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2fVL-0004I9-Sp for qemu-devel@nongnu.org; Fri, 14 Feb 2020 13:15:56 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j2fVK-00004z-UH for qemu-devel@nongnu.org; Fri, 14 Feb 2020 13:15:55 -0500 Received: from mail-pl1-x643.google.com ([2607:f8b0:4864:20::643]:43505) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j2fVK-0008WF-Om for qemu-devel@nongnu.org; Fri, 14 Feb 2020 13:15:54 -0500 Received: by mail-pl1-x643.google.com with SMTP id p11so4004581plq.10 for ; Fri, 14 Feb 2020 10:15:54 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id i3sm7525123pfg.94.2020.02.14.10.15.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Feb 2020 10:15:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WVNZD9ad+przMHF0OKz5odOrKHpFBH9KJ8cJLa9N9Zg=; b=KT9j2MfjOXeXJVi7VqQjJ+K0N41/v9gusJAx9FpN1q/USdFibu9jrzKIfZM0v4a2Ok p2eySqyoiz7Yiri6CiPyvpxk3JDU9HKC0D452cUFpm+mk6/vfGiBRvbdaGRze4ih7+B4 UFfVJtA0PM45PmHV0uFOEWHXmTEzR6ScLf6BS6zAo8LWv23q1vHsigLr00ahcDX4mhVv ZkO2cJZv4RC4QlzNNtGsTV+BpxuHVjss7Lyoq7JiZ0hjzPJlP3QRWkVK+3wshi7pSUuy IQxR5g5P5y9cBOVLB5jEfuY1uIePXS8MN9MPPmLTAXC8sQr7w30P9MPCsSszHPpPZK4F /zcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WVNZD9ad+przMHF0OKz5odOrKHpFBH9KJ8cJLa9N9Zg=; b=GsEGPIMnjym9xZK39gVAI3jx85OYvWwsVu0ToyZVDtjVzcVxZQd+5+gxO1UIvBfM0F XGEJkUGR3Nk6rO2hkS5Z5PQF9S12eEVoinRka6XCCbPsBebFRzCFdqFStavKU1AjbV9I fgR4kEOSEh6t+2vncHXQ0VB7INAgE/IZAfoDilyJyJuzZAq27OQf4u+lXJVmdOjtJeuE Mx3LAD26Pyo/51pOAAdz6qY1q4qTqRPbmZtbG0bQp8leoxUZ+QSFBq44mM8vrWKZE5l9 LnNKjkp069ONAeQmtuvVP5gy3gDolkU8GAdb+V9+5kav1QXT742pWuf4Ip9WRqnBpQI9 E00A== X-Gm-Message-State: APjAAAVjhJyeJu+HsxZFbX88+9yKSis1FD1IZjViAArL7ffr3PICzkPL 6fZcZutBcxnqZXxWR1DAyYYVieieXnc= X-Google-Smtp-Source: APXvYqwQAirYuZYjjvW7i4TGK7e292EzW0GG9p4Kvwps/XyExe3/N6ftiWo5dg8nxlUGO8ec3XU41A== X-Received: by 2002:a17:902:6ac7:: with SMTP id i7mr4479347plt.66.1581704153452; Fri, 14 Feb 2020 10:15:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 04/19] target/arm: Set MVFR0.FPSP for ARMv5 cpus Date: Fri, 14 Feb 2020 10:15:32 -0800 Message-Id: <20200214181547.21408-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200214181547.21408-1-richard.henderson@linaro.org> References: <20200214181547.21408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" We are going to convert FEATURE tests to ISAR tests, so FPSP needs to be set for these cpus, like we have already for FPDP. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index f0bd419dd8..92006e56c8 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1869,10 +1869,11 @@ static void arm926_initfn(Object *obj) */ cpu->isar.id_isar1 =3D FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELL= E, 1); /* - * Similarly, we need to set MVFR0 fields to enable double precision - * and short vector support even though ARMv5 doesn't have this regist= er. + * Similarly, we need to set MVFR0 fields to enable vfp and short vect= or + * support even though ARMv5 doesn't have this register. */ cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); + cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1); cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1); } =20 @@ -1911,10 +1912,11 @@ static void arm1026_initfn(Object *obj) */ cpu->isar.id_isar1 =3D FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELL= E, 1); /* - * Similarly, we need to set MVFR0 fields to enable double precision - * and short vector support even though ARMv5 doesn't have this regist= er. + * Similarly, we need to set MVFR0 fields to enable vfp and short vect= or + * support even though ARMv5 doesn't have this register. */ cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); + cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1); cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1); =20 { --=20 2.20.1 From nobody Fri Mar 29 00:38:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581704603133699.3783176755318; Fri, 14 Feb 2020 10:23:23 -0800 (PST) Received: from localhost ([::1]:43720 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2fcX-0002Sd-Nz for importer@patchew.org; Fri, 14 Feb 2020 13:23:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60826) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2fVO-0004Kp-PL for qemu-devel@nongnu.org; Fri, 14 Feb 2020 13:16:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j2fVM-000062-S1 for qemu-devel@nongnu.org; Fri, 14 Feb 2020 13:15:58 -0500 Received: from mail-pg1-x544.google.com ([2607:f8b0:4864:20::544]:36589) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j2fVM-00005e-Ja for qemu-devel@nongnu.org; Fri, 14 Feb 2020 13:15:56 -0500 Received: by mail-pg1-x544.google.com with SMTP id d9so5353830pgu.3 for ; Fri, 14 Feb 2020 10:15:56 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id i3sm7525123pfg.94.2020.02.14.10.15.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Feb 2020 10:15:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yuUusOCzpkaCF7XSY4s6jOjJNMax37vMLlyW3jWBGpE=; b=RwlhFhZIemAzDANaXXLgLvrWJdhU1rS2aHWE37Z5bcpzOPNKprdcW+w16M49XbCVkq ZxrIKzCnjgC5IOta7QZpQSS9PJCsQl9YggHWwSf0VWqxYpSo1gpz2SOihf2svhVvI6ZG 2fLNTRyWKwUofQFyMWX/9ZoOBF/f57IllmX2/HcMG+4nEXV0QU8nUzOlxU3mMmhpXjhZ oHFVxpxxs10iqAG+Qi1igT3HInBjj0yt5DymxJ2cdVYHxchKnhxXnjbRaPtECeD13h02 XFPI6qtAgmr5vxeIwtJ4VNkVaqpNS6zsYf87g0fODRPAltR4yeDf808qx279TeTYpyYb Fduw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yuUusOCzpkaCF7XSY4s6jOjJNMax37vMLlyW3jWBGpE=; b=cRPzQRnyxoebGFX8lK1qmw/kumj5/R2Y8cHvr2Iflf9mI0RakxI4wdcaSks03pZjRc kHJ/AcwOHEdryHv439V/9VzXPxusvwG1jhws+qN8OJUnAijTiSaW2zMDdvu3yYf5zKoX zDfg0uStLtuXt7o99OD0DSjZvEzrIB4FaWXtU4siFILTlejNyUTdnCx7mxvbXzPWoG4Y q6xCTKthjR753UoCXUOUWOFBjzPlzIlotNafpJHjycti/yn2lT1NCM62uFjbd21Rh3gm wNcmc4ikJq51R7fVB7wK7sWppFtY++Ey7ngwOAyH/RyFZMPWhiTd7Izdn4ij7fcY8fBn 6u2g== X-Gm-Message-State: APjAAAWMNsm8B50PCT6e9PfKv3mkGOTER0AI9THh2ZDWPbmQosdAYcla 7PKdG5GKURj6BoRSAYS5DYe67q0SyrQ= X-Google-Smtp-Source: APXvYqyZ3CtTIpNDXitfTN/u0yLypA0Tf0g+0sCSw3DaNpGIRQPgyA+N4Csr1ZE1D9ouSCFMOorv7A== X-Received: by 2002:a65:4b83:: with SMTP id t3mr4718725pgq.195.1581704154773; Fri, 14 Feb 2020 10:15:54 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 05/19] target/arm: Add isar_feature_aa32_simd_r16 Date: Fri, 14 Feb 2020 10:15:33 -0800 Message-Id: <20200214181547.21408-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200214181547.21408-1-richard.henderson@linaro.org> References: <20200214181547.21408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Use this in the places that were checking ARM_FEATURE_VFP, and are obviously testing for the existance of the register set as opposed to testing for some particular instruction extension. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 6 ++++++ hw/intc/armv7m_nvic.c | 20 ++++++++++---------- linux-user/arm/signal.c | 4 ++-- target/arm/arch_dump.c | 11 ++++++----- target/arm/cpu.c | 8 ++++---- target/arm/helper.c | 4 ++-- target/arm/m_helper.c | 11 ++++++----- target/arm/machine.c | 3 +-- 8 files changed, 37 insertions(+), 30 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index f7139db02d..85b90eaed2 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3412,6 +3412,12 @@ static inline bool isar_feature_aa32_fp16_arith(cons= t ARMISARegisters *id) return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) =3D=3D 1; } =20 +static inline bool isar_feature_aa32_simd_r16(const ARMISARegisters *id) +{ + /* Return true if D0-D15 are implemented */ + return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0; +} + static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id) { /* Return true if D16-D31 are implemented */ diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index f9e0eeaace..e5da962bb6 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1262,12 +1262,12 @@ static uint32_t nvic_readl(NVICState *s, uint32_t o= ffset, MemTxAttrs attrs) case 0xd84: /* CSSELR */ return cpu->env.v7m.csselr[attrs.secure]; case 0xd88: /* CPACR */ - if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (!cpu_isar_feature(aa32_simd_r16, cpu)) { return 0; } return cpu->env.v7m.cpacr[attrs.secure]; case 0xd8c: /* NSACR */ - if (!attrs.secure || !arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (!attrs.secure || !cpu_isar_feature(aa32_simd_r16, cpu)) { return 0; } return cpu->env.v7m.nsacr; @@ -1417,7 +1417,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t off= set, MemTxAttrs attrs) } return cpu->env.v7m.sfar; case 0xf34: /* FPCCR */ - if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (!cpu_isar_feature(aa32_simd_r16, cpu)) { return 0; } if (attrs.secure) { @@ -1444,12 +1444,12 @@ static uint32_t nvic_readl(NVICState *s, uint32_t o= ffset, MemTxAttrs attrs) return value; } case 0xf38: /* FPCAR */ - if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (!cpu_isar_feature(aa32_simd_r16, cpu)) { return 0; } return cpu->env.v7m.fpcar[attrs.secure]; case 0xf3c: /* FPDSCR */ - if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (!cpu_isar_feature(aa32_simd_r16, cpu)) { return 0; } return cpu->env.v7m.fpdscr[attrs.secure]; @@ -1711,13 +1711,13 @@ static void nvic_writel(NVICState *s, uint32_t offs= et, uint32_t value, } break; case 0xd88: /* CPACR */ - if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_simd_r16, cpu)) { /* We implement only the Floating Point extension's CP10/CP11 = */ cpu->env.v7m.cpacr[attrs.secure] =3D value & (0xf << 20); } break; case 0xd8c: /* NSACR */ - if (attrs.secure && arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (attrs.secure && cpu_isar_feature(aa32_simd_r16, cpu)) { /* We implement only the Floating Point extension's CP10/CP11 = */ cpu->env.v7m.nsacr =3D value & (3 << 10); } @@ -1951,7 +1951,7 @@ static void nvic_writel(NVICState *s, uint32_t offset= , uint32_t value, break; } case 0xf34: /* FPCCR */ - if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_simd_r16, cpu)) { /* Not all bits here are banked. */ uint32_t fpccr_s; =20 @@ -2005,13 +2005,13 @@ static void nvic_writel(NVICState *s, uint32_t offs= et, uint32_t value, } break; case 0xf38: /* FPCAR */ - if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_simd_r16, cpu)) { value &=3D ~7; cpu->env.v7m.fpcar[attrs.secure] =3D value; } break; case 0xf3c: /* FPDSCR */ - if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_simd_r16, cpu)) { value &=3D 0x07c00000; cpu->env.v7m.fpdscr[attrs.secure] =3D value; } diff --git a/linux-user/arm/signal.c b/linux-user/arm/signal.c index b0e753801b..2871a7cc21 100644 --- a/linux-user/arm/signal.c +++ b/linux-user/arm/signal.c @@ -346,7 +346,7 @@ static void setup_sigframe_v2(struct target_ucontext_v2= *uc, setup_sigcontext(&uc->tuc_mcontext, env, set->sig[0]); /* Save coprocessor signal frame. */ regspace =3D uc->tuc_regspace; - if (arm_feature(env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_simd_r16, env_archcpu(env))) { regspace =3D setup_sigframe_v2_vfp(regspace, env); } if (arm_feature(env, ARM_FEATURE_IWMMXT)) { @@ -671,7 +671,7 @@ static int do_sigframe_return_v2(CPUARMState *env, =20 /* Restore coprocessor signal frame */ regspace =3D uc->tuc_regspace; - if (arm_feature(env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_simd_r16, env_archcpu(env))) { regspace =3D restore_sigframe_v2_vfp(env, regspace); if (!regspace) { return 1; diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c index 2345dec3c2..a5a4f4e1f8 100644 --- a/target/arm/arch_dump.c +++ b/target/arm/arch_dump.c @@ -363,9 +363,11 @@ int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, = CPUState *cs, int cpuid, void *opaque) { struct arm_note note; - CPUARMState *env =3D &ARM_CPU(cs)->env; + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; DumpState *s =3D opaque; - int ret, i, fpvalid =3D !!arm_feature(env, ARM_FEATURE_VFP); + int ret, i; + bool fpvalid =3D cpu_isar_feature(aa32_simd_r16, cpu); =20 arm_note_init(¬e, s, "CORE", 5, NT_PRSTATUS, sizeof(note.prstatus)); =20 @@ -444,7 +446,6 @@ int cpu_get_dump_info(ArchDumpInfo *info, ssize_t cpu_get_note_size(int class, int machine, int nr_cpus) { ARMCPU *cpu =3D ARM_CPU(first_cpu); - CPUARMState *env =3D &cpu->env; size_t note_size; =20 if (class =3D=3D ELFCLASS64) { @@ -452,12 +453,12 @@ ssize_t cpu_get_note_size(int class, int machine, int= nr_cpus) note_size +=3D AARCH64_PRFPREG_NOTE_SIZE; #ifdef TARGET_AARCH64 if (cpu_isar_feature(aa64_sve, cpu)) { - note_size +=3D AARCH64_SVE_NOTE_SIZE(env); + note_size +=3D AARCH64_SVE_NOTE_SIZE(&cpu->env); } #endif } else { note_size =3D ARM_PRSTATUS_NOTE_SIZE; - if (arm_feature(env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_simd_r16, cpu)) { note_size +=3D ARM_VFP_NOTE_SIZE; } } diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 92006e56c8..8d3eff8cb3 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -293,7 +293,7 @@ static void arm_cpu_reset(CPUState *s) env->v7m.ccr[M_REG_S] |=3D R_V7M_CCR_UNALIGN_TRP_MASK; } =20 - if (arm_feature(env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_simd_r16, cpu)) { env->v7m.fpccr[M_REG_NS] =3D R_V7M_FPCCR_ASPEN_MASK; env->v7m.fpccr[M_REG_S] =3D R_V7M_FPCCR_ASPEN_MASK | R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; @@ -1011,7 +1011,7 @@ static void arm_cpu_dump_state(CPUState *cs, FILE *f,= int flags) int numvfpregs =3D 0; if (cpu_isar_feature(aa32_simd_r32, cpu)) { numvfpregs =3D 32; - } else if (arm_feature(env, ARM_FEATURE_VFP)) { + } else if (cpu_isar_feature(aa32_simd_r16, cpu)) { numvfpregs =3D 16; } for (i =3D 0; i < numvfpregs; i++) { @@ -1260,7 +1260,7 @@ void arm_cpu_post_init(Object *obj) * KVM does not currently allow us to lie to the guest about its * ID/feature registers, so the guest always sees what the host has. */ - if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_simd_r16, cpu)) { cpu->has_vfp =3D true; if (!kvm_enabled()) { qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_propert= y); @@ -1634,7 +1634,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) * We rely on no XScale CPU having VFP so we can use the same bits in = the * TB flags field for VECSTRIDE and XSCALE_CPAR. */ - assert(!(arm_feature(env, ARM_FEATURE_VFP) && + assert(!(cpu_isar_feature(aa32_simd_r16, cpu) && arm_feature(env, ARM_FEATURE_XSCALE))); =20 if (arm_feature(env, ARM_FEATURE_V7) && diff --git a/target/arm/helper.c b/target/arm/helper.c index 0eeedc3c18..3f0b8eee8c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -893,7 +893,7 @@ static void cpacr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP. * TRCDIS [28] is RAZ/WI since we do not implement a trace macroce= ll. */ - if (arm_feature(env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_simd_r16, env_archcpu(env))) { /* VFP coprocessor: cp10 & cp11 [23:20] */ mask |=3D (1 << 31) | (1 << 30) | (0xf << 20); =20 @@ -7757,7 +7757,7 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *c= pu) } else if (cpu_isar_feature(aa32_simd_r32, cpu)) { gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, 35, "arm-vfp3.xml", 0); - } else if (arm_feature(env, ARM_FEATURE_VFP)) { + } else if (cpu_isar_feature(aa32_simd_r16, cpu)) { gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, 19, "arm-vfp.xml", 0); } diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 33d414a684..c024970221 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -738,7 +738,8 @@ static uint32_t v7m_integrity_sig(CPUARMState *env, uin= t32_t lr) */ uint32_t sig =3D 0xfefa125a; =20 - if (!arm_feature(env, ARM_FEATURE_VFP) || (lr & R_V7M_EXCRET_FTYPE_MAS= K)) { + if (!cpu_isar_feature(aa32_simd_r16, env_archcpu(env)) + || (lr & R_V7M_EXCRET_FTYPE_MASK)) { sig |=3D 1; } return sig; @@ -841,7 +842,7 @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t l= r, bool dotailchain, =20 if (dotailchain) { /* Sanitize LR FType and PREFIX bits */ - if (!arm_feature(env, ARM_FEATURE_VFP)) { + if (!cpu_isar_feature(aa32_simd_r16, cpu)) { lr |=3D R_V7M_EXCRET_FTYPE_MASK; } lr =3D deposit32(lr, 24, 8, 0xff); @@ -1373,7 +1374,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) =20 ftype =3D excret & R_V7M_EXCRET_FTYPE_MASK; =20 - if (!arm_feature(env, ARM_FEATURE_VFP) && !ftype) { + if (!ftype && !cpu_isar_feature(aa32_simd_r16, cpu)) { qemu_log_mask(LOG_GUEST_ERROR, "M profile: zero FTYPE in exception= " "exit PC value 0x%" PRIx32 " is UNPREDICTABLE " "if FPU not present\n", @@ -2450,7 +2451,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskr= eg, uint32_t val) * SFPA is RAZ/WI from NS. FPCA is RO if NSACR.CP10 =3D=3D 0, * RES0 if the FPU is not present, and is stored in the S bank */ - if (arm_feature(env, ARM_FEATURE_VFP) && + if (cpu_isar_feature(aa32_simd_r16, env_archcpu(env)) && extract32(env->v7m.nsacr, 10, 1)) { env->v7m.control[M_REG_S] &=3D ~R_V7M_CONTROL_FPCA_MASK; env->v7m.control[M_REG_S] |=3D val & R_V7M_CONTROL_FPCA_MA= SK; @@ -2565,7 +2566,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskr= eg, uint32_t val) env->v7m.control[env->v7m.secure] &=3D ~R_V7M_CONTROL_NPRIV_MA= SK; env->v7m.control[env->v7m.secure] |=3D val & R_V7M_CONTROL_NPR= IV_MASK; } - if (arm_feature(env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_simd_r16, env_archcpu(env))) { /* * SFPA is RAZ/WI from NS or if no FPU. * FPCA is RO if NSACR.CP10 =3D=3D 0, RES0 if the FPU is not p= resent. diff --git a/target/arm/machine.c b/target/arm/machine.c index 241890ac8c..7050bde459 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -9,9 +9,8 @@ static bool vfp_needed(void *opaque) { ARMCPU *cpu =3D opaque; - CPUARMState *env =3D &cpu->env; =20 - return arm_feature(env, ARM_FEATURE_VFP); + return cpu_isar_feature(aa32_simd_r16, cpu); } =20 static int get_fpscr(QEMUFile *f, void *opaque, size_t size, --=20 2.20.1 From nobody Fri Mar 29 00:38:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581704530421167.87179507685778; Fri, 14 Feb 2020 10:22:10 -0800 (PST) Received: from localhost ([::1]:43676 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2fbN-0008Lh-6B for importer@patchew.org; Fri, 14 Feb 2020 13:22:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60832) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2fVP-0004LD-1L for qemu-devel@nongnu.org; Fri, 14 Feb 2020 13:16:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j2fVN-00006I-GB for qemu-devel@nongnu.org; Fri, 14 Feb 2020 13:15:58 -0500 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:44087) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j2fVN-00005y-9p for qemu-devel@nongnu.org; Fri, 14 Feb 2020 13:15:57 -0500 Received: by mail-pg1-x543.google.com with SMTP id g3so5208354pgs.11 for ; Fri, 14 Feb 2020 10:15:57 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id i3sm7525123pfg.94.2020.02.14.10.15.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Feb 2020 10:15:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bLNTrgdvvZF7PnSY+r2yk4nJu3Fd25nqdhwKgVxP4y8=; b=GYKE089kTv91kmETyK0jyL74T8rE1zGRPjFKDuqFK8x9NzrPETSanVvoPuwszh31Qd DYH0f2BzDma5lvrDsxbW/qo5QHMoq98SXd5BE9hxCz4QhG2s3RmsySrQ/A6639kLyqkV wOXnN/9z77VRB4xks2cayOhzcySgt3hSD5KpYkPDS/HX+ABuC3emLNWzwauHFs+wLB5h D0t0aN59cZBO6Yj+ze09kLd37i8dmkxaDJQ0zLxiEPANyeJIBQTs+1R3/xPnYesUo3mi tQgT0nVXebtfJfw8NwTT+w9+vX5OcmI5rjB0/ZRbPCyAyeujbEujodmrVU8dkWkx2HW3 HPZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bLNTrgdvvZF7PnSY+r2yk4nJu3Fd25nqdhwKgVxP4y8=; b=fWt4oPGEqkJgZg3aXYfoE5+cvUp2JNBMQX9bhjw7MOsX8OhV6jD7MuCGbBku1G+YGL 3zY7FDdMEy/SNNPfsrxUKfb4kzYFhrIipHFtvwmgot2Ev3XxnCJWaeMShKaQyipVXpKo xaY3Muy7sYF0P9NvmyamP2sFWp5FPM+FwHngmDk0luYb6VzvE432n+Lq5E38GdgMEr9U M5/gTLCNwe+rAAIW/AS/Q4tBfy0SJ9tlBWzja2Gj+m5nrZW+uPqZjHXM4d4t7sNm/VQc /2O/T+ZR/cv57+oULeN4iJLmjlnSVzrcby6l36TH3UnbOGqXen/X3VHynGLJdjIvfVSS NVoA== X-Gm-Message-State: APjAAAVVZSU9DZd3ysyAcu6yPTK5X89TSl14wK/VZif8CazBjK6aeM6Z I9PS46mqWSQoSYO67xWoLiq0s6+CNWc= X-Google-Smtp-Source: APXvYqw3x3UjxGmwNCl2/4Gd92AQHYyZfRgVgmNMG3ZtoeYuSY9UgLMiw4vhyTvhDpRzmWxQmstvhw== X-Received: by 2002:a63:9257:: with SMTP id s23mr5037458pgn.0.1581704155908; Fri, 14 Feb 2020 10:15:55 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 06/19] target/arm: Rename isar_feature_aa32_fpdp_v2 Date: Fri, 14 Feb 2020 10:15:34 -0800 Message-Id: <20200214181547.21408-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200214181547.21408-1-richard.henderson@linaro.org> References: <20200214181547.21408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The old name, isar_feature_aa32_fpdp, does not reflect that the test includes VFPv2. We will introduce another feature tests for VFPv3. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpu.h | 4 ++-- target/arm/translate-vfp.inc.c | 40 +++++++++++++++++----------------- 2 files changed, 22 insertions(+), 22 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 85b90eaed2..5f08cbd2d8 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3429,9 +3429,9 @@ static inline bool isar_feature_aa32_fpshvec(const AR= MISARegisters *id) return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0; } =20 -static inline bool isar_feature_aa32_fpdp(const ARMISARegisters *id) +static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id) { - /* Return true if CPU supports double precision floating point */ + /* Return true if CPU supports double precision floating point, VFPv2 = */ return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0; } =20 diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 96a1d727c6..5290828d0d 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -206,7 +206,7 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) return false; } =20 - if (dp && !dc_isar_feature(aa32_fpdp, s)) { + if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -339,7 +339,7 @@ static bool trans_VMINMAXNM(DisasContext *s, arg_VMINMA= XNM *a) return false; } =20 - if (dp && !dc_isar_feature(aa32_fpdp, s)) { + if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -425,7 +425,7 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a) return false; } =20 - if (dp && !dc_isar_feature(aa32_fpdp, s)) { + if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -488,7 +488,7 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) return false; } =20 - if (dp && !dc_isar_feature(aa32_fpdp, s)) { + if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -1313,7 +1313,7 @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpD= PFn *fn, return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -1462,7 +1462,7 @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpD= PFn *fn, int vd, int vm) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -1826,7 +1826,7 @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp = *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -1925,7 +1925,7 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VM= OV_imm_dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2069,7 +2069,7 @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_d= p *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2142,7 +2142,7 @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_V= CVT_f64_f16 *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2208,7 +2208,7 @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_V= CVT_f16_f64 *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2268,7 +2268,7 @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRIN= TR_dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2329,7 +2329,7 @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRIN= TZ_dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2388,7 +2388,7 @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRIN= TX_dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2416,7 +2416,7 @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_s= p *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2444,7 +2444,7 @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_d= p *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2498,7 +2498,7 @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_VC= VT_int_dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2538,7 +2538,7 @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2631,7 +2631,7 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VC= VT_fix_dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2727,7 +2727,7 @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VC= VT_dp_int *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 --=20 2.20.1 From nobody Fri Mar 29 00:38:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id i3sm7525123pfg.94.2020.02.14.10.15.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Feb 2020 10:15:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bFodYZjZFzCVB6GfD5JV/0vM0v0zus5xTQluYRgEuVA=; b=mn3JnS8Jvr4MDWK75x/kpAf+V1CcrWOmtB8fH9hTWJDDutpUIdanPEueHvcfjp8xWC UDtDMGKyC3jkuHnsuJKxYdK6yBkhQzwwrL4ABIqP4I65X0vOjoeLVg/mWF5gllcQQl+3 rIl2Re3huWwrV5d3Wpi0q2FeRWX/IVMAsk0NS1ViyETsYI1isb8D94TlexzfNK6xLP6S mfcMwIOMO+Bye+yvxxPm0mb1jbtfzlLU2EoTg8jqxPw2RpzfLZlZEqVctCgw8vugy4ee F/FczYcXN5yy4OUKkCZsyaDxmc9D9QqqpZRt44/CPrVix0Lekh3LRwBUmuFJ2FLIDBiY PteQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bFodYZjZFzCVB6GfD5JV/0vM0v0zus5xTQluYRgEuVA=; b=RgsOpeTxZ7qODK/3u4EdtrO/Ru8MuZZkR00O634QgugcoLqqK01sXzk7dGDzKz82o4 hvdQHdGwYxbhZSRyFsHL0A8wgJKcl9tN5ZKkK8/DNG0fUKt9UFWC0qnDnuWRWG8cEDTZ aKVQbOUQ6XGY1RwMuD7BfOdQ62ahJbdRqc2vG3Z3vsumeDXSQkDwUfQffWNGTgGAK701 QGqXzRhonnmwh0u2roQnz/6aqD8Lc8l/V9bEmR2OHIzvEBRv1vskD0Tvj/+vSqy2hZQw Y595+qsp1ylw4Pq4lk4oK0F8Zf7wfd1RFmjkx9g4WodSmX06Rk+SHhv8fkRk/bakwe2k aWbQ== X-Gm-Message-State: APjAAAVM1K/xoFlZ1jJoW1HrtrU1P98RV++2nMhs2zCf+Gig3wiBdoMq QrVCPpqQN3ihLvjWELulsIxKoBDtYTI= X-Google-Smtp-Source: APXvYqwJbdQcs2Grf6oVy4T2qW9FmJj6kuzceV5HdALmuzVrfJ5m4L6O9wUUKecZu0cegUijVE2tzQ== X-Received: by 2002:a63:4525:: with SMTP id s37mr4756791pga.418.1581704157012; Fri, 14 Feb 2020 10:15:57 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 07/19] target/arm: Add isar_feature_aa32_{fpsp_v2, fpsp_v3, fpdp_v3} Date: Fri, 14 Feb 2020 10:15:35 -0800 Message-Id: <20200214181547.21408-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200214181547.21408-1-richard.henderson@linaro.org> References: <20200214181547.21408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" We will shortly use these to test for VFPv2 and VFPv3 in different situations. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 5f08cbd2d8..4ff28418df 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3429,12 +3429,30 @@ static inline bool isar_feature_aa32_fpshvec(const = ARMISARegisters *id) return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0; } =20 +static inline bool isar_feature_aa32_fpsp_v2(const ARMISARegisters *id) +{ + /* Return true if CPU supports single precision floating point, VFPv2 = */ + return FIELD_EX32(id->mvfr0, MVFR0, FPSP) > 0; +} + +static inline bool isar_feature_aa32_fpsp_v3(const ARMISARegisters *id) +{ + /* Return true if CPU supports single precision floating point, VFPv3 = */ + return FIELD_EX32(id->mvfr0, MVFR0, FPSP) >=3D 2; +} + static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id) { /* Return true if CPU supports double precision floating point, VFPv2 = */ return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0; } =20 +static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id) +{ + /* Return true if CPU supports double precision floating point, VFPv3 = */ + return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >=3D 2; +} + /* * We always set the FP and SIMD FP16 fields to indicate identical * levels of support (assuming SIMD is implemented at all), so --=20 2.20.1 From nobody Fri Mar 29 00:38:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 158170444856768.89057544115246; Fri, 14 Feb 2020 10:20:48 -0800 (PST) Received: from localhost ([::1]:43628 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2fa3-0004rT-97 for importer@patchew.org; Fri, 14 Feb 2020 13:20:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60866) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2fVS-0004Nu-2r for qemu-devel@nongnu.org; Fri, 14 Feb 2020 13:16:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j2fVQ-0000Cx-4b for qemu-devel@nongnu.org; Fri, 14 Feb 2020 13:16:01 -0500 Received: from mail-pf1-x441.google.com ([2607:f8b0:4864:20::441]:35527) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j2fVP-00009V-Sa for qemu-devel@nongnu.org; Fri, 14 Feb 2020 13:16:00 -0500 Received: by mail-pf1-x441.google.com with SMTP id y73so5269407pfg.2 for ; Fri, 14 Feb 2020 10:15:59 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id i3sm7525123pfg.94.2020.02.14.10.15.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Feb 2020 10:15:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MPCJ7dRq2fpTnBkIuHG7jADk+0h3hLWHD3XSDLeSg9g=; b=UI6JmzRnpNrL7G0Cvnr4KMvYPBy9+Wy+5LG6IQOz9Yxa8YAmXA7C7YYVFDx0Uy4/W6 YAX1WRpxfid8LtBratA385xm2d/in01gRJxsQRznOBhuUAPVs6sDMk5xxSkWgQWtxujS MsLBTKdCIx80dlURaYh5Oew7gQU2FMJPwRyLBoxexKOzLsFAeKiOIajMsA651WCfuyTz HbE+rlmfulxXmrjI6pmKiTlYzQfIyTA3aGLsaim6QYApiSvAo7AkBYIklQCRF7zVAr7H xGMLB3m6wY81mCMQ+AXxg3T1vGwiisHVR0GVpdE1lfPR1vZ72alTLfo1c12Fypxkp3rx Arjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MPCJ7dRq2fpTnBkIuHG7jADk+0h3hLWHD3XSDLeSg9g=; b=S3XafJrtvIz5mHfgg+szSPNj693zuIw/G8h4tQXr9+8k+yZo0zExjrorzZrqq84b2s BZYmBnnFUTl26iUESkC2sfN8yJSJKGZJSgOxlTAYmNiV1o8XWIGXrdCcYsZO2LCARfJ5 FWCMyI2BVkTU/aioWGI0WqSJNGwPLHVDSgvbfi3ZuiwliYMo2hkkNH90ZRN20/PbbIqd BQmBC2MXUMz4XOJdf/SBXF3zuppuLzIDFUeqSQZOJSRfrl6oVGnBEWCgTd/CdWXDIlXi g2qm31WlIXx0Lks85WMev+9RjMlUQ9xHSqOhuEc+tzvCvfHf+Wq+3kHNUjLvA6r/heVK 7cZQ== X-Gm-Message-State: APjAAAVF7RgheAsDzMfdurMkNBTS8rwR7zd71iyTaBImHwpGg+4tyOcv oUWRzIOS3rbvhHXWOC4wYnMiM04U/Ck= X-Google-Smtp-Source: APXvYqxVUK0ku6IaYqJXcjT0RjyFCO9IODq6R8MjqxDaG1pnF0oadPvBU1/qgcc/OeGEawCqAOEWmQ== X-Received: by 2002:a63:451b:: with SMTP id s27mr4713938pga.233.1581704158059; Fri, 14 Feb 2020 10:15:58 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 08/19] target/arm: Perform fpdp_v2 check first Date: Fri, 14 Feb 2020 10:15:36 -0800 Message-Id: <20200214181547.21408-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200214181547.21408-1-richard.henderson@linaro.org> References: <20200214181547.21408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Shuffle the order of the checks so that we test the ISA before we test anything else, such as the register arguments. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate-vfp.inc.c | 143 +++++++++++++++++---------------- 1 file changed, 72 insertions(+), 71 deletions(-) diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 5290828d0d..0c55140127 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -200,13 +200,13 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) return false; } =20 - /* UNDEF accesses to D16-D31 if they don't exist */ - if (dp && !dc_isar_feature(aa32_simd_r32, s) && - ((a->vm | a->vn | a->vd) & 0x10)) { + if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 - if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist */ + if (dp && !dc_isar_feature(aa32_simd_r32, s) && + ((a->vm | a->vn | a->vd) & 0x10)) { return false; } =20 @@ -333,13 +333,13 @@ static bool trans_VMINMAXNM(DisasContext *s, arg_VMIN= MAXNM *a) return false; } =20 - /* UNDEF accesses to D16-D31 if they don't exist */ - if (dp && !dc_isar_feature(aa32_simd_r32, s) && - ((a->vm | a->vn | a->vd) & 0x10)) { + if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 - if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist */ + if (dp && !dc_isar_feature(aa32_simd_r32, s) && + ((a->vm | a->vn | a->vd) & 0x10)) { return false; } =20 @@ -419,13 +419,13 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a) return false; } =20 - /* UNDEF accesses to D16-D31 if they don't exist */ - if (dp && !dc_isar_feature(aa32_simd_r32, s) && - ((a->vm | a->vd) & 0x10)) { + if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 - if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist */ + if (dp && !dc_isar_feature(aa32_simd_r32, s) && + ((a->vm | a->vd) & 0x10)) { return false; } =20 @@ -483,12 +483,12 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) return false; } =20 - /* UNDEF accesses to D16-D31 if they don't exist */ - if (dp && !dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { + if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 - if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist */ + if (dp && !dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { return false; } =20 @@ -1308,12 +1308,12 @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3O= pDPFn *fn, TCGv_i64 f0, f1, fd; TCGv_ptr fpst; =20 - /* UNDEF accesses to D16-D31 if they don't exist */ - if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vn | vm) & 0x10)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist */ + if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vn | vm) & 0x10)) { return false; } =20 @@ -1457,12 +1457,12 @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2O= pDPFn *fn, int vd, int vm) int veclen =3D s->vec_len; TCGv_i64 f0, fd; =20 - /* UNDEF accesses to D16-D31 if they don't exist */ - if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vm) & 0x10)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist */ + if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vm) & 0x10)) { return false; } =20 @@ -1821,12 +1821,13 @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_d= p *a) return false; } =20 - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && ((a->vd | a->vn | a->vm) & 0= x10)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vn | a->vm) & 0x10)) { return false; } =20 @@ -1920,12 +1921,12 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_= VMOV_imm_dp *a) =20 vd =3D a->vd; =20 - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && (vd & 0x10)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && (vd & 0x10)) { return false; } =20 @@ -2059,6 +2060,10 @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_= dp *a) { TCGv_i64 vd, vm; =20 + if (!dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + /* Vm/M bits must be zero for the Z variant */ if (a->z && a->vm !=3D 0) { return false; @@ -2069,10 +2074,6 @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_= dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - if (!vfp_access_check(s)) { return true; } @@ -2133,6 +2134,10 @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_= VCVT_f64_f16 *a) TCGv_i32 tmp; TCGv_i64 vd; =20 + if (!dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + if (!dc_isar_feature(aa32_fp16_dpconv, s)) { return false; } @@ -2142,10 +2147,6 @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_= VCVT_f64_f16 *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - if (!vfp_access_check(s)) { return true; } @@ -2199,6 +2200,10 @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_= VCVT_f16_f64 *a) TCGv_i32 tmp; TCGv_i64 vm; =20 + if (!dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + if (!dc_isar_feature(aa32_fp16_dpconv, s)) { return false; } @@ -2208,10 +2213,6 @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_= VCVT_f16_f64 *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - if (!vfp_access_check(s)) { return true; } @@ -2259,6 +2260,10 @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRI= NTR_dp *a) TCGv_ptr fpst; TCGv_i64 tmp; =20 + if (!dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + if (!dc_isar_feature(aa32_vrint, s)) { return false; } @@ -2268,10 +2273,6 @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRI= NTR_dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - if (!vfp_access_check(s)) { return true; } @@ -2320,6 +2321,10 @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRI= NTZ_dp *a) TCGv_i64 tmp; TCGv_i32 tcg_rmode; =20 + if (!dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + if (!dc_isar_feature(aa32_vrint, s)) { return false; } @@ -2329,10 +2334,6 @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRI= NTZ_dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - if (!vfp_access_check(s)) { return true; } @@ -2379,6 +2380,10 @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRI= NTX_dp *a) TCGv_ptr fpst; TCGv_i64 tmp; =20 + if (!dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + if (!dc_isar_feature(aa32_vrint, s)) { return false; } @@ -2388,10 +2393,6 @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRI= NTX_dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - if (!vfp_access_check(s)) { return true; } @@ -2411,12 +2412,12 @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT= _sp *a) TCGv_i64 vd; TCGv_i32 vm; =20 - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { return false; } =20 @@ -2439,12 +2440,12 @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT= _dp *a) TCGv_i64 vm; TCGv_i32 vd; =20 - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { return false; } =20 @@ -2493,12 +2494,12 @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_= VCVT_int_dp *a) TCGv_i64 vd; TCGv_ptr fpst; =20 - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { return false; } =20 @@ -2529,6 +2530,10 @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *= a) TCGv_i32 vd; TCGv_i64 vm; =20 + if (!dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + if (!dc_isar_feature(aa32_jscvt, s)) { return false; } @@ -2538,10 +2543,6 @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *= a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - if (!vfp_access_check(s)) { return true; } @@ -2622,6 +2623,10 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_V= CVT_fix_dp *a) TCGv_ptr fpst; int frac_bits; =20 + if (!dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) { return false; } @@ -2631,10 +2636,6 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_V= CVT_fix_dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - if (!vfp_access_check(s)) { return true; } @@ -2722,12 +2723,12 @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_= VCVT_dp_int *a) TCGv_i64 vm; TCGv_ptr fpst; =20 - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { return false; } =20 --=20 2.20.1 From nobody Fri Mar 29 00:38:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581704675612250.75421452075523; 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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id i3sm7525123pfg.94.2020.02.14.10.15.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Feb 2020 10:15:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pElnR5+ZNReOFV25D5Wd4OZyDSMZOeR76smz6O5bwn4=; b=hjUdmAd37aNlIq8IPlsbcSfAKHSjpi6isiDOKLK17Crix6/2Ymba1cQmYhnge/Av9z WQmvvodmneZ9sDBJo/ItH1l55Zg63Ygi0+aR+eMbROTckEjyrWpFgNKdMJIGLQn9tMez IrU7qvvsbODT/yzg4IwAVlcy2NQDaLZuA8FDOGhcZeZqkK6uqRTrgjE+7MNAodMAzUw2 ZGI8HiYrrMVoVr5jW+/IKGGml4jA7vlmGuLfGs1jZFtgXen0dibBseQpFqEtx36IE2Ls mq/7ueBm4EK1aDCvaXfde3W9bsXd++1055DVx9I/B5RKfo58VP1nEVS3D5J0UfZuefVZ P5Zg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pElnR5+ZNReOFV25D5Wd4OZyDSMZOeR76smz6O5bwn4=; b=G0HWUj22hzV3Altaznz3kdLgwYrJu0hzNjy0pRjXzlR4iiu8lyXjMTF11RQ5sxJYL3 9gAuFcrR26mt7Xj8mnwC8+Iaku5ddqfQdKJT8YDGlbp8W5s3TwMztNX1NXiqOAkarF2I OTsqWKu0IKn19upbYeOBeQ3iH9JZV6mpmCs0MR59rTs6lPMfClp6PvfW46sZlUOHLSQY 6Uac0OcxbH8B49uGVQbq5J7GUiwYEc1GKTLIY9uDnBsEEokTMTvz0JMFlUwrf9AbdOdj /tZi7gF6LUoSzSQ+pTXuAn/3cYwFyjKtjh7iol22NZTEsYWnFm9DeFtq/IJknAl0U0vb FV6g== X-Gm-Message-State: APjAAAWfFbMJ4MbwbGHEXtKD7oHyFRxn5hnw3wayHAaiTqadzSqIAmKm NSlhkoRIqDnPgq4B2x/XRfWEfAfyNT0= X-Google-Smtp-Source: APXvYqzm2G8FnQhPwmYjcskc/H6ubcvwbrWQs1mqkJBkFgAnUANH4keHnBjW+ta9ohlLynRmkTRWLw== X-Received: by 2002:a17:902:7b92:: with SMTP id w18mr4534765pll.72.1581704159122; Fri, 14 Feb 2020 10:15:59 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 09/19] target/arm: Replace ARM_FEATURE_VFP3 checks with fp{sp, dp}_v3 Date: Fri, 14 Feb 2020 10:15:37 -0800 Message-Id: <20200214181547.21408-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200214181547.21408-1-richard.henderson@linaro.org> References: <20200214181547.21408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Sort this check to the start of a trans_* function. Merge this with any existing test for fpdp_v2. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate-vfp.inc.c | 24 ++++++++---------------- 1 file changed, 8 insertions(+), 16 deletions(-) diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 0c55140127..9e5516f208 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -717,7 +717,7 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_V= MRS *a) * VFPv2 allows access to FPSID from userspace; VFPv3 restricts * all ID registers to privileged access only. */ - if (IS_USER(s) && arm_dc_feature(s, ARM_FEATURE_VFP3)) { + if (IS_USER(s) && dc_isar_feature(aa32_fpsp_v3, s)) { return false; } ignore_vfp_enabled =3D true; @@ -746,7 +746,7 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_V= MRS *a) case ARM_VFP_FPINST: case ARM_VFP_FPINST2: /* Not present in VFPv3 */ - if (IS_USER(s) || arm_dc_feature(s, ARM_FEATURE_VFP3)) { + if (IS_USER(s) || dc_isar_feature(aa32_fpsp_v3, s)) { return false; } break; @@ -1871,12 +1871,12 @@ static bool trans_VMOV_imm_sp(DisasContext *s, arg_= VMOV_imm_sp *a) =20 vd =3D a->vd; =20 - if (!dc_isar_feature(aa32_fpshvec, s) && - (veclen !=3D 0 || s->vec_stride !=3D 0)) { + if (!dc_isar_feature(aa32_fpsp_v3, s)) { return false; } =20 - if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) { + if (!dc_isar_feature(aa32_fpshvec, s) && + (veclen !=3D 0 || s->vec_stride !=3D 0)) { return false; } =20 @@ -1921,7 +1921,7 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VM= OV_imm_dp *a) =20 vd =3D a->vd; =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { + if (!dc_isar_feature(aa32_fpdp_v3, s)) { return false; } =20 @@ -1935,10 +1935,6 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_V= MOV_imm_dp *a) return false; } =20 - if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) { - return false; - } - if (!vfp_access_check(s)) { return true; } @@ -2563,7 +2559,7 @@ static bool trans_VCVT_fix_sp(DisasContext *s, arg_VC= VT_fix_sp *a) TCGv_ptr fpst; int frac_bits; =20 - if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) { + if (!dc_isar_feature(aa32_fpsp_v3, s)) { return false; } =20 @@ -2623,11 +2619,7 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_V= CVT_fix_dp *a) TCGv_ptr fpst; int frac_bits; =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - - if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) { + if (!dc_isar_feature(aa32_fpdp_v3, s)) { return false; } =20 --=20 2.20.1 From nobody Fri Mar 29 00:38:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581704745258770.8542724012653; Fri, 14 Feb 2020 10:25:45 -0800 (PST) Received: from localhost ([::1]:43776 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2feq-0006G9-1k for importer@patchew.org; Fri, 14 Feb 2020 13:25:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60884) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2fVU-0004RT-Eo for qemu-devel@nongnu.org; Fri, 14 Feb 2020 13:16:05 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j2fVS-0000Eo-1A for qemu-devel@nongnu.org; Fri, 14 Feb 2020 13:16:04 -0500 Received: from mail-pj1-x1043.google.com ([2607:f8b0:4864:20::1043]:55927) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j2fVR-0000EW-Pc for qemu-devel@nongnu.org; Fri, 14 Feb 2020 13:16:01 -0500 Received: by mail-pj1-x1043.google.com with SMTP id d5so4191272pjz.5 for ; Fri, 14 Feb 2020 10:16:01 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id i3sm7525123pfg.94.2020.02.14.10.15.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Feb 2020 10:15:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jaAC4b+WQDjTB8KwLDIOWST2Ik8xCOfklX+0EF0qKFI=; b=iYdkLkx91FTUw8c8aBjrmN1KPeXf/SG3+sU1Yc9XDgtYaNpxxaimOW3oXl0srjnFaS yO6s7pv4yulfxaEMidlD+sGi1+IDu7sxa3ipRq2LWe5sNxJQ5egSnP/qG/vQKfgchhLX f8E5m+APpOS3UzDT5hpdCakIQHO2iRP3qwsE3gIVK82+wXRpJzSQ6BieWbj0e8SBrlJy KHIbK2/+oErmPRQXYfJLpH7Z53yvmRNgr3Fl/dPVBPQkwA93WYqSFNgjjwLkiraLceUw UCp2N/QBGAPNZaGCIcMDwnWMsBu1FFEvkwOlODZHE86mIgIJodckAt7rybURduIKcfuv mN8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jaAC4b+WQDjTB8KwLDIOWST2Ik8xCOfklX+0EF0qKFI=; b=dzVGicuCzXw9SQcOaDo4nq/h2PYNpBZ3xVpyXS4DPaOwr2XJh0vuhsfRR4zZWF0zG9 p28yRCiKXck5Q/u9EeeiyEHkVrVQMD5w1h3VuHtRaDu8qX83UOmB+CDnI9HnJ9H4u4MK fDSfUeewqINWKyaKg2O6oT3AteNAZO2pEGd+QFg2kHT2ecX+s6rCkTLVYCqdNpWPzl8Z tAKq2enJEiWN0p7x96p1aGZJL8B4lJkLKKPhfiNeqgLsJAC9M7sPXCmUAoEBtJ+hZyro 9HrVIGyubq0I2Th2kKLS5sQwfeMzrwea1ggR6Yl3ldLSy+ElflnY2ZHQq9SsjBxFmXjK mdHA== X-Gm-Message-State: APjAAAVbNEDJFuQnGi91sonwgGLtU7uiUE8X+vZREQMVVL9y09hpoBRE /PUHBxolkKZlvFRrnsDOC/9Ushu8p7E= X-Google-Smtp-Source: APXvYqyri7x81oPnuh6GV+wpNbaTh1DaWzdLLZQ/djrKMOXXFFFRlJlFlPCR3j+jQC6ojRRqe4NDfg== X-Received: by 2002:a17:90a:628c:: with SMTP id d12mr5123055pjj.59.1581704160272; Fri, 14 Feb 2020 10:16:00 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 10/19] target/arm: Add missing checks for fpsp_v2 Date: Fri, 14 Feb 2020 10:15:38 -0800 Message-Id: <20200214181547.21408-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200214181547.21408-1-richard.henderson@linaro.org> References: <20200214181547.21408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1043 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" We will eventually remove the early ARM_FEATURE_VFP test, so add a proper test for each trans_* that does not already have another ISA test. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate-vfp.inc.c | 78 ++++++++++++++++++++++++++++++---- 1 file changed, 69 insertions(+), 9 deletions(-) diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 9e5516f208..8913320259 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -555,6 +555,13 @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV= _to_gp *a) int pass; uint32_t offset; =20 + /* SIZE =3D=3D 2 is a VFP instruction; otherwise NEON. */ + if (a->size =3D=3D 2 + ? !dc_isar_feature(aa32_fpsp_v2, s) + : !arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + /* UNDEF accesses to D16-D31 if they don't exist */ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) { return false; @@ -564,10 +571,6 @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV= _to_gp *a) pass =3D extract32(offset, 2, 1); offset =3D extract32(offset, 0, 2) * 8; =20 - if (a->size !=3D 2 && !arm_dc_feature(s, ARM_FEATURE_NEON)) { - return false; - } - if (!vfp_access_check(s)) { return true; } @@ -614,6 +617,13 @@ static bool trans_VMOV_from_gp(DisasContext *s, arg_VM= OV_from_gp *a) int pass; uint32_t offset; =20 + /* SIZE =3D=3D 2 is a VFP instruction; otherwise NEON. */ + if (a->size =3D=3D 2 + ? !dc_isar_feature(aa32_fpsp_v2, s) + : !arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + /* UNDEF accesses to D16-D31 if they don't exist */ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) { return false; @@ -623,10 +633,6 @@ static bool trans_VMOV_from_gp(DisasContext *s, arg_VM= OV_from_gp *a) pass =3D extract32(offset, 2, 1); offset =3D extract32(offset, 0, 2) * 8; =20 - if (a->size !=3D 2 && !arm_dc_feature(s, ARM_FEATURE_NEON)) { - return false; - } - if (!vfp_access_check(s)) { return true; } @@ -700,6 +706,10 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_= VMRS *a) TCGv_i32 tmp; bool ignore_vfp_enabled =3D false; =20 + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + if (arm_dc_feature(s, ARM_FEATURE_M)) { /* * The only M-profile VFP vmrs/vmsr sysreg is FPSCR. @@ -844,6 +854,10 @@ static bool trans_VMOV_single(DisasContext *s, arg_VMO= V_single *a) { TCGv_i32 tmp; =20 + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + if (!vfp_access_check(s)) { return true; } @@ -873,6 +887,10 @@ static bool trans_VMOV_64_sp(DisasContext *s, arg_VMOV= _64_sp *a) { TCGv_i32 tmp; =20 + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + /* * VMOV between two general-purpose registers and two single precision * floating point registers @@ -908,8 +926,12 @@ static bool trans_VMOV_64_dp(DisasContext *s, arg_VMOV= _64_dp *a) =20 /* * VMOV between two general-purpose registers and one double precision - * floating point register + * floating point register. Note that this does not require support + * for double precision arithmetic. */ + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } =20 /* UNDEF accesses to D16-D31 if they don't exist */ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { @@ -946,6 +968,10 @@ static bool trans_VLDR_VSTR_sp(DisasContext *s, arg_VL= DR_VSTR_sp *a) uint32_t offset; TCGv_i32 addr, tmp; =20 + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + if (!vfp_access_check(s)) { return true; } @@ -977,6 +1003,11 @@ static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_V= LDR_VSTR_dp *a) TCGv_i32 addr; TCGv_i64 tmp; =20 + /* Note that this does not require support for double arithmetic. */ + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + /* UNDEF accesses to D16-D31 if they don't exist */ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { return false; @@ -1013,6 +1044,10 @@ static bool trans_VLDM_VSTM_sp(DisasContext *s, arg_= VLDM_VSTM_sp *a) TCGv_i32 addr, tmp; int i, n; =20 + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + n =3D a->imm; =20 if (n =3D=3D 0 || (a->vd + n) > 32) { @@ -1086,6 +1121,11 @@ static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_= VLDM_VSTM_dp *a) TCGv_i64 tmp; int i, n; =20 + /* Note that this does not require support for double arithmetic. */ + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + n =3D a->imm >> 1; =20 if (n =3D=3D 0 || (a->vd + n) > 32 || n > 16) { @@ -1234,6 +1274,10 @@ static bool do_vfp_3op_sp(DisasContext *s, VFPGen3Op= SPFn *fn, TCGv_i32 f0, f1, fd; TCGv_ptr fpst; =20 + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + if (!dc_isar_feature(aa32_fpshvec, s) && (veclen !=3D 0 || s->vec_stride !=3D 0)) { return false; @@ -1388,6 +1432,10 @@ static bool do_vfp_2op_sp(DisasContext *s, VFPGen2Op= SPFn *fn, int vd, int vm) int veclen =3D s->vec_len; TCGv_i32 f0, fd; =20 + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + if (!dc_isar_feature(aa32_fpshvec, s) && (veclen !=3D 0 || s->vec_stride !=3D 0)) { return false; @@ -2021,6 +2069,10 @@ static bool trans_VCMP_sp(DisasContext *s, arg_VCMP_= sp *a) { TCGv_i32 vd, vm; =20 + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + /* Vm/M bits must be zero for the Z variant */ if (a->z && a->vm !=3D 0) { return false; @@ -2464,6 +2516,10 @@ static bool trans_VCVT_int_sp(DisasContext *s, arg_V= CVT_int_sp *a) TCGv_i32 vm; TCGv_ptr fpst; =20 + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + if (!vfp_access_check(s)) { return true; } @@ -2682,6 +2738,10 @@ static bool trans_VCVT_sp_int(DisasContext *s, arg_V= CVT_sp_int *a) TCGv_i32 vm; TCGv_ptr fpst; =20 + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + if (!vfp_access_check(s)) { return true; } --=20 2.20.1 From nobody Fri Mar 29 00:38:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581704365937481.71984930489555; Fri, 14 Feb 2020 10:19:25 -0800 (PST) Received: from localhost ([::1]:43558 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2fYi-0001bc-IK for importer@patchew.org; Fri, 14 Feb 2020 13:19:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60909) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2fVW-0004Um-2d for qemu-devel@nongnu.org; Fri, 14 Feb 2020 13:16:07 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j2fVV-0000Fx-03 for qemu-devel@nongnu.org; Fri, 14 Feb 2020 13:16:05 -0500 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]:33990) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j2fVU-0000F8-Q7 for qemu-devel@nongnu.org; Fri, 14 Feb 2020 13:16:04 -0500 Received: by mail-pl1-x62c.google.com with SMTP id j7so4026785plt.1 for ; Fri, 14 Feb 2020 10:16:04 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id i3sm7525123pfg.94.2020.02.14.10.16.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Feb 2020 10:16:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=a/LcTtPEaSKt2TqD4S4P5QmkhybGw6G87ufOx2pyeQw=; b=c61cqr0ruFzGdXgVtkN+YNg//bdC9gjAflB/RTCR+hibxY6RdyOLFzZxon4u+hZ8C4 r4B3GUR2u/8Q8sD98MpGvpSbBFNCvrd+j5uRXOJBKXBTAblu8bALN3mfmTWof1kYQzsv N14y+wrNtk3HE6x41aUIwxr7+llq4sU7UHqnKUFFS4TaV6nHAG4gOIt4J+XJiRrM/xg0 81DHM+qp0ujOaFXhAKQWymt5b6+/kzNndYYYYC7iayt1zOVtq8CfhY07ocvvdzNKDrDG DAuqpuRD8mzqRSDJdf3pKUTnEQ9lJNp5CyaGuh43K6L+H/pysgLZ5l3fgElXeMlHZa/I a1lA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=a/LcTtPEaSKt2TqD4S4P5QmkhybGw6G87ufOx2pyeQw=; b=mGCWy+LfcC/6mvSZlUb3HxDOx9VL3zIzBjphzfIZ/3J5f70eLwbmZiaQiG5HyF50ng 8wrPCMG58qJiLe15z67ktiIDGjiBjNrmiHWcoZa32uJNeQaEhmWopzJ9ZTjrnWotX5mo Maahv2BF5jW09sxMuRZfDmTm9NoGyvOR/fHcD3WvwSWP8rWzvOm9hj5kfMoQrCx2TCc4 d/53DrrqZB4IPbpUQmnzRXhSYjNURKmH3osH/L+/F3HqUq+UHdWqgW43fZF/Rs4Dcsuc BFAAcoQLtn06jxAjubdxEIpesxX5q/z5jK0QIX4OceNd/Un06d/8xJ0We/2tzP1NU+f1 1zmA== X-Gm-Message-State: APjAAAXG7bU+4BZ/ML7vOoI4QAsrK/aoIFB2BEEtSPnjyvY1XfnZY95m oJSFGdoSmKFwFDIEYMQlMM/2FMYg4wY= X-Google-Smtp-Source: APXvYqx7iArNF4CsabU32pLpZRdIpRtFQwaoHAgWfiXUaKpOnwPwX8CQCPnLgOLjrCI3bvImxamWow== X-Received: by 2002:a17:90b:87:: with SMTP id bb7mr5164459pjb.49.1581704161742; Fri, 14 Feb 2020 10:16:01 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 11/19] target/arm: Replace ARM_FEATURE_VFP4 with isar_feature_aa32_simdfmac Date: Fri, 14 Feb 2020 10:15:39 -0800 Message-Id: <20200214181547.21408-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200214181547.21408-1-richard.henderson@linaro.org> References: <20200214181547.21408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::62c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" All remaining tests for VFP4 are for fused multiply-add insns. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 +++++ target/arm/translate-vfp.inc.c | 12 ++++++++---- target/arm/translate.c | 2 +- 3 files changed, 14 insertions(+), 5 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 4ff28418df..f27b8e35df 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3468,6 +3468,11 @@ static inline bool isar_feature_aa32_fp16_dpconv(con= st ARMISARegisters *id) return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1; } =20 +static inline bool isar_feature_aa32_simdfmac(const ARMISARegisters *id) +{ + return FIELD_EX32(id->mvfr1, MVFR1, SIMDFMAC) !=3D 0; +} + static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id) { return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >=3D 1; diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 8913320259..f6f7601fe2 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -1806,8 +1806,10 @@ static bool trans_VFM_sp(DisasContext *s, arg_VFM_sp= *a) * In v7A, UNPREDICTABLE with non-zero vector length/stride; from * v8A, must UNDEF. We choose to UNDEF for both v7A and v8A. */ - if (!arm_dc_feature(s, ARM_FEATURE_VFP4) || - (s->vec_len !=3D 0 || s->vec_stride !=3D 0)) { + if (!dc_isar_feature(aa32_simdfmac, s)) { + return false; + } + if (s->vec_len !=3D 0 || s->vec_stride !=3D 0) { return false; } =20 @@ -1864,8 +1866,10 @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp= *a) * In v7A, UNPREDICTABLE with non-zero vector length/stride; from * v8A, must UNDEF. We choose to UNDEF for both v7A and v8A. */ - if (!arm_dc_feature(s, ARM_FEATURE_VFP4) || - (s->vec_len !=3D 0 || s->vec_stride !=3D 0)) { + if (!dc_isar_feature(aa32_simdfmac, s)) { + return false; + } + if (s->vec_len !=3D 0 || s->vec_stride !=3D 0) { return false; } =20 diff --git a/target/arm/translate.c b/target/arm/translate.c index 3b9bf13933..0da780102c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -4877,7 +4877,7 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) } break; case NEON_3R_VFM_VQRDMLSH: - if (!arm_dc_feature(s, ARM_FEATURE_VFP4)) { + if (!dc_isar_feature(aa32_simdfmac, s)) { return 1; } break; --=20 2.20.1 From nobody Fri Mar 29 00:38:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581704239150486.4111295218254; Fri, 14 Feb 2020 10:17:19 -0800 (PST) Received: from localhost ([::1]:43510 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2fWf-0006GI-Rv for importer@patchew.org; Fri, 14 Feb 2020 13:17:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60894) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2fVV-0004TM-BA for qemu-devel@nongnu.org; Fri, 14 Feb 2020 13:16:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j2fVU-0000FY-Dm for qemu-devel@nongnu.org; Fri, 14 Feb 2020 13:16:05 -0500 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]:33297) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j2fVU-0000FK-7H for qemu-devel@nongnu.org; Fri, 14 Feb 2020 13:16:04 -0500 Received: by mail-pl1-x644.google.com with SMTP id ay11so4028780plb.0 for ; Fri, 14 Feb 2020 10:16:04 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id i3sm7525123pfg.94.2020.02.14.10.16.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Feb 2020 10:16:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hc+/AucXa0inxq9dbV/arLbbzIae9WxdVjI4zl5RMxY=; b=upfqOujZGWqMRFNIe2Y4HrByxOI+hj3ayK33nXTKGLh9nQgtl7T2uG7bkQyxpUfpgE ZmgP10cb/8yOXuRakIVq4khHPFm/Wx0fOdOuvYJtthyjxbYjVPu9fLAJ6R66UMxjGQm6 u83i07TWr+DXx7tjIGC0AObz47i7a90B0tdWpb51vFN4wFQIzQjknvGNkvJcUItzhqpz P+hA0TvbSKBomcEECSUbRln2jdEU7krQ+XMVN26zQUje6KWoq9+DPzAjesGKRB25Nm4v ccdFeIo8jKQpVqX1b9mkuz7KLDnQhJblXLxhXF8AXrLHj9bBlTQVw1nAzyr7vOtWYjEH XF1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hc+/AucXa0inxq9dbV/arLbbzIae9WxdVjI4zl5RMxY=; b=KncrELX3+PPxgMbagT80tmnezGRC8brw7NmroCN8yrW65/BLQoGRgAD/Wlfkuakb96 I3cZbVNKOI/fXnuHcmqa2zjudjHM+XP7BVRbHYkZs/KBM6D1ccOdLFkCLxuUwT/pOu8M TY9xJc2YvJ4VUakHl2/xUaIuW9ZWM8mdeLr5OfZZotiegy8+gqaJ4lzmeWB1z76XXd5w 4JoWIjQ8KMDaoMG7YUbH1MTbhTOaCC6E7EXzV8Zeg3eLYVfNOpazbDKabvzYcbbW2G0h fLRpSo2InlwRnHmxc2O4kaDaSSmKPxu8qFNizSwO3sc/86DMq31KH7WUEoLfKSuWBanC 76FA== X-Gm-Message-State: APjAAAVyy5hLW3VG6VNEPI2XOfOJ2CVL0aPqf/Xv4kZ4lL38p/R2QPRs Ccu37QufgxZwByub9vO3IAK43sqsPX8= X-Google-Smtp-Source: APXvYqxqulXxdG7hk382vvxsBn259LGCN4zy9eER1fHDr7Q40c5Qzx6a1VRmv9v/Ide+z1V4gXWeEw== X-Received: by 2002:a17:902:a5c4:: with SMTP id t4mr4694242plq.242.1581704162920; Fri, 14 Feb 2020 10:16:02 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 12/19] target/arm: Remove ARM_FEATURE_VFP check from disas_vfp_insn Date: Fri, 14 Feb 2020 10:15:40 -0800 Message-Id: <20200214181547.21408-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200214181547.21408-1-richard.henderson@linaro.org> References: <20200214181547.21408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" We now have proper ISA checks within each trans_* function. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 0da780102c..e8c3d4f26f 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -2652,10 +2652,6 @@ static void gen_neon_dup_high16(TCGv_i32 var) */ static int disas_vfp_insn(DisasContext *s, uint32_t insn) { - if (!arm_dc_feature(s, ARM_FEATURE_VFP)) { - return 1; - } - /* * If the decodetree decoder handles this insn it will always * emit code to either execute the insn or generate an appropriate --=20 2.20.1 From nobody Fri Mar 29 00:38:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581704532472398.204093052761; Fri, 14 Feb 2020 10:22:12 -0800 (PST) Received: from localhost ([::1]:43680 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2fbP-0008Pd-9h for importer@patchew.org; Fri, 14 Feb 2020 13:22:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60921) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2fVW-0004Vs-Vx for qemu-devel@nongnu.org; Fri, 14 Feb 2020 13:16:08 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j2fVV-0000GM-Lm for qemu-devel@nongnu.org; Fri, 14 Feb 2020 13:16:06 -0500 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:37088) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j2fVV-0000Fu-FM for qemu-devel@nongnu.org; Fri, 14 Feb 2020 13:16:05 -0500 Received: by mail-pf1-x444.google.com with SMTP id p14so5264995pfn.4 for ; Fri, 14 Feb 2020 10:16:05 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id i3sm7525123pfg.94.2020.02.14.10.16.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Feb 2020 10:16:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KNXQ9uIT7Co5CZWLUxtFqeHCHOoXldJvxdr++tcI33U=; b=p0TaMt+fQy9mNLg6/mlONYUBZ8Ubz9qwoEP++u5+q95ZSw4TxN78D30n9LgP0kSIXB c/B16AWveocGQ/PH60hrOV/Hceqe4EAmCqJWcHndjka8Q3io0iGeba03jZafyvruNZaY Lnvo+6nGlcjQu9fCWefveEVTZI6tt53R3RWpmvXd4Hw013bDHu0tHgn6i8cjsl5gf7gM HHIXeEm3YarIz8BAGKec1I09BtV50tQLMU+7LMyULJXG2TrL7aCKOQ/yxbYCuNLkdbFk jrz/omI5pC9V5fg9CWHYFWZ7xTUOWj7NGPNfjsWHvsscP/k/Eq5LE3xzLv4QqcQvU2oZ YtRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KNXQ9uIT7Co5CZWLUxtFqeHCHOoXldJvxdr++tcI33U=; b=tH3eB+7WX2oRoSbZoMi/bH2mlZXftsIbfTSfJ4xog9xGhQswwIi3rptOJ6ykXW3GRR j3+vBVV0WoStx8b64DumDCYzsnXBp8bqRr/qBCODNbPPnvTZl97gRqXWbQ7GbgeqVSOi MrF68UIzuWe7RbT5mj+XdJsYIDzTmpUc16TK70bSttMdSSHSTcmNPXW+lPICRFR37lXw aPizTmiYeplC/WqitbkactQZdNVEqxnMN2gRDqoUsgnPNiUlAD8v0otBgKuG9M6QKW0H DelZQxAqZ9BC49EjiwkNGbr7L8y5nrkmBpEEa0yEfzdE0XyYQCX5LUzyF/9jXd5QBqL7 hHFg== X-Gm-Message-State: APjAAAW4/PK0EG/Kbzd5UapSs55Dh5/5ovBit6wZ27H12w7i9hdKXiKW /R3HIIhx/1+6qtuIVtWjcxUpdGI9P6w= X-Google-Smtp-Source: APXvYqzdiCTG6m9MKi+gipSGguA2OM9G+qIjl3IwUcFBUhbnd2RVyP9osEsERfRukvC31MoPZvjpsA== X-Received: by 2002:a65:6147:: with SMTP id o7mr5138480pgv.442.1581704164122; Fri, 14 Feb 2020 10:16:04 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 13/19] target/arm: Move VLLDM and VLSTM to vfp.decode Date: Fri, 14 Feb 2020 10:15:41 -0800 Message-Id: <20200214181547.21408-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200214181547.21408-1-richard.henderson@linaro.org> References: <20200214181547.21408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Now that we no longer have an early check for ARM_FEATURE_VFP, we can use the proper ISA check in trans_VLLDM_VLSTM. Signed-off-by: Richard Henderson --- target/arm/vfp.decode | 2 ++ target/arm/translate-vfp.inc.c | 35 ++++++++++++++++++++++ target/arm/translate.c | 53 ++++++---------------------------- 3 files changed, 46 insertions(+), 44 deletions(-) diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode index a67b3f29ee..592fe9e1e4 100644 --- a/target/arm/vfp.decode +++ b/target/arm/vfp.decode @@ -242,3 +242,5 @@ VCVT_sp_int ---- 1110 1.11 110 s:1 .... 1010 rz:1 1.0 = .... \ vd=3D%vd_sp vm=3D%vm_sp VCVT_dp_int ---- 1110 1.11 110 s:1 .... 1011 rz:1 1.0 .... \ vd=3D%vd_sp vm=3D%vm_dp + +VLLDM_VLSTM 1110 1100 001 l:1 rn:4 0000 1010 0000 0000 diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index f6f7601fe2..8f2b97e0e7 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -2816,3 +2816,38 @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_V= CVT_dp_int *a) tcg_temp_free_ptr(fpst); return true; } + +/* + * Decode VLLDM of VLSTM are nonstandard because: + * * if there is no FPU then these insns must NOP in + * Secure state and UNDEF in Nonsecure state + * * if there is an FPU then these insns do not have + * the usual behaviour that disas_vfp_insn() provides of + * being controlled by CPACR/NSACR enable bits or the + * lazy-stacking logic. + */ +static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a) +{ + TCGv_i32 fptr; + + if (!arm_dc_feature(s, ARM_FEATURE_M) || + !arm_dc_feature(s, ARM_FEATURE_V8)) { + return false; + } + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + /* No FPU: NOP if secure, otherwise UNDEF. */ + return s->v8m_secure; + } + + fptr =3D load_reg(s, a->rn); + if (a->l) { + gen_helper_v7m_vlldm(cpu_env, fptr); + } else { + gen_helper_v7m_vlstm(cpu_env, fptr); + } + tcg_temp_free_i32(fptr); + + /* End the TB, because we have updated FP control bits */ + s->base.is_jmp =3D DISAS_UPDATE; + return true; +} diff --git a/target/arm/translate.c b/target/arm/translate.c index e8c3d4f26f..b2641b4262 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10708,53 +10708,18 @@ static void disas_thumb2_insn(DisasContext *s, ui= nt32_t insn) goto illegal_op; /* op0 =3D 0b11 : unallocated */ } =20 - /* - * Decode VLLDM and VLSTM first: these are nonstandard because: - * * if there is no FPU then these insns must NOP in - * Secure state and UNDEF in Nonsecure state - * * if there is an FPU then these insns do not have - * the usual behaviour that disas_vfp_insn() provides of - * being controlled by CPACR/NSACR enable bits or the - * lazy-stacking logic. - */ - if (arm_dc_feature(s, ARM_FEATURE_V8) && - (insn & 0xffa00f00) =3D=3D 0xec200a00) { - /* 0b1110_1100_0x1x_xxxx_xxxx_1010_xxxx_xxxx - * - VLLDM, VLSTM - * We choose to UNDEF if the RAZ bits are non-zero. - */ - if (!s->v8m_secure || (insn & 0x0040f0ff)) { + if (disas_vfp_insn(s, insn)) { + if (((insn >> 8) & 0xe) =3D=3D 10 && + dc_isar_feature(aa32_fpsp_v2, s)) { + /* FP, and the CPU supports it */ goto illegal_op; + } else { + /* All other insns: NOCP */ + gen_exception_insn(s, s->pc_curr, EXCP_NOCP, + syn_uncategorized(), + default_exception_el(s)); } - - if (arm_dc_feature(s, ARM_FEATURE_VFP)) { - uint32_t rn =3D (insn >> 16) & 0xf; - TCGv_i32 fptr =3D load_reg(s, rn); - - if (extract32(insn, 20, 1)) { - gen_helper_v7m_vlldm(cpu_env, fptr); - } else { - gen_helper_v7m_vlstm(cpu_env, fptr); - } - tcg_temp_free_i32(fptr); - - /* End the TB, because we have updated FP control bits= */ - s->base.is_jmp =3D DISAS_UPDATE; - } - break; } - if (arm_dc_feature(s, ARM_FEATURE_VFP) && - ((insn >> 8) & 0xe) =3D=3D 10) { - /* FP, and the CPU supports it */ - if (disas_vfp_insn(s, insn)) { - goto illegal_op; - } - break; - } - - /* All other insns: NOCP */ - gen_exception_insn(s, s->pc_curr, EXCP_NOCP, syn_uncategorized= (), - default_exception_el(s)); break; } if ((insn & 0xfe000a00) =3D=3D 0xfc000800 --=20 2.20.1 From nobody Fri Mar 29 00:38:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id i3sm7525123pfg.94.2020.02.14.10.16.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Feb 2020 10:16:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2kZ9BsLAsFQXYPLtyMT3ZoVnOYLNLzYgitMu8C6B1ag=; b=kfgDX/AvC7uAk2+/8dqYe+dRnlgoXukH0uruVMfMj9VSUyM3F2LxP3l93gzpy5mSH9 lbip3mDlr+1wqQ/v1DNOo9EwUYHQgLXFdcX3hyDbeTPIApbyVQVeyrlweUp7KT6yf6zw 3xVb8wDIHXqI0LYzLRJonFw/EasfWyN/0EWLwb48LRKYxUjozt+eAeabiM09Sdi4x/dZ 1Bu089O3lo1QXr1sJozglvqtK/rvVvXkN/t0rlQIGCjqOtHigUOK8ZbFDQ4oB9cRaRcs pLMNoeiKXmTbOgyK2eypewi5R+yvP83qlgak9nPikfJ5rVgxt2ZXHxH5zzLfNxn3w05S F/Rw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2kZ9BsLAsFQXYPLtyMT3ZoVnOYLNLzYgitMu8C6B1ag=; b=qRjRh7y5yqMauDyRSv+IMV42yI1h2pkybxZdzVcusbTSu7ru7qQDzxaljfSfqCdaOu L0ttu6W8/Qs2jt7wyUZk1kua77WfD8PDHc+aZD34CToPB2yMqMrVcWbWHCmgmb4NOP7e CDP2WI4vynKxFZVxdbqlelT2rP0qDCzTxFopvdeBFA8TX/97aAn6bFZl/wSBu6ji0o4q nCJoIB9j67rBLz73fFr8pPWpi53NpTwlPUN85PtBPqOiPbzwUcQ62Qso3kesnKVc/9Km U2LR0AUqDdp6Gf/OjFOY/6KhkokN72pcnOe0wVBV+EbmNqrOrsWUKwxMtCg8rAQhFWb/ bd2Q== X-Gm-Message-State: APjAAAWRYIYr7aD/HWq/ym3pYDwxMiIGkRISTjVyW2tTUsw7WgBQBqRj jCwPyJX4t9dHmjmiC+PKxRw4ZMfp8s0= X-Google-Smtp-Source: APXvYqwwK6+u6ob85GTch+wY+iB9rRTfZzcmgkuGythmfDj1PKt58Dqk17Squ8jVVPWLs7W7hFPazA== X-Received: by 2002:a65:68ce:: with SMTP id k14mr4655713pgt.336.1581704165314; Fri, 14 Feb 2020 10:16:05 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 14/19] target/arm: Move the vfp decodetree calls next to the base isa Date: Fri, 14 Feb 2020 10:15:42 -0800 Message-Id: <20200214181547.21408-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200214181547.21408-1-richard.henderson@linaro.org> References: <20200214181547.21408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Have the calls adjacent as an intermediate step toward actually merging the decodes. Signed-off-by: Richard Henderson --- target/arm/translate.c | 80 +++++++++++++----------------------------- 1 file changed, 24 insertions(+), 56 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index b2641b4262..5cabe6b2e9 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -2646,31 +2646,6 @@ static void gen_neon_dup_high16(TCGv_i32 var) tcg_temp_free_i32(tmp); } =20 -/* - * Disassemble a VFP instruction. Returns nonzero if an error occurred - * (ie. an undefined instruction). - */ -static int disas_vfp_insn(DisasContext *s, uint32_t insn) -{ - /* - * If the decodetree decoder handles this insn it will always - * emit code to either execute the insn or generate an appropriate - * exception; so we don't need to ever return non-zero to tell - * the calling code to emit an UNDEF exception. - */ - if (extract32(insn, 28, 4) =3D=3D 0xf) { - if (disas_vfp_uncond(s, insn)) { - return 0; - } - } else { - if (disas_vfp(s, insn)) { - return 0; - } - } - /* If the decodetree decoder didn't handle this insn, it must be UNDEF= */ - return 1; -} - static inline bool use_goto_tb(DisasContext *s, target_ulong dest) { #ifndef CONFIG_USER_ONLY @@ -10524,7 +10499,9 @@ static void disas_arm_insn(DisasContext *s, unsigne= d int insn) ARCH(5); =20 /* Unconditional instructions. */ - if (disas_a32_uncond(s, insn)) { + /* TODO: Perhaps merge these into one decodetree output file. */ + if (disas_a32_uncond(s, insn) || + disas_vfp_uncond(s, insn)) { return; } /* fall back to legacy decoder */ @@ -10551,13 +10528,6 @@ static void disas_arm_insn(DisasContext *s, unsign= ed int insn) } return; } - if ((insn & 0x0f000e10) =3D=3D 0x0e000a00) { - /* VFP. */ - if (disas_vfp_insn(s, insn)) { - goto illegal_op; - } - return; - } if ((insn & 0x0e000f00) =3D=3D 0x0c000100) { if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) { /* iWMMXt register transfer. */ @@ -10588,7 +10558,9 @@ static void disas_arm_insn(DisasContext *s, unsigne= d int insn) arm_skip_unless(s, cond); } =20 - if (disas_a32(s, insn)) { + /* TODO: Perhaps merge these into one decodetree output file. */ + if (disas_a32(s, insn) || + disas_vfp(s, insn)) { return; } /* fall back to legacy decoder */ @@ -10597,12 +10569,7 @@ static void disas_arm_insn(DisasContext *s, unsign= ed int insn) case 0xc: case 0xd: case 0xe: - if (((insn >> 8) & 0xe) =3D=3D 10) { - /* VFP. */ - if (disas_vfp_insn(s, insn)) { - goto illegal_op; - } - } else if (disas_coproc_insn(s, insn)) { + if (((insn >> 8) & 0xe) !=3D 10 && disas_coproc_insn(s, insn)) { /* Coprocessor. */ goto illegal_op; } @@ -10691,7 +10658,14 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) ARCH(6T2); } =20 - if (disas_t32(s, insn)) { + /* + * TODO: Perhaps merge these into one decodetree output file. + * Note disas_vfp is written for a32 with cond field in the=20 + * top nibble. The t32 encoding requires 0xe in the top nibble. + */ + if (disas_t32(s, insn) || + disas_vfp_uncond(s, insn) || + ((insn >> 28) =3D=3D 0xe && disas_vfp(s, insn))) { return; } /* fall back to legacy decoder */ @@ -10708,17 +10682,15 @@ static void disas_thumb2_insn(DisasContext *s, ui= nt32_t insn) goto illegal_op; /* op0 =3D 0b11 : unallocated */ } =20 - if (disas_vfp_insn(s, insn)) { - if (((insn >> 8) & 0xe) =3D=3D 10 && - dc_isar_feature(aa32_fpsp_v2, s)) { - /* FP, and the CPU supports it */ - goto illegal_op; - } else { - /* All other insns: NOCP */ - gen_exception_insn(s, s->pc_curr, EXCP_NOCP, - syn_uncategorized(), - default_exception_el(s)); - } + if (((insn >> 8) & 0xe) =3D=3D 10 && + dc_isar_feature(aa32_fpsp_v2, s)) { + /* FP, and the CPU supports it */ + goto illegal_op; + } else { + /* All other insns: NOCP */ + gen_exception_insn(s, s->pc_curr, EXCP_NOCP, + syn_uncategorized(), + default_exception_el(s)); } break; } @@ -10740,10 +10712,6 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) if (disas_neon_data_insn(s, insn)) { goto illegal_op; } - } else if (((insn >> 8) & 0xe) =3D=3D 10) { - if (disas_vfp_insn(s, insn)) { - goto illegal_op; - } } else { if (insn & (1 << 28)) goto illegal_op; --=20 2.20.1 From nobody Fri Mar 29 00:38:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581704490290432.5252460426125; Fri, 14 Feb 2020 10:21:30 -0800 (PST) Received: from localhost ([::1]:43640 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2faj-0006Y2-15 for importer@patchew.org; Fri, 14 Feb 2020 13:21:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60941) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2fVZ-0004cJ-3E for qemu-devel@nongnu.org; Fri, 14 Feb 2020 13:16:10 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j2fVX-0000Hq-W1 for qemu-devel@nongnu.org; Fri, 14 Feb 2020 13:16:09 -0500 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]:38895) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j2fVX-0000HU-Pz for qemu-devel@nongnu.org; Fri, 14 Feb 2020 13:16:07 -0500 Received: by mail-pg1-x542.google.com with SMTP id d6so5339844pgn.5 for ; Fri, 14 Feb 2020 10:16:07 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id i3sm7525123pfg.94.2020.02.14.10.16.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Feb 2020 10:16:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=M8UM5e+3VRfykuEhj/KpHZJCPyatXYB/tx3EOhHQRHg=; b=P2a3DJc5xDlZOW9ERiwMm2spp1DfTNP6HytA05EBy4VJ6VjnjDmpDWo3u1al6wnrcu 4eu6uz1lmVNk6+n8YQXvZiGj5XOPC6yDBt+InvAaKmEL8VzaJEqN8LYaPc5FyxFiTW8I jgC8s+c8/9a+WSFRPcmhBnXkeQY6VAmslVw/KczReCT3bLvNxKRXX3VkJA6TL3+Et0aF QZrP78lB5CGcujeJHbaIMvCTAPAi63ZochngZinYJgXgxCQIy+0lEC+TIDCZMYo08hpk 4dTnDb9lPrj94DvEAsVuo1/AUPjITVSIZqKsqpcvmr0uaCwPFCmfyIuoI17/snwsk3b4 +EzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=M8UM5e+3VRfykuEhj/KpHZJCPyatXYB/tx3EOhHQRHg=; b=oNiJ7Ga/K1wtov2rRFMSHKTtD0/z3lEkwDJL32oN2ekmhDgNGwrWVOtgeLtM2UwqAD iIHhRYpLoiUpKC5UuNZypNjSdacoMLmc2MgVbEc72YP+r1XpldH8vq5pGYtOWkep8/pd I45o30G63gkuwEaiV8NJcXc1+Rh6R6F8YZPfccAI6LjkcYkKw343K3cufUtLRPWy1BbL PhwrgAP/MGmRQtzjapA6MgiVbky7rrehSh7eE4TR7litY717cz62BoNFqe7b2pGnAA11 fZqYzzbtmjjV/jr7nZ/RH/0Nqn3RNnGqF3wzcbaC/2dhc2TJvTLElAoo8wVDkCHaw3ma kMyg== X-Gm-Message-State: APjAAAXAjZSDaXHiZiFCIadShd9PJJGcbTbfFZloqqn5nZTzIg3RR4Bs OJKYK3Pyo6tNLsvU5FBqFY+Q6mB/Sbk= X-Google-Smtp-Source: APXvYqzl2nh4H3juslcW0ct9JvnktgZ0ZbSimHMGZ1sL+hncyiRAImarJeZmWCehSZseN5tu+Ea7/Q== X-Received: by 2002:a63:5a65:: with SMTP id k37mr5002076pgm.264.1581704166488; Fri, 14 Feb 2020 10:16:06 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 15/19] linux-user/arm: Replace ARM_FEATURE_VFP* tests for HWCAP Date: Fri, 14 Feb 2020 10:15:43 -0800 Message-Id: <20200214181547.21408-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200214181547.21408-1-richard.henderson@linaro.org> References: <20200214181547.21408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Use isar feature tests instead of feature bit tests. Although none of QEMUs current cpus have VFPv3 without D32, replace the large comment explaining why with one line that sets ARM_HWCAP_ARM_VFPv3D16 under the correct conditions. Mirror the test sequence used in the linux kernel. Signed-off-by: Richard Henderson --- linux-user/elfload.c | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index f3080a1635..c52c814a2e 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -468,22 +468,28 @@ static uint32_t get_elf_hwcap(void) =20 /* EDSP is in v5TE and above, but all our v5 CPUs are v5TE */ GET_FEATURE(ARM_FEATURE_V5, ARM_HWCAP_ARM_EDSP); - GET_FEATURE(ARM_FEATURE_VFP, ARM_HWCAP_ARM_VFP); GET_FEATURE(ARM_FEATURE_IWMMXT, ARM_HWCAP_ARM_IWMMXT); GET_FEATURE(ARM_FEATURE_THUMB2EE, ARM_HWCAP_ARM_THUMBEE); GET_FEATURE(ARM_FEATURE_NEON, ARM_HWCAP_ARM_NEON); - GET_FEATURE(ARM_FEATURE_VFP3, ARM_HWCAP_ARM_VFPv3); GET_FEATURE(ARM_FEATURE_V6K, ARM_HWCAP_ARM_TLS); - GET_FEATURE(ARM_FEATURE_VFP4, ARM_HWCAP_ARM_VFPv4); + GET_FEATURE(ARM_FEATURE_LPAE, ARM_HWCAP_ARM_LPAE); + GET_FEATURE_ID(arm_div, ARM_HWCAP_ARM_IDIVA); GET_FEATURE_ID(thumb_div, ARM_HWCAP_ARM_IDIVT); - /* All QEMU's VFPv3 CPUs have 32 registers, see VFP_DREG in translate.= c. - * Note that the ARM_HWCAP_ARM_VFPv3D16 bit is always the inverse of - * ARM_HWCAP_ARM_VFPD32 (and so always clear for QEMU); it is unrelated - * to our VFP_FP16 feature bit. + /* + * Note that none of QEMU's cpus have double precision without single + * precision support in VFP, so only test the single precision field. */ - GET_FEATURE(ARM_FEATURE_VFP3, ARM_HWCAP_ARM_VFPD32); - GET_FEATURE(ARM_FEATURE_LPAE, ARM_HWCAP_ARM_LPAE); + GET_FEATURE_ID(aa32_fpsp_v2, ARM_HWCAP_ARM_VFP); + if (cpu_isar_feature(aa32_fpsp_v3, cpu)) { + hwcaps |=3D ARM_HWCAP_ARM_VFPv3; + if (cpu_isar_feature(aa32_simd_r32, cpu)) { + hwcaps |=3D ARM_HWCAP_ARM_VFPD32; + } else { + hwcaps |=3D ARM_HWCAP_ARM_VFPv3D16; + } + } + GET_FEATURE_ID(aa32_simdfmac, ARM_HWCAP_ARM_VFPv4); =20 return hwcaps; } --=20 2.20.1 From nobody Fri Mar 29 00:38:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581704369863828.7456147258998; Fri, 14 Feb 2020 10:19:29 -0800 (PST) Received: from localhost ([::1]:43562 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2fYm-0001lu-5P for importer@patchew.org; Fri, 14 Feb 2020 13:19:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60960) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2fVb-0004gX-B0 for qemu-devel@nongnu.org; Fri, 14 Feb 2020 13:16:13 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j2fVZ-0000J9-Ej for qemu-devel@nongnu.org; Fri, 14 Feb 2020 13:16:11 -0500 Received: from mail-pf1-x442.google.com ([2607:f8b0:4864:20::442]:43077) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j2fVZ-0000IX-6u for qemu-devel@nongnu.org; Fri, 14 Feb 2020 13:16:09 -0500 Received: by mail-pf1-x442.google.com with SMTP id s1so5247084pfh.10 for ; Fri, 14 Feb 2020 10:16:09 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id i3sm7525123pfg.94.2020.02.14.10.16.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Feb 2020 10:16:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3XMTldT5aciMedkzJMCvbzI5Oq2p1yxlgK/fC8SFtRE=; b=DqVXLRHk2AH0TOk9roOM71XK1ogP/3Ai25uA6tTNypXI41T+M+J6t/afMcMMWYNAFV vHCuUhb6oWtcvads4BwBg8CUiJLn3SdfcGAvfpwKW086+rMgpawqDdfzcg4j+1JGRjqq v3hSfOOnZc/T1k+g6ONKUIISblkvzsiApDj2HoSIcjR/ol9mHLMou9P+jz1bcl4lg3og jkj2JHfz/xPB0Po+AWvSp+pIBFNKVZMeo9D6sz+qTcf/LBS8Eq6ricOWESWdySNx6xDW rIdzHWw3+v9t62EZ8LaTb+vqWzBqgTWtvuFPhzVzigcLetR/Zi4+Fxi9ZJaJEyP6icvi yU0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3XMTldT5aciMedkzJMCvbzI5Oq2p1yxlgK/fC8SFtRE=; b=LMC/Ahgq93SpcYPXo0ayD8THGND8SA65yRY5V+pl8fXiB2yXmfFBegNlZU4SqmGMdb DHhOUlddnimnTYU1MSnyoEhJGIQYTRSXc+zggVXkwOTAZCZZh7eLYoiWzLbC2ZJzWyqo X/oc3JJuo9AAI6JJY4QDOxbkqMQUwqbMZf46l0hxPGr1hMOHf+CILvstX14bv48Lmci2 NAJRlJRR1sIo8i1vaXFoaYDB8x6iZOwjco5+dkAXvBNUCxZkzMW/IEOMk68NBb3BHvAg pt/KT07K3Y6TvwKCIYiUbIDC18GsX74uHsYfh1/36yCiRbg4JSwvm/t2uYRoFrVYx0hC lAjg== X-Gm-Message-State: APjAAAWDMyZCnNnBGRnSp/o0Bin4Xdx1R+I2+yYch/hB+kBBHLM553C6 kbOMAHFXwOydT//65ITLrmbaKOFUlq4= X-Google-Smtp-Source: APXvYqyDDAOefOCF3M6oXuZnQJF/qDYLF7jsv+s0EzVE10xGYNmv6nQYq2/Xl0Kgxp4531rlMgYzBg== X-Received: by 2002:a63:242:: with SMTP id 63mr4685514pgc.84.1581704167558; Fri, 14 Feb 2020 10:16:07 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 16/19] target/arm: Remove ARM_FEATURE_VFP* Date: Fri, 14 Feb 2020 10:15:44 -0800 Message-Id: <20200214181547.21408-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200214181547.21408-1-richard.henderson@linaro.org> References: <20200214181547.21408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" We have converted all tests against these features to ISAR tests. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 3 --- target/arm/cpu.c | 25 ------------------------- target/arm/cpu64.c | 3 --- target/arm/kvm32.c | 5 ----- target/arm/kvm64.c | 1 - 5 files changed, 37 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index f27b8e35df..571038d0de 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1858,7 +1858,6 @@ QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= =3D R_V7M_CSSELR_INDEX_MASK); * mapping in linux-user/elfload.c:get_elf_hwcap(). */ enum arm_features { - ARM_FEATURE_VFP, ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ @@ -1867,7 +1866,6 @@ enum arm_features { ARM_FEATURE_V7, ARM_FEATURE_THUMB2, ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ - ARM_FEATURE_VFP3, ARM_FEATURE_NEON, ARM_FEATURE_M, /* Microcontroller profile. */ ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ @@ -1878,7 +1876,6 @@ enum arm_features { ARM_FEATURE_V5, ARM_FEATURE_STRONGARM, ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ - ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */ ARM_FEATURE_GENERIC_TIMER, ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=3D15 */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 8d3eff8cb3..afb80d4636 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1208,13 +1208,6 @@ void arm_cpu_post_init(Object *obj) if (arm_feature(&cpu->env, ARM_FEATURE_M)) { set_feature(&cpu->env, ARM_FEATURE_PMSA); } - /* Similarly for the VFP feature bits */ - if (arm_feature(&cpu->env, ARM_FEATURE_VFP4)) { - set_feature(&cpu->env, ARM_FEATURE_VFP3); - } - if (arm_feature(&cpu->env, ARM_FEATURE_VFP3)) { - set_feature(&cpu->env, ARM_FEATURE_VFP); - } =20 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { @@ -1440,10 +1433,6 @@ static void arm_cpu_realizefn(DeviceState *dev, Erro= r **errp) uint64_t t; uint32_t u; =20 - unset_feature(env, ARM_FEATURE_VFP); - unset_feature(env, ARM_FEATURE_VFP3); - unset_feature(env, ARM_FEATURE_VFP4); - t =3D cpu->isar.id_aa64isar1; t =3D FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0); cpu->isar.id_aa64isar1 =3D t; @@ -1855,7 +1844,6 @@ static void arm926_initfn(Object *obj) =20 cpu->dtb_compatible =3D "arm,arm926"; set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_VFP); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); cpu->midr =3D 0x41069265; @@ -1896,7 +1884,6 @@ static void arm1026_initfn(Object *obj) =20 cpu->dtb_compatible =3D "arm,arm1026"; set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_VFP); set_feature(&cpu->env, ARM_FEATURE_AUXCR); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); @@ -1944,7 +1931,6 @@ static void arm1136_r2_initfn(Object *obj) =20 cpu->dtb_compatible =3D "arm,arm1136"; set_feature(&cpu->env, ARM_FEATURE_V6); - set_feature(&cpu->env, ARM_FEATURE_VFP); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); @@ -1976,7 +1962,6 @@ static void arm1136_initfn(Object *obj) cpu->dtb_compatible =3D "arm,arm1136"; set_feature(&cpu->env, ARM_FEATURE_V6K); set_feature(&cpu->env, ARM_FEATURE_V6); - set_feature(&cpu->env, ARM_FEATURE_VFP); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); @@ -2007,7 +1992,6 @@ static void arm1176_initfn(Object *obj) =20 cpu->dtb_compatible =3D "arm,arm1176"; set_feature(&cpu->env, ARM_FEATURE_V6K); - set_feature(&cpu->env, ARM_FEATURE_VFP); set_feature(&cpu->env, ARM_FEATURE_VAPA); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); @@ -2040,7 +2024,6 @@ static void arm11mpcore_initfn(Object *obj) =20 cpu->dtb_compatible =3D "arm,arm11mpcore"; set_feature(&cpu->env, ARM_FEATURE_V6K); - set_feature(&cpu->env, ARM_FEATURE_VFP); set_feature(&cpu->env, ARM_FEATURE_VAPA); set_feature(&cpu->env, ARM_FEATURE_MPIDR); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); @@ -2106,7 +2089,6 @@ static void cortex_m4_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_M); set_feature(&cpu->env, ARM_FEATURE_M_MAIN); set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); - set_feature(&cpu->env, ARM_FEATURE_VFP4); cpu->midr =3D 0x410fc240; /* r0p0 */ cpu->pmsav7_dregion =3D 8; cpu->isar.mvfr0 =3D 0x10110021; @@ -2137,7 +2119,6 @@ static void cortex_m7_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_M); set_feature(&cpu->env, ARM_FEATURE_M_MAIN); set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); - set_feature(&cpu->env, ARM_FEATURE_VFP4); cpu->midr =3D 0x411fc272; /* r1p2 */ cpu->pmsav7_dregion =3D 8; cpu->isar.mvfr0 =3D 0x10110221; @@ -2169,7 +2150,6 @@ static void cortex_m33_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_M_MAIN); set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); - set_feature(&cpu->env, ARM_FEATURE_VFP4); cpu->midr =3D 0x410fd213; /* r0p3 */ cpu->pmsav7_dregion =3D 16; cpu->sau_sregion =3D 8; @@ -2253,7 +2233,6 @@ static void cortex_r5f_initfn(Object *obj) ARMCPU *cpu =3D ARM_CPU(obj); =20 cortex_r5_initfn(obj); - set_feature(&cpu->env, ARM_FEATURE_VFP3); cpu->isar.mvfr0 =3D 0x10110221; cpu->isar.mvfr1 =3D 0x00000011; } @@ -2272,7 +2251,6 @@ static void cortex_a8_initfn(Object *obj) =20 cpu->dtb_compatible =3D "arm,cortex-a8"; set_feature(&cpu->env, ARM_FEATURE_V7); - set_feature(&cpu->env, ARM_FEATURE_VFP3); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); @@ -2340,7 +2318,6 @@ static void cortex_a9_initfn(Object *obj) =20 cpu->dtb_compatible =3D "arm,cortex-a9"; set_feature(&cpu->env, ARM_FEATURE_V7); - set_feature(&cpu->env, ARM_FEATURE_VFP3); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_EL3); @@ -2405,7 +2382,6 @@ static void cortex_a7_initfn(Object *obj) =20 cpu->dtb_compatible =3D "arm,cortex-a7"; set_feature(&cpu->env, ARM_FEATURE_V7VE); - set_feature(&cpu->env, ARM_FEATURE_VFP4); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); @@ -2451,7 +2427,6 @@ static void cortex_a15_initfn(Object *obj) =20 cpu->dtb_compatible =3D "arm,cortex-a15"; set_feature(&cpu->env, ARM_FEATURE_V7VE); - set_feature(&cpu->env, ARM_FEATURE_VFP4); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index f0d98bc79d..e4e8499e71 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -102,7 +102,6 @@ static void aarch64_a57_initfn(Object *obj) =20 cpu->dtb_compatible =3D "arm,cortex-a57"; set_feature(&cpu->env, ARM_FEATURE_V8); - set_feature(&cpu->env, ARM_FEATURE_VFP4); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); set_feature(&cpu->env, ARM_FEATURE_AARCH64); @@ -156,7 +155,6 @@ static void aarch64_a53_initfn(Object *obj) =20 cpu->dtb_compatible =3D "arm,cortex-a53"; set_feature(&cpu->env, ARM_FEATURE_V8); - set_feature(&cpu->env, ARM_FEATURE_VFP4); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); set_feature(&cpu->env, ARM_FEATURE_AARCH64); @@ -210,7 +208,6 @@ static void aarch64_a72_initfn(Object *obj) =20 cpu->dtb_compatible =3D "arm,cortex-a72"; set_feature(&cpu->env, ARM_FEATURE_V8); - set_feature(&cpu->env, ARM_FEATURE_VFP4); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); set_feature(&cpu->env, ARM_FEATURE_AARCH64); diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c index 3a8b437eef..2e7d7a1e02 100644 --- a/target/arm/kvm32.c +++ b/target/arm/kvm32.c @@ -122,7 +122,6 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *= ahcf) * bits, but a few must be tested. */ set_feature(&features, ARM_FEATURE_V7VE); - set_feature(&features, ARM_FEATURE_VFP3); set_feature(&features, ARM_FEATURE_GENERIC_TIMER); =20 if (extract32(id_pfr0, 12, 4) =3D=3D 1) { @@ -131,10 +130,6 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures = *ahcf) if (extract32(ahcf->isar.mvfr1, 12, 4) =3D=3D 1) { set_feature(&features, ARM_FEATURE_NEON); } - if (extract32(ahcf->isar.mvfr1, 28, 4) =3D=3D 1) { - /* FMAC support implies VFPv4 */ - set_feature(&features, ARM_FEATURE_VFP4); - } =20 ahcf->features =3D features; =20 diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 3bae9e4a66..e555e8dbc0 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -603,7 +603,6 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *= ahcf) * feature bits. */ set_feature(&features, ARM_FEATURE_V8); - set_feature(&features, ARM_FEATURE_VFP4); set_feature(&features, ARM_FEATURE_NEON); set_feature(&features, ARM_FEATURE_AARCH64); set_feature(&features, ARM_FEATURE_PMU); --=20 2.20.1 From nobody Fri Mar 29 00:38:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 158170468148998.20273061168291; Fri, 14 Feb 2020 10:24:41 -0800 (PST) Received: from localhost ([::1]:43748 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2fdn-0004Qr-SW for importer@patchew.org; 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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id i3sm7525123pfg.94.2020.02.14.10.16.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Feb 2020 10:16:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Ao4evsYU9ClX8Sc2l9Bc6gohu0+9pes1UrtoAkrt1oc=; b=aH4PVPtUVS7G/LvGgNAACMyr71FeKO6+eRnv/0z2ULDUCtop7oALXbwHeFzLKnbZFk 81wbP5/QYZG6SBiTk9+akX4nLFNYt2nWIjc8hbvJ7xhiA3wQ/D/D8qrwIhYwWkmadMNq qTSo6FjhnRkTaPtUaZcNSCzwZ2Uh7KM6UKel5WSrdImodDCKYZL3Xy7viiguNuMVHz20 XyBmT1zs7NSG4lnDw/45UWMCf81m/g+p0blBS7sIZXH8YpKwMiCtYyIyM+31n/Sdc6ae z/tOVcJouJuMgitjWEQQcbNmRu+Fx5j3hYFVNuurJXXoWareH/HNIqftajyUdK1KM5i5 Fkyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Ao4evsYU9ClX8Sc2l9Bc6gohu0+9pes1UrtoAkrt1oc=; b=IeQkyEylZVQvKtFYBx5GgkZx3tnmy47AmQYSkfeEvqBPzSlVlgg7PA3WaQFJ1AlqVq szA6KVNK5g/G4S73ZtvYaTCjtTCbG8hrGj5MXyFcHvVTMEBBb97KpBk/8f8zvjHevkLU MsCs2+muVPzKVRQMVb4fYTSd/gg5a0lGovV+1O7IKw9Ict1pyoudSqX1XBiV9vwRTAJM 6fjD5qzLolCeoEnVD9JbGbzpBCwHnh7WTcbP46Jf2BYOBv5Vn2pF9UcmW5ePnHPPmt7x dvHvrXIhzuDIjwzWlk/2/4csCxujw9LuGhCXVDGwBHNW0Gtr/+lueJJZG3T3O/4wVZFj qnvg== X-Gm-Message-State: APjAAAXe+LLhmXkuEirT97G80A4UNfIDULInuVUb9C/KcFg7c/F4kGJL hpsWXrT54jOZWJM1N0weYV+NdH0TwfI= X-Google-Smtp-Source: APXvYqx/DrfWFwrWfMK3rLHLB6gWQP42wykNDJQPnQ9TY//H+sEbE5QjX0dIJkuQTu2dpIqFW34JVQ== X-Received: by 2002:a63:7744:: with SMTP id s65mr4744619pgc.312.1581704168515; Fri, 14 Feb 2020 10:16:08 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 17/19] target/arm: Add formats for some vfp 2 and 3-register insns Date: Fri, 14 Feb 2020 10:15:45 -0800 Message-Id: <20200214181547.21408-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200214181547.21408-1-richard.henderson@linaro.org> References: <20200214181547.21408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Those vfp instructions without extra opcode fields can share a common @format for brevity. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/vfp.decode | 134 ++++++++++++++++-------------------------- 1 file changed, 52 insertions(+), 82 deletions(-) diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode index 592fe9e1e4..4f294f88be 100644 --- a/target/arm/vfp.decode +++ b/target/arm/vfp.decode @@ -46,6 +46,14 @@ =20 %vmov_imm 16:4 0:4 =20 +@vfp_dnm_s ................................ vm=3D%vm_sp vn=3D%vn_sp vd= =3D%vd_sp +@vfp_dnm_d ................................ vm=3D%vm_dp vn=3D%vn_dp vd= =3D%vd_dp + +@vfp_dm_ss ................................ vm=3D%vm_sp vd=3D%vd_sp +@vfp_dm_dd ................................ vm=3D%vm_dp vd=3D%vd_dp +@vfp_dm_ds ................................ vm=3D%vm_sp vd=3D%vd_dp +@vfp_dm_sd ................................ vm=3D%vm_dp vd=3D%vd_sp + # VMOV scalar to general-purpose register; note that this does # include some Neon cases. VMOV_to_gp ---- 1110 u:1 1. 1 .... rt:4 1011 ... 1 0000 \ @@ -66,20 +74,15 @@ VDUP ---- 1110 1 b:1 q:1 0 .... rt:4 1011 . 0 e= :1 1 0000 \ vn=3D%vn_dp =20 VMSR_VMRS ---- 1110 111 l:1 reg:4 rt:4 1010 0001 0000 -VMOV_single ---- 1110 000 l:1 .... rt:4 1010 . 001 0000 \ - vn=3D%vn_sp +VMOV_single ---- 1110 000 l:1 .... rt:4 1010 . 001 0000 vn=3D%vn_sp =20 -VMOV_64_sp ---- 1100 010 op:1 rt2:4 rt:4 1010 00.1 .... \ - vm=3D%vm_sp -VMOV_64_dp ---- 1100 010 op:1 rt2:4 rt:4 1011 00.1 .... \ - vm=3D%vm_dp +VMOV_64_sp ---- 1100 010 op:1 rt2:4 rt:4 1010 00.1 .... vm=3D%vm_sp +VMOV_64_dp ---- 1100 010 op:1 rt2:4 rt:4 1011 00.1 .... vm=3D%vm_dp =20 # Note that the half-precision variants of VLDR and VSTR are # not part of this decodetree at all because they have bits [9:8] =3D=3D 0= b01 -VLDR_VSTR_sp ---- 1101 u:1 .0 l:1 rn:4 .... 1010 imm:8 \ - vd=3D%vd_sp -VLDR_VSTR_dp ---- 1101 u:1 .0 l:1 rn:4 .... 1011 imm:8 \ - vd=3D%vd_dp +VLDR_VSTR_sp ---- 1101 u:1 .0 l:1 rn:4 .... 1010 imm:8 vd=3D%vd_sp +VLDR_VSTR_dp ---- 1101 u:1 .0 l:1 rn:4 .... 1011 imm:8 vd=3D%vd_dp =20 # We split the load/store multiple up into two patterns to avoid # overlap with other insns in the "Advanced SIMD load/store and 64-bit mov= e" @@ -100,50 +103,32 @@ VLDM_VSTM_dp ---- 1101 0.1 l:1 rn:4 .... 1011 imm:8 \ vd=3D%vd_dp p=3D1 u=3D0 w=3D1 =20 # 3-register VFP data-processing; bits [23,21:20,6] identify the operation. -VMLA_sp ---- 1110 0.00 .... .... 1010 .0.0 .... \ - vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp -VMLA_dp ---- 1110 0.00 .... .... 1011 .0.0 .... \ - vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp +VMLA_sp ---- 1110 0.00 .... .... 1010 .0.0 .... @vfp_dnm_s +VMLA_dp ---- 1110 0.00 .... .... 1011 .0.0 .... @vfp_dnm_d =20 -VMLS_sp ---- 1110 0.00 .... .... 1010 .1.0 .... \ - vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp -VMLS_dp ---- 1110 0.00 .... .... 1011 .1.0 .... \ - vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp +VMLS_sp ---- 1110 0.00 .... .... 1010 .1.0 .... @vfp_dnm_s +VMLS_dp ---- 1110 0.00 .... .... 1011 .1.0 .... @vfp_dnm_d =20 -VNMLS_sp ---- 1110 0.01 .... .... 1010 .0.0 .... \ - vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp -VNMLS_dp ---- 1110 0.01 .... .... 1011 .0.0 .... \ - vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp +VNMLS_sp ---- 1110 0.01 .... .... 1010 .0.0 .... @vfp_dnm_s +VNMLS_dp ---- 1110 0.01 .... .... 1011 .0.0 .... @vfp_dnm_d =20 -VNMLA_sp ---- 1110 0.01 .... .... 1010 .1.0 .... \ - vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp -VNMLA_dp ---- 1110 0.01 .... .... 1011 .1.0 .... \ - vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp +VNMLA_sp ---- 1110 0.01 .... .... 1010 .1.0 .... @vfp_dnm_s +VNMLA_dp ---- 1110 0.01 .... .... 1011 .1.0 .... @vfp_dnm_d =20 -VMUL_sp ---- 1110 0.10 .... .... 1010 .0.0 .... \ - vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp -VMUL_dp ---- 1110 0.10 .... .... 1011 .0.0 .... \ - vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp +VMUL_sp ---- 1110 0.10 .... .... 1010 .0.0 .... @vfp_dnm_s +VMUL_dp ---- 1110 0.10 .... .... 1011 .0.0 .... @vfp_dnm_d =20 -VNMUL_sp ---- 1110 0.10 .... .... 1010 .1.0 .... \ - vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp -VNMUL_dp ---- 1110 0.10 .... .... 1011 .1.0 .... \ - vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp +VNMUL_sp ---- 1110 0.10 .... .... 1010 .1.0 .... @vfp_dnm_s +VNMUL_dp ---- 1110 0.10 .... .... 1011 .1.0 .... @vfp_dnm_d =20 -VADD_sp ---- 1110 0.11 .... .... 1010 .0.0 .... \ - vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp -VADD_dp ---- 1110 0.11 .... .... 1011 .0.0 .... \ - vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp +VADD_sp ---- 1110 0.11 .... .... 1010 .0.0 .... @vfp_dnm_s +VADD_dp ---- 1110 0.11 .... .... 1011 .0.0 .... @vfp_dnm_d =20 -VSUB_sp ---- 1110 0.11 .... .... 1010 .1.0 .... \ - vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp -VSUB_dp ---- 1110 0.11 .... .... 1011 .1.0 .... \ - vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp +VSUB_sp ---- 1110 0.11 .... .... 1010 .1.0 .... @vfp_dnm_s +VSUB_dp ---- 1110 0.11 .... .... 1011 .1.0 .... @vfp_dnm_d =20 -VDIV_sp ---- 1110 1.00 .... .... 1010 .0.0 .... \ - vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp -VDIV_dp ---- 1110 1.00 .... .... 1011 .0.0 .... \ - vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp +VDIV_sp ---- 1110 1.00 .... .... 1010 .0.0 .... @vfp_dnm_s +VDIV_dp ---- 1110 1.00 .... .... 1011 .0.0 .... @vfp_dnm_d =20 VFM_sp ---- 1110 1.01 .... .... 1010 . o2:1 . 0 .... \ vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp o1=3D1 @@ -159,25 +144,17 @@ VMOV_imm_sp ---- 1110 1.11 .... .... 1010 0000 .... \ VMOV_imm_dp ---- 1110 1.11 .... .... 1011 0000 .... \ vd=3D%vd_dp imm=3D%vmov_imm =20 -VMOV_reg_sp ---- 1110 1.11 0000 .... 1010 01.0 .... \ - vd=3D%vd_sp vm=3D%vm_sp -VMOV_reg_dp ---- 1110 1.11 0000 .... 1011 01.0 .... \ - vd=3D%vd_dp vm=3D%vm_dp +VMOV_reg_sp ---- 1110 1.11 0000 .... 1010 01.0 .... @vfp_dm_ss +VMOV_reg_dp ---- 1110 1.11 0000 .... 1011 01.0 .... @vfp_dm_dd =20 -VABS_sp ---- 1110 1.11 0000 .... 1010 11.0 .... \ - vd=3D%vd_sp vm=3D%vm_sp -VABS_dp ---- 1110 1.11 0000 .... 1011 11.0 .... \ - vd=3D%vd_dp vm=3D%vm_dp +VABS_sp ---- 1110 1.11 0000 .... 1010 11.0 .... @vfp_dm_ss +VABS_dp ---- 1110 1.11 0000 .... 1011 11.0 .... @vfp_dm_dd =20 -VNEG_sp ---- 1110 1.11 0001 .... 1010 01.0 .... \ - vd=3D%vd_sp vm=3D%vm_sp -VNEG_dp ---- 1110 1.11 0001 .... 1011 01.0 .... \ - vd=3D%vd_dp vm=3D%vm_dp +VNEG_sp ---- 1110 1.11 0001 .... 1010 01.0 .... @vfp_dm_ss +VNEG_dp ---- 1110 1.11 0001 .... 1011 01.0 .... @vfp_dm_dd =20 -VSQRT_sp ---- 1110 1.11 0001 .... 1010 11.0 .... \ - vd=3D%vd_sp vm=3D%vm_sp -VSQRT_dp ---- 1110 1.11 0001 .... 1011 11.0 .... \ - vd=3D%vd_dp vm=3D%vm_dp +VSQRT_sp ---- 1110 1.11 0001 .... 1010 11.0 .... @vfp_dm_ss +VSQRT_dp ---- 1110 1.11 0001 .... 1011 11.0 .... @vfp_dm_dd =20 VCMP_sp ---- 1110 1.11 010 z:1 .... 1010 e:1 1.0 .... \ vd=3D%vd_sp vm=3D%vm_sp @@ -190,32 +167,26 @@ VCVT_f32_f16 ---- 1110 1.11 0010 .... 1010 t:1 1.0 ..= .. \ VCVT_f64_f16 ---- 1110 1.11 0010 .... 1011 t:1 1.0 .... \ vd=3D%vd_dp vm=3D%vm_sp =20 -# VCVTB and VCVTT to f16: Vd format is always vd_sp; Vm format depends on = size bit +# VCVTB and VCVTT to f16: Vd format is always vd_sp; +# Vm format depends on size bit VCVT_f16_f32 ---- 1110 1.11 0011 .... 1010 t:1 1.0 .... \ vd=3D%vd_sp vm=3D%vm_sp VCVT_f16_f64 ---- 1110 1.11 0011 .... 1011 t:1 1.0 .... \ vd=3D%vd_sp vm=3D%vm_dp =20 -VRINTR_sp ---- 1110 1.11 0110 .... 1010 01.0 .... \ - vd=3D%vd_sp vm=3D%vm_sp -VRINTR_dp ---- 1110 1.11 0110 .... 1011 01.0 .... \ - vd=3D%vd_dp vm=3D%vm_dp +VRINTR_sp ---- 1110 1.11 0110 .... 1010 01.0 .... @vfp_dm_ss +VRINTR_dp ---- 1110 1.11 0110 .... 1011 01.0 .... @vfp_dm_dd =20 -VRINTZ_sp ---- 1110 1.11 0110 .... 1010 11.0 .... \ - vd=3D%vd_sp vm=3D%vm_sp -VRINTZ_dp ---- 1110 1.11 0110 .... 1011 11.0 .... \ - vd=3D%vd_dp vm=3D%vm_dp +VRINTZ_sp ---- 1110 1.11 0110 .... 1010 11.0 .... @vfp_dm_ss +VRINTZ_dp ---- 1110 1.11 0110 .... 1011 11.0 .... @vfp_dm_dd =20 -VRINTX_sp ---- 1110 1.11 0111 .... 1010 01.0 .... \ - vd=3D%vd_sp vm=3D%vm_sp -VRINTX_dp ---- 1110 1.11 0111 .... 1011 01.0 .... \ - vd=3D%vd_dp vm=3D%vm_dp +VRINTX_sp ---- 1110 1.11 0111 .... 1010 01.0 .... @vfp_dm_ss +VRINTX_dp ---- 1110 1.11 0111 .... 1011 01.0 .... @vfp_dm_dd =20 -# VCVT between single and double: Vm precision depends on size; Vd is its = reverse -VCVT_sp ---- 1110 1.11 0111 .... 1010 11.0 .... \ - vd=3D%vd_dp vm=3D%vm_sp -VCVT_dp ---- 1110 1.11 0111 .... 1011 11.0 .... \ - vd=3D%vd_sp vm=3D%vm_dp +# VCVT between single and double: +# Vm precision depends on size; Vd is its reverse +VCVT_sp ---- 1110 1.11 0111 .... 1010 11.0 .... @vfp_dm_ds +VCVT_dp ---- 1110 1.11 0111 .... 1011 11.0 .... @vfp_dm_sd =20 # VCVT from integer to floating point: Vm always single; Vd depends on size VCVT_int_sp ---- 1110 1.11 1000 .... 1010 s:1 1.0 .... \ @@ -224,8 +195,7 @@ VCVT_int_dp ---- 1110 1.11 1000 .... 1011 s:1 1.0 ....= \ vd=3D%vd_dp vm=3D%vm_sp =20 # VJCVT is always dp to sp -VJCVT ---- 1110 1.11 1001 .... 1011 11.0 .... \ - vd=3D%vd_sp vm=3D%vm_dp +VJCVT ---- 1110 1.11 1001 .... 1011 11.0 .... @vfp_dm_sd =20 # VCVT between floating-point and fixed-point. The immediate value # is in the same format as a Vm single-precision register number. --=20 2.20.1 From nobody Fri Mar 29 00:38:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581704603296855.6950343272621; Fri, 14 Feb 2020 10:23:23 -0800 (PST) Received: from localhost ([::1]:43724 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2fcY-0002Uz-5Z for importer@patchew.org; Fri, 14 Feb 2020 13:23:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60975) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2fVc-0004jg-Hn for qemu-devel@nongnu.org; Fri, 14 Feb 2020 13:16:13 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j2fVb-0000M1-71 for qemu-devel@nongnu.org; Fri, 14 Feb 2020 13:16:12 -0500 Received: from mail-pf1-x442.google.com ([2607:f8b0:4864:20::442]:46225) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j2fVb-0000L1-18 for qemu-devel@nongnu.org; Fri, 14 Feb 2020 13:16:11 -0500 Received: by mail-pf1-x442.google.com with SMTP id k29so5238023pfp.13 for ; Fri, 14 Feb 2020 10:16:10 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id i3sm7525123pfg.94.2020.02.14.10.16.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Feb 2020 10:16:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=08YWOW4uPN/K//8Sv/iAQdt6yoHtAxwQIa1pxOQkXxw=; b=CmrUFjhRgBmeKXvH7NHnFbQpBEyRRrlSu7RRgr3lzAklwKujje0eh+AYgMgXpK6m4N TVLWc9TCl7MoM3pCMiJdrqqxOqQm44RpTr2wTO9iOD9gFB3o4eWjrWZxCGo1rFoY845U 9lWE8hrarjlIhuEKpHXDjqhRUNs2Rzqv86OLZYRMUph/vabVocw7b+PDYLeEhVZYg9cp BMVOi5HW5+IW/nLMeGMhZMSRx5thMi/Cw1w5mKg2WpXDHrNuKj+K5Zpl8sfBlJpvYId1 9jVeP/jQIZ3HUY13+F2IMHAoTwaGJ4UOX8lioPP9A3s1NyEPtv/jBtVjK147BzLISkZQ DYHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=08YWOW4uPN/K//8Sv/iAQdt6yoHtAxwQIa1pxOQkXxw=; b=iiAWhF/s9T5s/bqEjXPZfbB6smzYMOIqwfkfL6mNlhpVYxHAMRv9KWloaRxBnW6JIo 2ezEcNhFwu85JFxYem1PoXvr5HBdqyaU2vk7lQlHf8iKA/cqDEtHVg5u9KeuDdFwbOSD aHjLqMFaLEdGepog0nm+omM1Jjk9D2lFoDYtOPB7lFddX0J2SvnWIZpQa8eoHzy+nZ0D jih3VqA59W4yL78WlLXyn79qmeAqRQxdIa/Nd467F6dHK/9/DiVwpwq1MuEnBpLenqRR mTORytGlWyJA5jM8nzCHVXgDUAAV9VqmpGSMwLT6NcF2pqV47QY27UUr4kG2i9OiOltr qz7g== X-Gm-Message-State: APjAAAVDCY7fY+m5hR4FiO4qElDMFBvBkPgWak2Drw/Fo3XuGzlBxREO Nyn5FLYEfOgzEM4QfpDitsLCAfxyH/U= X-Google-Smtp-Source: APXvYqyjCEfys8bdeZTdZ9W4WCUhcOq/eaMvVeUl90poWPjK0vBSR9M5n70oPGLiQuS0YOLDyNPcXw== X-Received: by 2002:a63:7f5c:: with SMTP id p28mr4977435pgn.212.1581704169483; Fri, 14 Feb 2020 10:16:09 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 18/19] target/arm: Split VFM decode Date: Fri, 14 Feb 2020 10:15:46 -0800 Message-Id: <20200214181547.21408-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200214181547.21408-1-richard.henderson@linaro.org> References: <20200214181547.21408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Passing the raw o1 and o2 fields from the manual is less instructive than it might be. Do the full decode and let the trans_* functions pass in booleans to a helper. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/vfp.decode | 17 +++++------ target/arm/translate-vfp.inc.c | 52 ++++++++++++++++++++++++++++++---- 2 files changed, 55 insertions(+), 14 deletions(-) diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode index 4f294f88be..5fd70f975a 100644 --- a/target/arm/vfp.decode +++ b/target/arm/vfp.decode @@ -130,14 +130,15 @@ VSUB_dp ---- 1110 0.11 .... .... 1011 .1.0 .... = @vfp_dnm_d VDIV_sp ---- 1110 1.00 .... .... 1010 .0.0 .... @vfp_dnm_s VDIV_dp ---- 1110 1.00 .... .... 1011 .0.0 .... @vfp_dnm_d =20 -VFM_sp ---- 1110 1.01 .... .... 1010 . o2:1 . 0 .... \ - vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp o1=3D1 -VFM_dp ---- 1110 1.01 .... .... 1011 . o2:1 . 0 .... \ - vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp o1=3D1 -VFM_sp ---- 1110 1.10 .... .... 1010 . o2:1 . 0 .... \ - vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp o1=3D2 -VFM_dp ---- 1110 1.10 .... .... 1011 . o2:1 . 0 .... \ - vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp o1=3D2 +VFMA_sp ---- 1110 1.10 .... .... 1010 .0. 0 .... @vfp_dnm_s +VFMS_sp ---- 1110 1.10 .... .... 1010 .1. 0 .... @vfp_dnm_s +VFNMA_sp ---- 1110 1.01 .... .... 1010 .0. 0 .... @vfp_dnm_s +VFNMS_sp ---- 1110 1.01 .... .... 1010 .1. 0 .... @vfp_dnm_s + +VFMA_dp ---- 1110 1.10 .... .... 1011 .0.0 .... @vfp_dnm_d +VFMS_dp ---- 1110 1.10 .... .... 1011 .1.0 .... @vfp_dnm_d +VFNMA_dp ---- 1110 1.01 .... .... 1011 .0.0 .... @vfp_dnm_d +VFNMS_dp ---- 1110 1.01 .... .... 1011 .1.0 .... @vfp_dnm_d =20 VMOV_imm_sp ---- 1110 1.11 .... .... 1010 0000 .... \ vd=3D%vd_sp imm=3D%vmov_imm diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 8f2b97e0e7..b5f3feaf8d 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -1784,7 +1784,7 @@ static bool trans_VDIV_dp(DisasContext *s, arg_VDIV_d= p *a) return do_vfp_3op_dp(s, gen_helper_vfp_divd, a->vd, a->vn, a->vm, fals= e); } =20 -static bool trans_VFM_sp(DisasContext *s, arg_VFM_sp *a) +static bool do_vfm_sp(DisasContext *s, arg_VFMA_sp *a, bool neg_n, bool ne= g_d) { /* * VFNMA : fd =3D muladd(-fd, fn, fm) @@ -1823,12 +1823,12 @@ static bool trans_VFM_sp(DisasContext *s, arg_VFM_s= p *a) =20 neon_load_reg32(vn, a->vn); neon_load_reg32(vm, a->vm); - if (a->o2) { + if (neg_n) { /* VFNMS, VFMS */ gen_helper_vfp_negs(vn, vn); } neon_load_reg32(vd, a->vd); - if (a->o1 & 1) { + if (neg_d) { /* VFNMA, VFNMS */ gen_helper_vfp_negs(vd, vd); } @@ -1844,7 +1844,27 @@ static bool trans_VFM_sp(DisasContext *s, arg_VFM_sp= *a) return true; } =20 -static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp *a) +static bool trans_VFMA_sp(DisasContext *s, arg_VFMA_sp *a) +{ + return do_vfm_sp(s, a, false, false); +} + +static bool trans_VFMS_sp(DisasContext *s, arg_VFMS_sp *a) +{ + return do_vfm_sp(s, a, true, false); +} + +static bool trans_VFNMA_sp(DisasContext *s, arg_VFNMA_sp *a) +{ + return do_vfm_sp(s, a, false, true); +} + +static bool trans_VFNMS_sp(DisasContext *s, arg_VFNMS_sp *a) +{ + return do_vfm_sp(s, a, true, true); +} + +static bool do_vfm_dp(DisasContext *s, arg_VFMA_dp *a, bool neg_n, bool ne= g_d) { /* * VFNMA : fd =3D muladd(-fd, fn, fm) @@ -1893,12 +1913,12 @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_d= p *a) =20 neon_load_reg64(vn, a->vn); neon_load_reg64(vm, a->vm); - if (a->o2) { + if (neg_n) { /* VFNMS, VFMS */ gen_helper_vfp_negd(vn, vn); } neon_load_reg64(vd, a->vd); - if (a->o1 & 1) { + if (neg_d) { /* VFNMA, VFNMS */ gen_helper_vfp_negd(vd, vd); } @@ -1914,6 +1934,26 @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp= *a) return true; } =20 +static bool trans_VFMA_dp(DisasContext *s, arg_VFMA_dp *a) +{ + return do_vfm_dp(s, a, false, false); +} + +static bool trans_VFMS_dp(DisasContext *s, arg_VFMS_dp *a) +{ + return do_vfm_dp(s, a, true, false); +} + +static bool trans_VFNMA_dp(DisasContext *s, arg_VFNMA_dp *a) +{ + return do_vfm_dp(s, a, false, true); +} + +static bool trans_VFNMS_dp(DisasContext *s, arg_VFNMS_dp *a) +{ + return do_vfm_dp(s, a, true, true); +} + static bool trans_VMOV_imm_sp(DisasContext *s, arg_VMOV_imm_sp *a) { uint32_t delta_d =3D 0; --=20 2.20.1 From nobody Fri Mar 29 00:38:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581704878453571.1196899588037; Fri, 14 Feb 2020 10:27:58 -0800 (PST) Received: from localhost ([::1]:43834 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2fgz-0000v6-9A for importer@patchew.org; Fri, 14 Feb 2020 13:27:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60990) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2fVd-0004m8-GJ for qemu-devel@nongnu.org; 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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id i3sm7525123pfg.94.2020.02.14.10.16.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Feb 2020 10:16:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pMw3WexDwdJHFaht64LuoLlVbRzrqioLE5XZ9OBOKYc=; b=OpOZLTFyEqK6z0NFplV4tDRaB/hXh8fwpOHTwR2ICSTFmNcXFYQ1/wuLXfZsyCm+b5 Z4fswPZ12UOB9MzsZ7brFasvCSl9VZMRYUWoM1eaV5PhqTWaKYYw8nkPCtZC1f2jGvtT ruQelYdHp5sstGVUnm46Dd+FG516ZEq6cfxFIH2UqwnRWE3LKG5HW18Q2w6q+QVMzBMc tOgRpxFvsk+y/YI0xjjezUTrgm0xcJDffLt236x4Vwi7E/++spbVeo0ad+WQokVu2NLZ fxzlW4JOK3lpn1EjCtsLikQ3OAE71XV7tKqHXxZpyUukL9XFQ4LNtnoL8VLpHDeczsCC 3fKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pMw3WexDwdJHFaht64LuoLlVbRzrqioLE5XZ9OBOKYc=; b=iiothwhOTDc+fSf+RUQ0fSgrZp75e4oWdicAxA5ZRLqolXt8Q+rh61VZTyxEtAmb57 d3QpnbOLjGYtZY9Q4FcGbFkdWQCjo8ky/2mcuF8M3g/jjDSINfVHaF9eYk3qGCWN/irw luBorsvt/8e1N2ya7oNz5QXQahSXACCLMIgPw6KuYyTW2qpuFWnLWHkQxPYmckQf5w9T 6LAJNUglJy+Y89VAPszv2Vvby1bjwrMdqFby3Cgo4Kdb7cuFhCAq7KEtrzZYcCMFEfQ4 Li8Cbbt0OJOk5kxgrQYltnXXXL5dNQI/6ODy+pRtxpmJL0xTMdUlr/haNaxC8lxOwKwV KQXQ== X-Gm-Message-State: APjAAAWpBJPV1Cs5YiFljjvbBCcWi++AiCFEDCXBWS4qwhB5uFE1QdpD BB9kr2hynenK/63B7bzkpVRKNQ5rUjo= X-Google-Smtp-Source: APXvYqyrf2/+wOY4I0ry0Rp1dmhyQulHacIJKGSySeoykNJZJok0ImNjxIh8iGot5nyOB/te48S4eA== X-Received: by 2002:a63:5c10:: with SMTP id q16mr4923809pgb.35.1581704170679; Fri, 14 Feb 2020 10:16:10 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 19/19] target/arm: Split VMINMAXNM decode Date: Fri, 14 Feb 2020 10:15:47 -0800 Message-Id: <20200214181547.21408-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200214181547.21408-1-richard.henderson@linaro.org> References: <20200214181547.21408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Passing the raw op field from the manual is less instructive than it might be. Do the full decode and use the existing helpers to perform the expansion. Since these are v8 insns, VECLEN+VECSTRIDE are already RES0. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/vfp-uncond.decode | 12 ++-- target/arm/translate-vfp.inc.c | 109 +++++++++++---------------------- 2 files changed, 44 insertions(+), 77 deletions(-) diff --git a/target/arm/vfp-uncond.decode b/target/arm/vfp-uncond.decode index 5af1f2ee66..34ca164266 100644 --- a/target/arm/vfp-uncond.decode +++ b/target/arm/vfp-uncond.decode @@ -41,15 +41,19 @@ %vd_dp 22:1 12:4 %vd_sp 12:4 22:1 =20 +@vfp_dnm_s ................................ vm=3D%vm_sp vn=3D%vn_sp vd= =3D%vd_sp +@vfp_dnm_d ................................ vm=3D%vm_dp vn=3D%vn_dp vd= =3D%vd_dp + VSEL 1111 1110 0. cc:2 .... .... 1010 .0.0 .... \ vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp dp=3D0 VSEL 1111 1110 0. cc:2 .... .... 1011 .0.0 .... \ vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp dp=3D1 =20 -VMINMAXNM 1111 1110 1.00 .... .... 1010 . op:1 .0 .... \ - vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp dp=3D0 -VMINMAXNM 1111 1110 1.00 .... .... 1011 . op:1 .0 .... \ - vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp dp=3D1 +VMAXNM_sp 1111 1110 1.00 .... .... 1010 .0.0 .... @vfp_dnm_s +VMINNM_sp 1111 1110 1.00 .... .... 1010 .1.0 .... @vfp_dnm_s + +VMAXNM_dp 1111 1110 1.00 .... .... 1011 .0.0 .... @vfp_dnm_d +VMINNM_dp 1111 1110 1.00 .... .... 1011 .1.0 .... @vfp_dnm_d =20 VRINT 1111 1110 1.11 10 rm:2 .... 1010 01.0 .... \ vm=3D%vm_sp vd=3D%vd_sp dp=3D0 diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index b5f3feaf8d..2cf85e73cf 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -322,79 +322,6 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) return true; } =20 -static bool trans_VMINMAXNM(DisasContext *s, arg_VMINMAXNM *a) -{ - uint32_t rd, rn, rm; - bool dp =3D a->dp; - bool vmin =3D a->op; - TCGv_ptr fpst; - - if (!dc_isar_feature(aa32_vminmaxnm, s)) { - return false; - } - - if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist */ - if (dp && !dc_isar_feature(aa32_simd_r32, s) && - ((a->vm | a->vn | a->vd) & 0x10)) { - return false; - } - - rd =3D a->vd; - rn =3D a->vn; - rm =3D a->vm; - - if (!vfp_access_check(s)) { - return true; - } - - fpst =3D get_fpstatus_ptr(0); - - if (dp) { - TCGv_i64 frn, frm, dest; - - frn =3D tcg_temp_new_i64(); - frm =3D tcg_temp_new_i64(); - dest =3D tcg_temp_new_i64(); - - neon_load_reg64(frn, rn); - neon_load_reg64(frm, rm); - if (vmin) { - gen_helper_vfp_minnumd(dest, frn, frm, fpst); - } else { - gen_helper_vfp_maxnumd(dest, frn, frm, fpst); - } - neon_store_reg64(dest, rd); - tcg_temp_free_i64(frn); - tcg_temp_free_i64(frm); - tcg_temp_free_i64(dest); - } else { - TCGv_i32 frn, frm, dest; - - frn =3D tcg_temp_new_i32(); - frm =3D tcg_temp_new_i32(); - dest =3D tcg_temp_new_i32(); - - neon_load_reg32(frn, rn); - neon_load_reg32(frm, rm); - if (vmin) { - gen_helper_vfp_minnums(dest, frn, frm, fpst); - } else { - gen_helper_vfp_maxnums(dest, frn, frm, fpst); - } - neon_store_reg32(dest, rd); - tcg_temp_free_i32(frn); - tcg_temp_free_i32(frm); - tcg_temp_free_i32(dest); - } - - tcg_temp_free_ptr(fpst); - return true; -} - /* * Table for converting the most common AArch32 encoding of * rounding mode to arm_fprounding order (which matches the @@ -1784,6 +1711,42 @@ static bool trans_VDIV_dp(DisasContext *s, arg_VDIV_= dp *a) return do_vfp_3op_dp(s, gen_helper_vfp_divd, a->vd, a->vn, a->vm, fals= e); } =20 +static bool trans_VMINNM_sp(DisasContext *s, arg_VMINNM_sp *a) +{ + if (!dc_isar_feature(aa32_vminmaxnm, s)) { + return false; + } + return do_vfp_3op_sp(s, gen_helper_vfp_minnums, + a->vd, a->vn, a->vm, false); +} + +static bool trans_VMAXNM_sp(DisasContext *s, arg_VMAXNM_sp *a) +{ + if (!dc_isar_feature(aa32_vminmaxnm, s)) { + return false; + } + return do_vfp_3op_sp(s, gen_helper_vfp_maxnums, + a->vd, a->vn, a->vm, false); +} + +static bool trans_VMINNM_dp(DisasContext *s, arg_VMINNM_dp *a) +{ + if (!dc_isar_feature(aa32_vminmaxnm, s)) { + return false; + } + return do_vfp_3op_dp(s, gen_helper_vfp_minnumd, + a->vd, a->vn, a->vm, false); +} + +static bool trans_VMAXNM_dp(DisasContext *s, arg_VMAXNM_dp *a) +{ + if (!dc_isar_feature(aa32_vminmaxnm, s)) { + return false; + } + return do_vfp_3op_dp(s, gen_helper_vfp_maxnumd, + a->vd, a->vn, a->vm, false); +} + static bool do_vfm_sp(DisasContext *s, arg_VFMA_sp *a, bool neg_n, bool ne= g_d) { /* --=20 2.20.1