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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id v8sm8001857wrw.2.2020.02.14.09.51.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Feb 2020 09:51:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4BLXsVcN28YFgzh7RunR4by8doFHHVtIkmiy7Jly1NU=; b=bJq6wSO64nQ7655iHrQy8uQ33zF92z6mllFOsd9mCZz9w/YAosZY/9qPsG69XByf4u ZcANLz6nOXrvhQJi4Ybn0eQTHvzbNrNUS8Qf3srvCqzUfQ96ycljrzhaalZYE3CKdpcr BDuP5yjRB9ClLPtg/a7/yseWhUV3a4vRBun+5dT/4Vm5lQLybz6KOZ4yps4GI82zDs22 qojNNb4P3LxD69VBsrF4G1xF2dldKCKJ396BUQF/JMkTSRBIZMiwvA8+fsDpMp/RiLuX z+uN9q/Y2105JXkzLHHyoEU/fneulHwbP8nsDSgnebVUQ1BAXfvpKEahMUAr2Z1DNgkt GZug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4BLXsVcN28YFgzh7RunR4by8doFHHVtIkmiy7Jly1NU=; b=qXu3+wDEH0a5fxem9WJd/zy9c8iuehUZLsp8YYT7GS/TPubytAn12DRcpb5RXwCZAh Tak849R983/0q6S81L5k+1zgILcKhvNnSPqZjPCozWk/Ndztxmf7KCBN/Oq0vBXVpIyH UVODNRgb3WWo9Goufdluob230N+BM9fkr6zlOfW37EZxwnylr1gXdyzXpiEdbovseWcU bpKy/5pLc5no4/JfZn2LOH5gIRJrjWj8Zn2hBT4tR/MYJsiCXgJYKmGI6wIhC6W/rTAt yi+gFHUoQJKloP+0OUYQT+yWxDorMg1UFQOMeF9YY9H8Ee9Sryd3tkYFQ+3FOqOJn4BO uuWg== X-Gm-Message-State: APjAAAWGrh3lKbQrXAv4LNOYunhyTgqM3ulnvwJndTsVWBm6Z/3O6cGY Bbp/RfnnHq0TWB/XermCHy58Qluymts= X-Google-Smtp-Source: APXvYqyAtnb4zGMsTJryfLntnFWOYcBV/xbFG14HBh7YCfI8bZDOSFdCgeWO3rOBAI6QaC0dtygT9w== X-Received: by 2002:adf:b64b:: with SMTP id i11mr5502856wre.58.1581702698797; Fri, 14 Feb 2020 09:51:38 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 14/21] target/arm: Implement ARMv8.4-PMU extension Date: Fri, 14 Feb 2020 17:51:09 +0000 Message-Id: <20200214175116.9164-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200214175116.9164-1-peter.maydell@linaro.org> References: <20200214175116.9164-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eric Auger , Aaron Lindsay , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The ARMv8.4-PMU extension adds: * one new required event, STALL * one new system register PMMIR_EL1 (There are also some more L1-cache related events, but since we don't implement any cache we don't provide these, in the same way we don't provide the base-PMUv3 cache events.) The STALL event "counts every attributable cycle on which no attributable instruction or operation was sent for execution on this PE". QEMU doesn't stall in this sense, so this is another always-reads-zero event. The PMMIR_EL1 register is a read-only register providing implementation-specific information about the PMU; currently it has only one field, SLOTS, which defines behaviour of the STALL_SLOT PMU event. Since QEMU doesn't implement the STALL_SLOT event, we can validly make the register read zero. Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell --- target/arm/cpu.h | 18 ++++++++++++++++++ target/arm/helper.c | 22 +++++++++++++++++++++- 2 files changed, 39 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e043932fcb1..cfa9fd6c1b9 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3519,6 +3519,13 @@ static inline bool isar_feature_aa32_pmu_8_1(const A= RMISARegisters *id) FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) !=3D 0xf; } =20 +static inline bool isar_feature_aa32_pmu_8_4(const ARMISARegisters *id) +{ + /* 0xf means "non-standard IMPDEF PMU" */ + return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >=3D 5 && + FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) !=3D 0xf; +} + /* * 64-bit feature tests via id registers. */ @@ -3704,6 +3711,12 @@ static inline bool isar_feature_aa64_pmu_8_1(const A= RMISARegisters *id) FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) !=3D 0xf; } =20 +static inline bool isar_feature_aa64_pmu_8_4(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >=3D 5 && + FIELD_EX32(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) !=3D 0xf; +} + /* * Feature tests for "does this exist in either 32-bit or 64-bit?" */ @@ -3722,6 +3735,11 @@ static inline bool isar_feature_any_pmu_8_1(const AR= MISARegisters *id) return isar_feature_aa64_pmu_8_1(id) || isar_feature_aa32_pmu_8_1(id); } =20 +static inline bool isar_feature_any_pmu_8_4(const ARMISARegisters *id) +{ + return isar_feature_aa64_pmu_8_4(id) || isar_feature_aa32_pmu_8_4(id); +} + /* * Forward to the above feature tests given an ARMCPU pointer. */ diff --git a/target/arm/helper.c b/target/arm/helper.c index aeb01617150..2feded1518c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1130,6 +1130,12 @@ static bool pmu_8_1_events_supported(CPUARMState *en= v) return cpu_isar_feature(any_pmu_8_1, env_archcpu(env)); } =20 +static bool pmu_8_4_events_supported(CPUARMState *env) +{ + /* For events which are supported in any v8.1 PMU */ + return cpu_isar_feature(any_pmu_8_4, env_archcpu(env)); +} + static uint64_t zero_event_get_count(CPUARMState *env) { /* For events which on QEMU never fire, so their count is always zero = */ @@ -1170,6 +1176,11 @@ static const pm_event pm_events[] =3D { .get_count =3D zero_event_get_count, .ns_per_count =3D zero_event_ns_per, }, + { .number =3D 0x03c, /* STALL */ + .supported =3D pmu_8_4_events_supported, + .get_count =3D zero_event_get_count, + .ns_per_count =3D zero_event_ns_per, + }, }; =20 /* @@ -1178,7 +1189,7 @@ static const pm_event pm_events[] =3D { * should first be updated to something sparse instead of the current * supported_event_map[] array. */ -#define MAX_EVENT_ID 0x24 +#define MAX_EVENT_ID 0x3c #define UNSUPPORTED_EVENT UINT16_MAX static uint16_t supported_event_map[MAX_EVENT_ID + 1]; =20 @@ -6414,6 +6425,15 @@ static void define_pmu_regs(ARMCPU *cpu) }; define_arm_cp_regs(cpu, v81_pmu_regs); } + if (cpu_isar_feature(any_pmu_8_4, cpu)) { + static const ARMCPRegInfo v84_pmmir =3D { + .name =3D "PMMIR_EL1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D 6, + .access =3D PL1_R, .accessfn =3D pmreg_access, .type =3D ARM_C= P_CONST, + .resetvalue =3D 0 + }; + define_one_arm_cp_reg(cpu, &v84_pmmir); + } } =20 /* We don't know until after realize whether there's a GICv3 --=20 2.20.1