From nobody Mon May 6 22:28:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581702761065105.96169858362157; Fri, 14 Feb 2020 09:52:41 -0800 (PST) Received: from localhost ([::1]:42780 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2f8o-0007Zf-Lg for importer@patchew.org; Fri, 14 Feb 2020 12:52:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55787) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2f7b-0005lN-5t for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:24 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j2f7Z-0000bg-RG for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:23 -0500 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]:53204) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j2f7Z-0000aw-KL for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:21 -0500 Received: by mail-wm1-x344.google.com with SMTP id p9so10847919wmc.2 for ; Fri, 14 Feb 2020 09:51:21 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id v8sm8001857wrw.2.2020.02.14.09.51.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Feb 2020 09:51:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+amQqSMMNkjYspkyG4VDVSbpi69YyKGpyIpBbA8qu7c=; b=MpLiOOJ1BXICWBv+uoW2t/a4hnWMq0va6NKe2ItQv2WsqsmX3HygsamEdfO68p7LoK seAG6vq9+G2U7G7AEIy5J4AsTkP7L8bWdkOm0nIyyaK4wSo5/DJJLcqFxU/+Gm2RoEAm AEGNMnL2KW9gtd2M6PX35hYSlnDXyM23m5PvVdMW+FEth59kUQ2d1iWu4/yjFytoxWIC bR4KftKyC1z95ZF4Kwm+beHVlR83i2lzdmt7KdgD6WkxGTWv0k4UERYOZGZntQDuTaqX 315w1QVBESHyCvp9O5C1tDKAfmI9M2wKyuFELKUeM0yDJxhzK+wi5rv8WYAPOG2bM0wb BcnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+amQqSMMNkjYspkyG4VDVSbpi69YyKGpyIpBbA8qu7c=; b=HQpl5LoTN4WEAJt5VWKLo6ble8FJk1sW2uoHbhzXEjYigv5fwhiSps3CHFJe548UAo L2yKqQsXsc6sJxwrZ0b2dip7epIvNUMw8LiGfMlUgl/CZMFYdi51KDWOgWdBzq4yg9Rq 9xaTIrSPYaw19hbO8nghOxEvLDhXDuBAWikdnneMNdJMuiYdqEriBbtEoMOTzLmfq4Og 2vfq1xcdNSOUY3w0EqL4FVoquHBSi5Qr4VQHeHzQhEFP6VNBxcKB4brOKZ7yVm37S5kr aR/c0647h5Ld6vOCPyG8T0RbmIDFxI89kSHHVM+hslLYDGLH0ekOKBxBsh5y3m3GYlpR CTBg== X-Gm-Message-State: APjAAAWWQfFJwkuyj9DT1lZR9PtNLZvlF2qL6HSWx4fWAreYC/013F6W /jfFEGe13m+swfkLTg97Nh18Ew== X-Google-Smtp-Source: APXvYqz27YlUkdNbQYP9Fk1xyivQKu8a5RsOzhZcXohgXUjSWIrAUy/fSOWfg846vV1x8E6r81TruQ== X-Received: by 2002:a1c:2342:: with SMTP id j63mr6030010wmj.160.1581702680538; Fri, 14 Feb 2020 09:51:20 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 01/21] target/arm: Add _aa32_ to isar_feature functions testing 32-bit ID registers Date: Fri, 14 Feb 2020 17:50:56 +0000 Message-Id: <20200214175116.9164-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200214175116.9164-1-peter.maydell@linaro.org> References: <20200214175116.9164-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eric Auger , Aaron Lindsay , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Enforce a convention that an isar_feature function that tests a 32-bit ID register always has _aa32_ in its name, and one that tests a 64-bit ID register always has _aa64_ in its name. We already follow this except for three cases: thumb_div, arm_div and jazelle, which all need _aa32_ adding. (As noted in the comment, isar_feature_aa32_fp16_arith() is an exception in that it currently tests ID_AA64PFR0_EL1, but will switch to MVFR1 once we've properly implemented FP16 for AArch32.) Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell --- v1->v2: fixed up new use of isar_feature_jazelle() in aarch32_cpsr_valid_mask() --- target/arm/cpu.h | 13 ++++++++++--- target/arm/internals.h | 2 +- linux-user/elfload.c | 4 ++-- target/arm/cpu.c | 6 ++++-- target/arm/helper.c | 2 +- target/arm/translate.c | 6 +++--- 6 files changed, 21 insertions(+), 12 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e943ffe8a9a..37d40e57901 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3324,20 +3324,27 @@ static inline uint64_t *aa64_vfp_qreg(CPUARMState *= env, unsigned regno) /* Shared between translate-sve.c and sve_helper.c. */ extern const uint64_t pred_esz_masks[4]; =20 +/* + * Naming convention for isar_feature functions: + * Functions which test 32-bit ID registers should have _aa32_ in + * their name. Functions which test 64-bit ID registers should have + * _aa64_ in their name. + */ + /* * 32-bit feature tests via id registers. */ -static inline bool isar_feature_thumb_div(const ARMISARegisters *id) +static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id) { return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) !=3D 0; } =20 -static inline bool isar_feature_arm_div(const ARMISARegisters *id) +static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id) { return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1; } =20 -static inline bool isar_feature_jazelle(const ARMISARegisters *id) +static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id) { return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) !=3D 0; } diff --git a/target/arm/internals.h b/target/arm/internals.h index 58c4d707c5d..052449b4826 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1091,7 +1091,7 @@ static inline uint32_t aarch32_cpsr_valid_mask(uint64= _t features, if ((features >> ARM_FEATURE_THUMB2) & 1) { valid |=3D CPSR_IT; } - if (isar_feature_jazelle(id)) { + if (isar_feature_aa32_jazelle(id)) { valid |=3D CPSR_J; } if (isar_feature_aa32_pan(id)) { diff --git a/linux-user/elfload.c b/linux-user/elfload.c index f3080a16358..b1a895f24ce 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -475,8 +475,8 @@ static uint32_t get_elf_hwcap(void) GET_FEATURE(ARM_FEATURE_VFP3, ARM_HWCAP_ARM_VFPv3); GET_FEATURE(ARM_FEATURE_V6K, ARM_HWCAP_ARM_TLS); GET_FEATURE(ARM_FEATURE_VFP4, ARM_HWCAP_ARM_VFPv4); - GET_FEATURE_ID(arm_div, ARM_HWCAP_ARM_IDIVA); - GET_FEATURE_ID(thumb_div, ARM_HWCAP_ARM_IDIVT); + GET_FEATURE_ID(aa32_arm_div, ARM_HWCAP_ARM_IDIVA); + GET_FEATURE_ID(aa32_thumb_div, ARM_HWCAP_ARM_IDIVT); /* All QEMU's VFPv3 CPUs have 32 registers, see VFP_DREG in translate.= c. * Note that the ARM_HWCAP_ARM_VFPv3D16 bit is always the inverse of * ARM_HWCAP_ARM_VFPD32 (and so always clear for QEMU); it is unrelated diff --git a/target/arm/cpu.c b/target/arm/cpu.c index de733aceeb8..56f2ab865da 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1586,7 +1586,8 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) * Presence of EL2 itself is ARM_FEATURE_EL2, and of the * Security Extensions is ARM_FEATURE_EL3. */ - assert(!tcg_enabled() || no_aa32 || cpu_isar_feature(arm_div, cpu)= ); + assert(!tcg_enabled() || no_aa32 || + cpu_isar_feature(aa32_arm_div, cpu)); set_feature(env, ARM_FEATURE_LPAE); set_feature(env, ARM_FEATURE_V7); } @@ -1612,7 +1613,8 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) if (arm_feature(env, ARM_FEATURE_V6)) { set_feature(env, ARM_FEATURE_V5); if (!arm_feature(env, ARM_FEATURE_M)) { - assert(!tcg_enabled() || no_aa32 || cpu_isar_feature(jazelle, = cpu)); + assert(!tcg_enabled() || no_aa32 || + cpu_isar_feature(aa32_jazelle, cpu)); set_feature(env, ARM_FEATURE_AUXCR); } } diff --git a/target/arm/helper.c b/target/arm/helper.c index 366dbcf460d..eec3876610c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7396,7 +7396,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (arm_feature(env, ARM_FEATURE_LPAE)) { define_arm_cp_regs(cpu, lpae_cp_reginfo); } - if (cpu_isar_feature(jazelle, cpu)) { + if (cpu_isar_feature(aa32_jazelle, cpu)) { define_arm_cp_regs(cpu, jazelle_regs); } /* Slightly awkwardly, the OMAP and StrongARM cores need all of diff --git a/target/arm/translate.c b/target/arm/translate.c index 20f89ace2fd..93f028f256b 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -42,7 +42,7 @@ #define ENABLE_ARCH_5 arm_dc_feature(s, ARM_FEATURE_V5) /* currently all emulated v5 cores are also v5TE, so don't bother */ #define ENABLE_ARCH_5TE arm_dc_feature(s, ARM_FEATURE_V5) -#define ENABLE_ARCH_5J dc_isar_feature(jazelle, s) +#define ENABLE_ARCH_5J dc_isar_feature(aa32_jazelle, s) #define ENABLE_ARCH_6 arm_dc_feature(s, ARM_FEATURE_V6) #define ENABLE_ARCH_6K arm_dc_feature(s, ARM_FEATURE_V6K) #define ENABLE_ARCH_6T2 arm_dc_feature(s, ARM_FEATURE_THUMB2) @@ -9845,8 +9845,8 @@ static bool op_div(DisasContext *s, arg_rrr *a, bool = u) TCGv_i32 t1, t2; =20 if (s->thumb - ? !dc_isar_feature(thumb_div, s) - : !dc_isar_feature(arm_div, s)) { + ? !dc_isar_feature(aa32_thumb_div, s) + : !dc_isar_feature(aa32_arm_div, s)) { return false; } =20 --=20 2.20.1 From nobody Mon May 6 22:28:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581702854079966.1921515229801; Fri, 14 Feb 2020 09:54:14 -0800 (PST) Received: from localhost ([::1]:42838 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2fAJ-0003M0-Ve for importer@patchew.org; Fri, 14 Feb 2020 12:54:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55853) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2f7e-0005lr-D2 for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:28 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j2f7d-0000fN-1D for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:26 -0500 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:55173) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j2f7c-0000eT-QK for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:24 -0500 Received: by mail-wm1-x343.google.com with SMTP id g1so10828127wmh.4 for ; Fri, 14 Feb 2020 09:51:24 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id v8sm8001857wrw.2.2020.02.14.09.51.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Feb 2020 09:51:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Rq8pejBQpyfpBvg4MHykyjE8mwu9sHhOGcsrOcoZVak=; b=RrmcKadGWzlb3rsABzU8q5x+n3s+OuOkKhA9Msf3q/bLe24/66mDf8gJJS4szkY6rI kcmHf0LEuKfSRINe2qidCVI7ShBK1cPGbybRHIrnf9Gu5lHbaDS3h7qXf4fpNahUebBM O+c/EdqgyMquekt3WSf5P7VD3ZgDVoiSFRiD2ftXdqIvxeuPKy+vBt6z0112g7MwJnv9 UqJxIwyEobtqeLQhZLQgze1QGr91YwNzFwl2lT+Gs3ikWftuqzZz6qmvIU4ttYHoyUJe SaHhbKRlgVP6hLu7KNPSRcPV2HUjHykNNZ8MKcPpCXOf5sMpTK3QA/w6R8zhyghRlppq Avsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Rq8pejBQpyfpBvg4MHykyjE8mwu9sHhOGcsrOcoZVak=; b=PvGweb4fesEGzUqQDzn+xsnsk28IYegCpKM7hSDeHqPXwTVdHSaOu0t+J+uTWzoBya dFAcr87UKgu6e3SKNDIAsLgkAG6dguLGIxeJpUY2/WJBuWEpy9b+47Iu6F9B3ZElxqjA JFLfcSBnqjgHKR0cZnEasYk1LsVHzX/f5X2Hb0R4O9CqYu09uE9TZ/67FK9GKq5iAtLt AVtA1VIQGRUuZ6Ozzld+hBBGJjvQalpZ4ORafIPpZF5vLPl5eW5zqHa+KyhQ2ZTCHNSM HKLd/Wnu8XP+smm3tI1GuGICyClDL0wTn4Plk/UgSPNxd7vO+PZdlS5AO/JwCAbApcBj 75Vg== X-Gm-Message-State: APjAAAW6agpQwPkCB34DBHnOp4pmcWQwKG9tGsedPAoaxV9zQXl+Sy5D lwtn6l7iwUj+p8CeG1FCg0gOBQ== X-Google-Smtp-Source: APXvYqzbHhH9wNc1N5m4OyPYQhcixSq6xo4qEpcyKoKJWtGTBJLZz8BJr17kEA7WcZynU5HjFUXwaA== X-Received: by 2002:a1c:9e13:: with SMTP id h19mr5955605wme.21.1581702681729; Fri, 14 Feb 2020 09:51:21 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 02/21] target/arm: Check aa32_pan in take_aarch32_exception(), not aa64_pan Date: Fri, 14 Feb 2020 17:50:57 +0000 Message-Id: <20200214175116.9164-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200214175116.9164-1-peter.maydell@linaro.org> References: <20200214175116.9164-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eric Auger , Aaron Lindsay , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" In take_aarch32_exception(), we know we are dealing with a CPU that has AArch32, so the right isar_feature test is aa32_pan, not aa64_pan. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index eec3876610c..d4ed52981fa 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8858,7 +8858,7 @@ static void take_aarch32_exception(CPUARMState *env, = int new_mode, env->elr_el[2] =3D env->regs[15]; } else { /* CPSR.PAN is normally preserved preserved unless... */ - if (cpu_isar_feature(aa64_pan, env_archcpu(env))) { + if (cpu_isar_feature(aa32_pan, env_archcpu(env))) { switch (new_el) { case 3: if (!arm_is_secure_below_el3(env)) { --=20 2.20.1 From nobody Mon May 6 22:28:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581702765148376.0818244975136; Fri, 14 Feb 2020 09:52:45 -0800 (PST) Received: from localhost ([::1]:42784 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2f8t-0007jm-Jy for importer@patchew.org; Fri, 14 Feb 2020 12:52:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55889) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2f7g-0005nQ-Fs for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:29 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j2f7e-0000h4-HF for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:28 -0500 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:44432) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j2f7e-0000gR-BH for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:26 -0500 Received: by mail-wr1-x435.google.com with SMTP id m16so11859597wrx.11 for ; Fri, 14 Feb 2020 09:51:26 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id v8sm8001857wrw.2.2020.02.14.09.51.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Feb 2020 09:51:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=s9mIaxlTRZ5zTlxqg89/DuL6snOn9SxxzOctwBKWPcM=; b=PhLe/1C/I4v1Cb7dLryZk3KEi9Tx4DFExGHh+uNYmxxFrcafekGoV1iDQuzOakfQJ+ uGxbwW7t/RF1rVsKcRkicSVdQ+LUklRjDNC4+AWLRG/TQtp9zemkgY3Z5TGWc06pqxpH dlgDpt+ONIXr1Cjp/x5Qn9ojeg86YfAySpzkI5fC3ctCGiY8jFCkzy0hN0zNy+uNjkUW lIjA0qk0/lHEvOSRnsy9rMs5G023FJYesKQtnCxJmUvwcFidJXdDM44p0jBM61i8goLd +SXYTrONEvP0zL+dm4VJG4jbdroH9kTLZJu3GcJ6UFhGNtjHWc9s/k5j7Opno/0jN6gC SUiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=s9mIaxlTRZ5zTlxqg89/DuL6snOn9SxxzOctwBKWPcM=; b=mSlXlJTnhYyvvIzgGa4/deaXNAxdZYr1hBUONoMfcEsM79YFqVHabTMMbqtwhL9397 5moFpTsi5oKkrLF5vPiG+vDnORunkh2zgBZqrYgSMLpDk0OA3u2E4HUocctPoE0e/6ZV IM8vaolUMXN2AA0riAXVQWqQKXh/gPa9Vszlfxk3HZik+aIceK0+f3Cxmego77iv1TaX b9Y+dAEHqAkubJpm2MjgwZclJl5plmu6bMtFCkwnmpPR1R35uEoS/Ok168Ku7hiP+QdT rD8eagyb11P5jvWz4E6MGCmEi5Crxlr0YVEIfmuY5Ivd2KFkKmcf+y4wxLkXjNY4P/Eq Rc2Q== X-Gm-Message-State: APjAAAUImkRUrfEVIfrHR83e6pyddATeGfNRm55Zl0sNIQA5psR9JZt4 0jY1prbgo6Pa8L+FI1XbMGxs2w== X-Google-Smtp-Source: APXvYqxF7917xGze3mt/9JLPt423aLnN1aY6hfmAn4/+0gI37pEK+eD1SGBfPzqKerg0J45wHxOGyw== X-Received: by 2002:a05:6000:1251:: with SMTP id j17mr5464470wrx.210.1581702685128; Fri, 14 Feb 2020 09:51:25 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 03/21] target/arm: Add isar_feature_any_fp16 and document naming/usage conventions Date: Fri, 14 Feb 2020 17:50:58 +0000 Message-Id: <20200214175116.9164-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200214175116.9164-1-peter.maydell@linaro.org> References: <20200214175116.9164-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::435 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eric Auger , Aaron Lindsay , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Our current usage of the isar_feature feature tests almost always uses an _aa32_ test when the code path is known to be AArch32 specific and an _aa64_ test when the code path is known to be AArch64 specific. There is just one exception: in the vfp_set_fpscr helper we check aa64_fp16 to determine whether the FZ16 bit in the FP(S)CR exists, but this code is also used for AArch32. There are other places in future where we're likely to want a general "does this feature exist for either AArch32 or AArch64" check (typically where architecturally the feature exists for both CPU states if it exists at all, but the CPU might be AArch32-only or AArch64-only, and so only have one set of ID registers). Introduce a new category of isar_feature_* functions: isar_feature_any_foo() should be tested when what we want to know is "does this feature exist for either AArch32 or AArch64", and always returns the logical OR of isar_feature_aa32_foo() and isar_feature_aa64_foo(). Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell --- target/arm/cpu.h | 19 ++++++++++++++++++- target/arm/vfp_helper.c | 2 +- 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 37d40e57901..7ccd65bdce3 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3328,7 +3328,16 @@ extern const uint64_t pred_esz_masks[4]; * Naming convention for isar_feature functions: * Functions which test 32-bit ID registers should have _aa32_ in * their name. Functions which test 64-bit ID registers should have - * _aa64_ in their name. + * _aa64_ in their name. These must only be used in code where we + * know for certain that the CPU has AArch32 or AArch64 respectively + * or where the correct answer for a CPU which doesn't implement that + * CPU state is "false" (eg when generating A32 or A64 code, if adding + * system registers that are specific to that CPU state, for "should + * we let this system register bit be set" tests where the 32-bit + * flavour of the register doesn't have the bit, and so on). + * Functions which simply ask "does this feature exist at all" have + * _any_ in their name, and always return the logical OR of the _aa64_ + * and the _aa32_ function. */ =20 /* @@ -3660,6 +3669,14 @@ static inline bool isar_feature_aa64_bti(const ARMIS= ARegisters *id) return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) !=3D 0; } =20 +/* + * Feature tests for "does this exist in either 32-bit or 64-bit?" + */ +static inline bool isar_feature_any_fp16(const ARMISARegisters *id) +{ + return isar_feature_aa64_fp16(id) || isar_feature_aa32_fp16_arith(id); +} + /* * Forward to the above feature tests given an ARMCPU pointer. */ diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index 0ae7d4f34a9..930d6e747f6 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -185,7 +185,7 @@ uint32_t vfp_get_fpscr(CPUARMState *env) void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) { /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */ - if (!cpu_isar_feature(aa64_fp16, env_archcpu(env))) { + if (!cpu_isar_feature(any_fp16, env_archcpu(env))) { val &=3D ~FPCR_FZ16; } =20 --=20 2.20.1 From nobody Mon May 6 22:28:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581702929176641.0553747315815; Fri, 14 Feb 2020 09:55:29 -0800 (PST) Received: from localhost ([::1]:42894 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2fBX-0006I8-St for importer@patchew.org; Fri, 14 Feb 2020 12:55:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55911) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2f7i-0005pz-BZ for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:31 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j2f7f-0000hq-CQ for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:30 -0500 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:45248) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j2f7f-0000hB-6W for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:27 -0500 Received: by mail-wr1-x443.google.com with SMTP id g3so11868395wrs.12 for ; Fri, 14 Feb 2020 09:51:27 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id v8sm8001857wrw.2.2020.02.14.09.51.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Feb 2020 09:51:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5yFL6qJIGrr6vMsTkdaf8oL+HzuN+eqpKkJ6fDD8yLs=; b=IYCp5AzTtdyojqddY7SiOZHntlgKyZ3KYGFsC69DYHBgd6uzM0lTbYhCcM0+E4dxg4 9ZyceTGxmOGIM3eaQlaWbt6OK1lyhYcVdTT+KY1aRhxDnJdUCrRDCxUQkW4SLkYwn4cW Xq9wWEo4kt3UpUi+Or2rVPWLUljpKBY8Jq0A/HitrCP2NuH96gNLzhf2lO+sRBF+VhN/ 3QeeJ7kKFrkoJ3KI1KfC0oxHUGJtzguiNPJLhnnqsayN0RYNCWJy0iM5MF1e+b8JR068 DBTN7NY5gK4FqFfaNoz80rAsWEUmyG2PBVG2cyhyCRWriWVsup/6QV15gkK3f9fpisNy Igwg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5yFL6qJIGrr6vMsTkdaf8oL+HzuN+eqpKkJ6fDD8yLs=; b=Usjkt65Wy61zKd0PMfKV2gbJ+3GGe6fNsnnSAgeFD0koNV/dLFEOUQ8sgYdqq8/yyM cAP0X5F0AEooqOu/RVcM0TdISRP8NEUwmgXqHqoMn+aMjXDxASWSHhHIv+INoGalB5XZ jfPIzjp2X93u0za3OqP6ARRrtLJUs0c8ItJQ4l85c0cReVzLDDqi+wjnch8gX8nvOfhR GH28IDmlYK+FuhFkk3bmjSWPSiwI+xxCSDG1iQznCiX7k7xM+tmewAGwkA9TJsnZUeWW DrrSCdnW8tvYDlAgoOBUL7PnVD5/ikvx7W5arrBoMlFGEYuoJO1zbVwBdk7S6QhI4BN5 I7LQ== X-Gm-Message-State: APjAAAXIx9PR8n8bth/YQmUpv1NqgPNJevLF8M86dMfAP3ili0N5mvSD zG954wunh1v8Zq/9sprn68YkeQ== X-Google-Smtp-Source: APXvYqy1MC/x2LSE7lEyzVkpTtGmSJG3QhOq7Cj7XIelCzHql3tfGSF1dlHR/IUSp31yInVnIQH3cA== X-Received: by 2002:adf:b60f:: with SMTP id f15mr5381955wre.372.1581702686270; Fri, 14 Feb 2020 09:51:26 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 04/21] target/arm: Define and use any_predinv isar_feature test Date: Fri, 14 Feb 2020 17:50:59 +0000 Message-Id: <20200214175116.9164-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200214175116.9164-1-peter.maydell@linaro.org> References: <20200214175116.9164-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eric Auger , Aaron Lindsay , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Instead of open-coding "ARM_FEATURE_AARCH64 ? aa64_predinv: aa32_predinv", define and use an any_predinv isar_feature test function. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell --- target/arm/cpu.h | 5 +++++ target/arm/helper.c | 9 +-------- 2 files changed, 6 insertions(+), 8 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 7ccd65bdce3..ef0feb228ab 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3677,6 +3677,11 @@ static inline bool isar_feature_any_fp16(const ARMIS= ARegisters *id) return isar_feature_aa64_fp16(id) || isar_feature_aa32_fp16_arith(id); } =20 +static inline bool isar_feature_any_predinv(const ARMISARegisters *id) +{ + return isar_feature_aa64_predinv(id) || isar_feature_aa32_predinv(id); +} + /* * Forward to the above feature tests given an ARMCPU pointer. */ diff --git a/target/arm/helper.c b/target/arm/helper.c index d4ed52981fa..b3ced7f78ba 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7721,14 +7721,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) #endif /*CONFIG_USER_ONLY*/ #endif =20 - /* - * While all v8.0 cpus support aarch64, QEMU does have configurations - * that do not set ID_AA64ISAR1, e.g. user-only qemu-arm -cpu max, - * which will set ID_ISAR6. - */ - if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) - ? cpu_isar_feature(aa64_predinv, cpu) - : cpu_isar_feature(aa32_predinv, cpu)) { + if (cpu_isar_feature(any_predinv, cpu)) { define_arm_cp_regs(cpu, predinv_reginfo); } =20 --=20 2.20.1 From nobody Mon May 6 22:28:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 15817028467749.070002975108991; Fri, 14 Feb 2020 09:54:06 -0800 (PST) Received: from localhost ([::1]:42830 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2fAB-0002v8-4a for importer@patchew.org; Fri, 14 Feb 2020 12:54:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55962) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2f7k-0005t7-9T for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:33 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j2f7i-0000jp-8w for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:31 -0500 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]:36021) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j2f7g-0000iB-FM for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:29 -0500 Received: by mail-wm1-x344.google.com with SMTP id p17so11555138wma.1 for ; Fri, 14 Feb 2020 09:51:28 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id v8sm8001857wrw.2.2020.02.14.09.51.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Feb 2020 09:51:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2XRfHOyhPSH4cYUDW/HDN1fLtRvOem+XGDBRyAVp+4g=; b=howWY4qzlzNbFfxTLB4TSROv/wu5EMJngCO5FaSXYWex4j5cbNsJzbSpksLIV7GXoK CrZDi8ssBLeBwunKyQ2SUwk1F8gX2iv3TLEFO70EPXdjuJzO3kcfsYXaEHsOruWXBeMn DEiW3YyVvfXkaIzTnRSjE9avp1x1olpym1yEuZy/uzSqp1MK8hx5n6cYAXSq+eTJuHj+ 9Qkms5M8j2NERs+hxs6K2Ab8Zj9E9zbp3rP5F5iNjMEz039mer0LBeLWqVYldaSvgdGP 3KAH0wtExQo/QjRJ8pwOxcf2641IKAcYd6wYlztH0uLqk0jhRa9n00iTWfYchjks31xB pr/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2XRfHOyhPSH4cYUDW/HDN1fLtRvOem+XGDBRyAVp+4g=; b=bpbTpDCTU04sH0OfufGWvN4IqQNq3W1+q0G1ZVl90bUxrfw9FUrnKlcMhKIUd03OYa v5RLUi9hl5Gaj6lZuqABtONQXIo2X5sHUEL+jibTGMm6sbB4kNI/FbIOc3ca3TkuIfQH IFPb3Okv8wo9PuRbczXRtvrNdnkAll/66UFi+myfAb42c7RJzJ/RxJ1I4DMg4ap77tOx PczhuKlB0uERQZo0d1+Aw8ATmO+wdiCk1wuRJUzQOXF/yvQvSJ/mpr9OXbDkKLei8Crv iUlXUeyAKTD3OTAV/zqyaYwUvq2V6N7lP4Son4pfBF4Wfn8u8tqT568rHmxeGgJXGKlm laaA== X-Gm-Message-State: APjAAAU9aSSmkmagR4Bwwhx4zd/TA60XuwsKQ4A7pQ2Dc26lJ8uBoTAy R6faN13R2rFWB/EeLvjimXdjig== X-Google-Smtp-Source: APXvYqxNtSAzvh3C4BzIoseHKH3vvaKuwZ1pzZIUnfIleYjw10BNjXP50Sbl8UrwijTH2/i5VgnirA== X-Received: by 2002:a1c:e483:: with SMTP id b125mr5869729wmh.187.1581702687425; Fri, 14 Feb 2020 09:51:27 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 05/21] target/arm: Factor out PMU register definitions Date: Fri, 14 Feb 2020 17:51:00 +0000 Message-Id: <20200214175116.9164-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200214175116.9164-1-peter.maydell@linaro.org> References: <20200214175116.9164-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eric Auger , Aaron Lindsay , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Pull the code that defines the various PMU registers out into its own function, matching the pattern we have already for the debug registers. Apart from one style fix to a multi-line comment, this is purely movement of code with no changes to it. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell --- target/arm/helper.c | 158 +++++++++++++++++++++++--------------------- 1 file changed, 82 insertions(+), 76 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index b3ced7f78ba..c53d6406474 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6317,6 +6317,87 @@ static void define_debug_regs(ARMCPU *cpu) } } =20 +static void define_pmu_regs(ARMCPU *cpu) +{ + /* + * v7 performance monitor control register: same implementor + * field as main ID register, and we implement four counters in + * addition to the cycle count register. + */ + unsigned int i, pmcrn =3D 4; + ARMCPRegInfo pmcr =3D { + .name =3D "PMCR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D 0= , .opc2 =3D 0, + .access =3D PL0_RW, + .type =3D ARM_CP_IO | ARM_CP_ALIAS, + .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmcr), + .accessfn =3D pmreg_access, .writefn =3D pmcr_write, + .raw_writefn =3D raw_write, + }; + ARMCPRegInfo pmcr64 =3D { + .name =3D "PMCR_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 0, + .access =3D PL0_RW, .accessfn =3D pmreg_access, + .type =3D ARM_CP_IO, + .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmcr), + .resetvalue =3D (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHIFT), + .writefn =3D pmcr_write, .raw_writefn =3D raw_write, + }; + define_one_arm_cp_reg(cpu, &pmcr); + define_one_arm_cp_reg(cpu, &pmcr64); + for (i =3D 0; i < pmcrn; i++) { + char *pmevcntr_name =3D g_strdup_printf("PMEVCNTR%d", i); + char *pmevcntr_el0_name =3D g_strdup_printf("PMEVCNTR%d_EL0", i); + char *pmevtyper_name =3D g_strdup_printf("PMEVTYPER%d", i); + char *pmevtyper_el0_name =3D g_strdup_printf("PMEVTYPER%d_EL0", i); + ARMCPRegInfo pmev_regs[] =3D { + { .name =3D pmevcntr_name, .cp =3D 15, .crn =3D 14, + .crm =3D 8 | (3 & (i >> 3)), .opc1 =3D 0, .opc2 =3D i & 7, + .access =3D PL0_RW, .type =3D ARM_CP_IO | ARM_CP_ALIAS, + .readfn =3D pmevcntr_readfn, .writefn =3D pmevcntr_writefn, + .accessfn =3D pmreg_access }, + { .name =3D pmevcntr_el0_name, .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 8 | (3 & (i = >> 3)), + .opc2 =3D i & 7, .access =3D PL0_RW, .accessfn =3D pmreg_acc= ess, + .type =3D ARM_CP_IO, + .readfn =3D pmevcntr_readfn, .writefn =3D pmevcntr_writefn, + .raw_readfn =3D pmevcntr_rawread, + .raw_writefn =3D pmevcntr_rawwrite }, + { .name =3D pmevtyper_name, .cp =3D 15, .crn =3D 14, + .crm =3D 12 | (3 & (i >> 3)), .opc1 =3D 0, .opc2 =3D i & 7, + .access =3D PL0_RW, .type =3D ARM_CP_IO | ARM_CP_ALIAS, + .readfn =3D pmevtyper_readfn, .writefn =3D pmevtyper_writefn, + .accessfn =3D pmreg_access }, + { .name =3D pmevtyper_el0_name, .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 12 | (3 & (i= >> 3)), + .opc2 =3D i & 7, .access =3D PL0_RW, .accessfn =3D pmreg_acc= ess, + .type =3D ARM_CP_IO, + .readfn =3D pmevtyper_readfn, .writefn =3D pmevtyper_writefn, + .raw_writefn =3D pmevtyper_rawwrite }, + REGINFO_SENTINEL + }; + define_arm_cp_regs(cpu, pmev_regs); + g_free(pmevcntr_name); + g_free(pmevcntr_el0_name); + g_free(pmevtyper_name); + g_free(pmevtyper_el0_name); + } + if (FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) >=3D 4 && + FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) !=3D 0xf) { + ARMCPRegInfo v81_pmu_regs[] =3D { + { .name =3D "PMCEID2", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D = 4, + .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, + .resetvalue =3D extract64(cpu->pmceid0, 32, 32) }, + { .name =3D "PMCEID3", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D = 5, + .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, + .resetvalue =3D extract64(cpu->pmceid1, 32, 32) }, + REGINFO_SENTINEL + }; + define_arm_cp_regs(cpu, v81_pmu_regs); + } +} + /* We don't know until after realize whether there's a GICv3 * attached, and that is what registers the gicv3 sysregs. * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_= EL1 @@ -6859,67 +6940,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, pmovsset_cp_reginfo); } if (arm_feature(env, ARM_FEATURE_V7)) { - /* v7 performance monitor control register: same implementor - * field as main ID register, and we implement four counters in - * addition to the cycle count register. - */ - unsigned int i, pmcrn =3D 4; - ARMCPRegInfo pmcr =3D { - .name =3D "PMCR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 = =3D 0, .opc2 =3D 0, - .access =3D PL0_RW, - .type =3D ARM_CP_IO | ARM_CP_ALIAS, - .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmcr), - .accessfn =3D pmreg_access, .writefn =3D pmcr_write, - .raw_writefn =3D raw_write, - }; - ARMCPRegInfo pmcr64 =3D { - .name =3D "PMCR_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 0, - .access =3D PL0_RW, .accessfn =3D pmreg_access, - .type =3D ARM_CP_IO, - .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmcr), - .resetvalue =3D (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHI= FT), - .writefn =3D pmcr_write, .raw_writefn =3D raw_write, - }; - define_one_arm_cp_reg(cpu, &pmcr); - define_one_arm_cp_reg(cpu, &pmcr64); - for (i =3D 0; i < pmcrn; i++) { - char *pmevcntr_name =3D g_strdup_printf("PMEVCNTR%d", i); - char *pmevcntr_el0_name =3D g_strdup_printf("PMEVCNTR%d_EL0", = i); - char *pmevtyper_name =3D g_strdup_printf("PMEVTYPER%d", i); - char *pmevtyper_el0_name =3D g_strdup_printf("PMEVTYPER%d_EL0"= , i); - ARMCPRegInfo pmev_regs[] =3D { - { .name =3D pmevcntr_name, .cp =3D 15, .crn =3D 14, - .crm =3D 8 | (3 & (i >> 3)), .opc1 =3D 0, .opc2 =3D i & = 7, - .access =3D PL0_RW, .type =3D ARM_CP_IO | ARM_CP_ALIAS, - .readfn =3D pmevcntr_readfn, .writefn =3D pmevcntr_write= fn, - .accessfn =3D pmreg_access }, - { .name =3D pmevcntr_el0_name, .state =3D ARM_CP_STATE_AA6= 4, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 8 | (3 &= (i >> 3)), - .opc2 =3D i & 7, .access =3D PL0_RW, .accessfn =3D pmreg= _access, - .type =3D ARM_CP_IO, - .readfn =3D pmevcntr_readfn, .writefn =3D pmevcntr_write= fn, - .raw_readfn =3D pmevcntr_rawread, - .raw_writefn =3D pmevcntr_rawwrite }, - { .name =3D pmevtyper_name, .cp =3D 15, .crn =3D 14, - .crm =3D 12 | (3 & (i >> 3)), .opc1 =3D 0, .opc2 =3D i &= 7, - .access =3D PL0_RW, .type =3D ARM_CP_IO | ARM_CP_ALIAS, - .readfn =3D pmevtyper_readfn, .writefn =3D pmevtyper_wri= tefn, - .accessfn =3D pmreg_access }, - { .name =3D pmevtyper_el0_name, .state =3D ARM_CP_STATE_AA= 64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 12 | (3 = & (i >> 3)), - .opc2 =3D i & 7, .access =3D PL0_RW, .accessfn =3D pmreg= _access, - .type =3D ARM_CP_IO, - .readfn =3D pmevtyper_readfn, .writefn =3D pmevtyper_wri= tefn, - .raw_writefn =3D pmevtyper_rawwrite }, - REGINFO_SENTINEL - }; - define_arm_cp_regs(cpu, pmev_regs); - g_free(pmevcntr_name); - g_free(pmevcntr_el0_name); - g_free(pmevtyper_name); - g_free(pmevtyper_el0_name); - } ARMCPRegInfo clidr =3D { .name =3D "CLIDR", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 1, .opc2 =3D 1, @@ -6930,24 +6950,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_one_arm_cp_reg(cpu, &clidr); define_arm_cp_regs(cpu, v7_cp_reginfo); define_debug_regs(cpu); + define_pmu_regs(cpu); } else { define_arm_cp_regs(cpu, not_v7_cp_reginfo); } - if (FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) >=3D 4 && - FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) !=3D 0xf) { - ARMCPRegInfo v81_pmu_regs[] =3D { - { .name =3D "PMCEID2", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D = 4, - .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, - .resetvalue =3D extract64(cpu->pmceid0, 32, 32) }, - { .name =3D "PMCEID3", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D = 5, - .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, - .resetvalue =3D extract64(cpu->pmceid1, 32, 32) }, - REGINFO_SENTINEL - }; - define_arm_cp_regs(cpu, v81_pmu_regs); - } if (arm_feature(env, ARM_FEATURE_V8)) { /* AArch64 ID registers, which all have impdef reset values. * Note that within the ID register ranges the unused slots --=20 2.20.1 From nobody Mon May 6 22:28:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581703131078650.6021162495662; Fri, 14 Feb 2020 09:58:51 -0800 (PST) Received: from localhost ([::1]:43015 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2fEn-0003YF-7O for importer@patchew.org; Fri, 14 Feb 2020 12:58:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55969) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2f7k-0005tL-EL for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:33 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j2f7j-0000kg-80 for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:32 -0500 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:36992) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j2f7i-0000in-88 for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:30 -0500 Received: by mail-wm1-x343.google.com with SMTP id a6so11578530wme.2 for ; Fri, 14 Feb 2020 09:51:29 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id v8sm8001857wrw.2.2020.02.14.09.51.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Feb 2020 09:51:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yBlr7RLXuaOwUWrVlg7CP/NZ0IeFAHTSIicsUai9nWU=; b=vBTlvwDKVpQvyC7BucuDnioGcfHw14OZ9eA4e9wpJLxYzEipRb797BLf2u0SAvDD4j qq7NoFoLmDle6555RyrKXltrifq8PWhuTWo3ZLQd4zOErUMeiRPmyzrbPdL0RgjiXjNu /pNfo3T+XmNto+C62pWNDcmLWeii6wVPBneaf2vgVvVqpUzK7OvxDaywLiALXHDLpzeQ aF/pBaD3R0aggy/E1CvT+iMkQk4vkFWk4Fks41i0MPMns8ZDHX32kV8qzwCkdV+B7HFl VgbITgJYY3lDbdeI5QicO+Q63WQSatDm27IHDdUanQqaVXVOny4N4pa986BxZYKxKcSl /RZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yBlr7RLXuaOwUWrVlg7CP/NZ0IeFAHTSIicsUai9nWU=; b=qwiLlA4J1sFgvYareuAf1ZVncR4T6fkUs122Z3BjfmXBaodD9vuVnp6EJ5y7QQiGOJ R7uxwt4O3Ari+7iZlMh4Wh0ewPWtJI5tBwh6trWYPJOD25jTctIQ8UrIdUmuAeVhv6b8 VXYC65Bglf0zYWTxxMHHkxexXFXPIE3NQsi1EgKlYcIck6ZnB1ZIEWljwVQFc/Pv1Gbf Q5HiivxHN6D6q6l5p5mEhbg9ClTpFcshTA2c0N84svUzt4t4fmn32A+O0iDKv3IxJvgy GOzB6YdGlAbj9W72X8mHR9TLwe35bjXaCg7n1LqpNiAIsZWX5tjaN3Dj6yC+rZ2mDagF QBDQ== X-Gm-Message-State: APjAAAUBtCRCaP/4oHvKN5jjMviG6CihV8o4pfpWOXEixiawsZBrru3E iOb+blcrRoQ3T+cIcLuAvDIX8zRkDmA= X-Google-Smtp-Source: APXvYqwySsB+QJhLxtkWqEPIgbb1WsFU92viGfoPL6nmpTMSOcobIfHzngbJxILvqw+/KIVVfN4Rxw== X-Received: by 2002:a1c:bdc6:: with SMTP id n189mr6009881wmf.102.1581702688695; Fri, 14 Feb 2020 09:51:28 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 06/21] target/arm: Add and use FIELD definitions for ID_AA64DFR0_EL1 Date: Fri, 14 Feb 2020 17:51:01 +0000 Message-Id: <20200214175116.9164-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200214175116.9164-1-peter.maydell@linaro.org> References: <20200214175116.9164-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eric Auger , Aaron Lindsay , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Add FIELD() definitions for the ID_AA64DFR0_EL1 and use them where we currently have hard-coded bit values. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell --- v1->v2: use FIELD_EX64/FIELD_DP64 for 64-bit ID register --- target/arm/cpu.h | 10 ++++++++++ target/arm/cpu.c | 2 +- target/arm/helper.c | 6 +++--- 3 files changed, 14 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ef0feb228ab..081955094dc 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1821,6 +1821,16 @@ FIELD(ID_AA64MMFR2, BBM, 52, 4) FIELD(ID_AA64MMFR2, EVT, 56, 4) FIELD(ID_AA64MMFR2, E0PD, 60, 4) =20 +FIELD(ID_AA64DFR0, DEBUGVER, 0, 4) +FIELD(ID_AA64DFR0, TRACEVER, 4, 4) +FIELD(ID_AA64DFR0, PMUVER, 8, 4) +FIELD(ID_AA64DFR0, BRPS, 12, 4) +FIELD(ID_AA64DFR0, WRPS, 20, 4) +FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4) +FIELD(ID_AA64DFR0, PMSVER, 32, 4) +FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4) +FIELD(ID_AA64DFR0, TRACEFILT, 40, 4) + FIELD(ID_DFR0, COPDBG, 0, 4) FIELD(ID_DFR0, COPSDBG, 4, 4) FIELD(ID_DFR0, MMAPDBG, 8, 4) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 56f2ab865da..12bf9688007 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1718,7 +1718,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) cpu); #endif } else { - cpu->id_aa64dfr0 &=3D ~0xf00; + cpu->id_aa64dfr0 =3D FIELD_DP64(cpu->id_aa64dfr0, ID_AA64DFR0, PMU= VER, 0); cpu->id_dfr0 &=3D ~(0xf << 24); cpu->pmceid0 =3D 0; cpu->pmceid1 =3D 0; diff --git a/target/arm/helper.c b/target/arm/helper.c index c53d6406474..376c6412f91 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6266,9 +6266,9 @@ static void define_debug_regs(ARMCPU *cpu) * check that if they both exist then they agree. */ if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - assert(extract32(cpu->id_aa64dfr0, 12, 4) =3D=3D brps); - assert(extract32(cpu->id_aa64dfr0, 20, 4) =3D=3D wrps); - assert(extract32(cpu->id_aa64dfr0, 28, 4) =3D=3D ctx_cmps); + assert(FIELD_EX64(cpu->id_aa64dfr0, ID_AA64DFR0, BRPS) =3D=3D brps= ); + assert(FIELD_EX64(cpu->id_aa64dfr0, ID_AA64DFR0, WRPS) =3D=3D wrps= ); + assert(FIELD_EX64(cpu->id_aa64dfr0, ID_AA64DFR0, CTX_CMPS) =3D=3D = ctx_cmps); } =20 define_one_arm_cp_reg(cpu, &dbgdidr); --=20 2.20.1 From nobody Mon May 6 22:28:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 158170303345322.957779984623016; Fri, 14 Feb 2020 09:57:13 -0800 (PST) Received: from localhost ([::1]:42962 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2fDE-0000p5-8r for importer@patchew.org; Fri, 14 Feb 2020 12:57:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55968) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2f7k-0005tJ-Dj for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:33 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j2f7j-0000lQ-Do for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:32 -0500 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:40896) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j2f7j-0000k3-6v for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:31 -0500 Received: by mail-wm1-x343.google.com with SMTP id t14so11550723wmi.5 for ; Fri, 14 Feb 2020 09:51:30 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id v8sm8001857wrw.2.2020.02.14.09.51.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Feb 2020 09:51:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CamjQrx2ACX1pcdy+Ha3T8xE7Ntp0ezj0SgMxc8gmcs=; b=c4/UMPy4cEWJPOu19sIDnKbKBQHCK1UaTu2xAKNM7G9dpBGC0BpTwrms73Tw7DHAOp W/EwyK0Y6/aVJnVYm7U3+YbYtoFFHTNPjpRo559U8tBzqELS0evaNTQZOfvKso/CawwS u4lLC9WmW4YDEZG4acOP6YVl17f10YjGj0tKVknruBhTk+PFS0r6/Jc8/mr8B3rB+fhE dhcRFK3jj1mFvxOQvLk0427NibQLjYKnwVx8AUQipFcJIw/MLIUpPCy/zBoH1G7p0Kh9 1O/Tg1YAMytA0UgR2oCfd3On9i9FwSIkzr1IvPaNHucldAkewUdK29EicVxuMOPipeD8 2vpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CamjQrx2ACX1pcdy+Ha3T8xE7Ntp0ezj0SgMxc8gmcs=; b=bZvvuWebjSJ3x+1/VDWnk6Ff0cdagw6xN1TzARG3vkwa5t85Hnj2V5h7tIkYaTYJF7 q9toa6jymezqx/z4T9HToXnuu2/d2569uPsCQ6CXPs+3Xke+nc5J8bryrFeN8t1F3NqM wLMJCFzUFd7BSfAIbuo5dvfBygorVHDBh6/oJWb7xqnvsnWcfZ5JcseLYNe8DlOsKJV7 DBxou/Q+DvOcv1pSUmnTiWgKFaE7vP5dPaNxvQRqUPIU5uqDtyGecg6UxBqYNvKwUKYQ 5GQzgBtp3Lr99By/X1c9HPNp4idnsIUEB4Go3l2Fko4wdQAhypQj+Y9oHdnuYDOvPJ8Y 34Dw== X-Gm-Message-State: APjAAAVnu2C3aOhE5yazO0r4Blm3eR54ED1TuyF8B7Y26S5d/duqnhXF kedZi0j/eN/uIWGY+wFLs/p2vA== X-Google-Smtp-Source: APXvYqy6560S0tzqD0RgASpxqZiSB2f/jGmZUl4l+KgLn2/1GqgfG+mTVYvpNwa8+/CFFS2UEkBCWQ== X-Received: by 2002:a7b:cbd6:: with SMTP id n22mr6083108wmi.118.1581702689959; Fri, 14 Feb 2020 09:51:29 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 07/21] target/arm: Use FIELD macros for clearing ID_DFR0 PERFMON field Date: Fri, 14 Feb 2020 17:51:02 +0000 Message-Id: <20200214175116.9164-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200214175116.9164-1-peter.maydell@linaro.org> References: <20200214175116.9164-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eric Auger , Aaron Lindsay , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) We already define FIELD macros for ID_DFR0, so use them in the one place where we're doing direct bit value manipulation. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell --- We have lots of this non-FIELD style in the code, of course; I change this one purely because it otherwise looks a bit odd sat next to the ID_AA64DFR0 line that was changed in the previous patch... --- target/arm/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 12bf9688007..1024f506c51 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1719,7 +1719,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) #endif } else { cpu->id_aa64dfr0 =3D FIELD_DP64(cpu->id_aa64dfr0, ID_AA64DFR0, PMU= VER, 0); - cpu->id_dfr0 &=3D ~(0xf << 24); + cpu->id_dfr0 =3D FIELD_DP32(cpu->id_dfr0, ID_DFR0, PERFMON, 0); cpu->pmceid0 =3D 0; cpu->pmceid1 =3D 0; } --=20 2.20.1 From nobody Mon May 6 22:28:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581703262734902.7241648531357; Fri, 14 Feb 2020 10:01:02 -0800 (PST) Received: from localhost ([::1]:43062 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2fGq-0006Go-3T for importer@patchew.org; Fri, 14 Feb 2020 13:00:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56022) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2f7m-0005vX-Qq for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:37 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j2f7l-0000n3-5C for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:34 -0500 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:41171) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j2f7k-0000lp-Bn for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:32 -0500 Received: by mail-wr1-x442.google.com with SMTP id c9so11896337wrw.8 for ; Fri, 14 Feb 2020 09:51:32 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id v8sm8001857wrw.2.2020.02.14.09.51.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Feb 2020 09:51:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8vZsaT2+tk9YLi++unYB+Z+jW0b/JEinNqFa1FTVjNg=; b=Wsh2MgwVg3QN3APiAcgnIcN5PpHA4mrawspkWx3oP8RMnEH8yxw9cQzSkdWF1syp7W rr4lpoZYYXATfKVwwUv+2wPjF3IojpHixzeTjkSTziWHM/SdtC8Wrk30trA7IA2BJ+O3 gXyvMsYTSrpt2XNGotUpqCpLVW2oZuWfzi/UHH2j+6OkFS+hODXJLJ0hEfDj0jf3qAja h5zDJBWuy1ULhGg18Td5phzH0jrHJZvr7V10QoEZL/DccAU7l6+/hUNirA9nxEzoBaHE u/TrJt/jXKC8miXkI68Vr3xIpgL3yQbGp4itS4bkbXqGDAsmXW/w4a57eFtLYM19Ngwf vtRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8vZsaT2+tk9YLi++unYB+Z+jW0b/JEinNqFa1FTVjNg=; b=MZJtfyi465k3FwV5K2XJlnAiTf7fQwmZ/3YcCV/Uej1SpWzufzzp/BobAYByM1WhDI LWTASCkNA1c6iDlgG+Teuhmk3BR/Ty1AbV2BtoZcLoP4NA1vA/Q+4ABTpnb6Q6Hah1Bs EJL8xsQ8GLOzPfzCNdb8y3qG8UzTWImIvv4FiGyVH0rgzJy7qArSKXcP7fqOTAJN9zRy 2cHPrJo9K+2kUdxreEKloR36dItMqQs0gxX69zVW07uJzw7P4oMOZtaHtvLY0t/wRI3P t8WbiiUAZgvfvXU3hjS3ntZsQLWZrGT6XnxBTBskgHFOaMfn+DuiLSbLQrex2W1Z6oGQ aJOQ== X-Gm-Message-State: APjAAAX4muQGf+bV+/6gX5snZ4oy3CIAS8iBpZfCIuT7AIJWz8SOEabo nqdsXFhcaPApfYqqRjKN8ArCfg== X-Google-Smtp-Source: APXvYqx+zdrwc0GGyH2blXS2VLhQIl+1v6OVJgzUkMMwOSBBdng1lxvOhkxkLxcbLTQYaiZmfzsjbw== X-Received: by 2002:adf:e5c6:: with SMTP id a6mr5253518wrn.185.1581702691276; Fri, 14 Feb 2020 09:51:31 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 08/21] target/arm: Define an aa32_pmu_8_1 isar feature test function Date: Fri, 14 Feb 2020 17:51:03 +0000 Message-Id: <20200214175116.9164-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200214175116.9164-1-peter.maydell@linaro.org> References: <20200214175116.9164-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eric Auger , Aaron Lindsay , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Instead of open-coding a check on the ID_DFR0 PerfMon ID register field, create a standardly-named isar_feature for "does AArch32 have a v8.1 PMUv3" and use it. This entails moving the id_dfr0 field into the ARMISARegisters struct. Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell --- target/arm/cpu.h | 9 ++++++++- hw/intc/armv7m_nvic.c | 2 +- target/arm/cpu.c | 28 ++++++++++++++-------------- target/arm/cpu64.c | 6 +++--- target/arm/helper.c | 5 ++--- 5 files changed, 28 insertions(+), 22 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 081955094dc..6c6088eb587 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -865,6 +865,7 @@ struct ARMCPU { uint32_t mvfr0; uint32_t mvfr1; uint32_t mvfr2; + uint32_t id_dfr0; uint64_t id_aa64isar0; uint64_t id_aa64isar1; uint64_t id_aa64pfr0; @@ -880,7 +881,6 @@ struct ARMCPU { uint32_t reset_sctlr; uint32_t id_pfr0; uint32_t id_pfr1; - uint32_t id_dfr0; uint64_t pmceid0; uint64_t pmceid1; uint32_t id_afr0; @@ -3500,6 +3500,13 @@ static inline bool isar_feature_aa32_ats1e1(const AR= MISARegisters *id) return FIELD_EX64(id->mvfr0, ID_MMFR3, PAN) >=3D 2; } =20 +static inline bool isar_feature_aa32_pmu_8_1(const ARMISARegisters *id) +{ + /* 0xf means "non-standard IMPDEF PMU" */ + return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >=3D 4 && + FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) !=3D 0xf; +} + /* * 64-bit feature tests via id registers. */ diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index f9e0eeaace6..5a403fc9704 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1227,7 +1227,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t off= set, MemTxAttrs attrs) case 0xd44: /* PFR1. */ return cpu->id_pfr1; case 0xd48: /* DFR0. */ - return cpu->id_dfr0; + return cpu->isar.id_dfr0; case 0xd4c: /* AFR0. */ return cpu->id_afr0; case 0xd50: /* MMFR0. */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 1024f506c51..b85040d36bc 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1719,7 +1719,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) #endif } else { cpu->id_aa64dfr0 =3D FIELD_DP64(cpu->id_aa64dfr0, ID_AA64DFR0, PMU= VER, 0); - cpu->id_dfr0 =3D FIELD_DP32(cpu->id_dfr0, ID_DFR0, PERFMON, 0); + cpu->isar.id_dfr0 =3D FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFM= ON, 0); cpu->pmceid0 =3D 0; cpu->pmceid1 =3D 0; } @@ -1957,7 +1957,7 @@ static void arm1136_r2_initfn(Object *obj) cpu->reset_sctlr =3D 0x00050078; cpu->id_pfr0 =3D 0x111; cpu->id_pfr1 =3D 0x1; - cpu->id_dfr0 =3D 0x2; + cpu->isar.id_dfr0 =3D 0x2; cpu->id_afr0 =3D 0x3; cpu->id_mmfr0 =3D 0x01130003; cpu->id_mmfr1 =3D 0x10030302; @@ -1989,7 +1989,7 @@ static void arm1136_initfn(Object *obj) cpu->reset_sctlr =3D 0x00050078; cpu->id_pfr0 =3D 0x111; cpu->id_pfr1 =3D 0x1; - cpu->id_dfr0 =3D 0x2; + cpu->isar.id_dfr0 =3D 0x2; cpu->id_afr0 =3D 0x3; cpu->id_mmfr0 =3D 0x01130003; cpu->id_mmfr1 =3D 0x10030302; @@ -2022,7 +2022,7 @@ static void arm1176_initfn(Object *obj) cpu->reset_sctlr =3D 0x00050078; cpu->id_pfr0 =3D 0x111; cpu->id_pfr1 =3D 0x11; - cpu->id_dfr0 =3D 0x33; + cpu->isar.id_dfr0 =3D 0x33; cpu->id_afr0 =3D 0; cpu->id_mmfr0 =3D 0x01130003; cpu->id_mmfr1 =3D 0x10030302; @@ -2052,7 +2052,7 @@ static void arm11mpcore_initfn(Object *obj) cpu->ctr =3D 0x1d192992; /* 32K icache 32K dcache */ cpu->id_pfr0 =3D 0x111; cpu->id_pfr1 =3D 0x1; - cpu->id_dfr0 =3D 0; + cpu->isar.id_dfr0 =3D 0; cpu->id_afr0 =3D 0x2; cpu->id_mmfr0 =3D 0x01100103; cpu->id_mmfr1 =3D 0x10020302; @@ -2084,7 +2084,7 @@ static void cortex_m3_initfn(Object *obj) cpu->pmsav7_dregion =3D 8; cpu->id_pfr0 =3D 0x00000030; cpu->id_pfr1 =3D 0x00000200; - cpu->id_dfr0 =3D 0x00100000; + cpu->isar.id_dfr0 =3D 0x00100000; cpu->id_afr0 =3D 0x00000000; cpu->id_mmfr0 =3D 0x00000030; cpu->id_mmfr1 =3D 0x00000000; @@ -2115,7 +2115,7 @@ static void cortex_m4_initfn(Object *obj) cpu->isar.mvfr2 =3D 0x00000000; cpu->id_pfr0 =3D 0x00000030; cpu->id_pfr1 =3D 0x00000200; - cpu->id_dfr0 =3D 0x00100000; + cpu->isar.id_dfr0 =3D 0x00100000; cpu->id_afr0 =3D 0x00000000; cpu->id_mmfr0 =3D 0x00000030; cpu->id_mmfr1 =3D 0x00000000; @@ -2146,7 +2146,7 @@ static void cortex_m7_initfn(Object *obj) cpu->isar.mvfr2 =3D 0x00000040; cpu->id_pfr0 =3D 0x00000030; cpu->id_pfr1 =3D 0x00000200; - cpu->id_dfr0 =3D 0x00100000; + cpu->isar.id_dfr0 =3D 0x00100000; cpu->id_afr0 =3D 0x00000000; cpu->id_mmfr0 =3D 0x00100030; cpu->id_mmfr1 =3D 0x00000000; @@ -2179,7 +2179,7 @@ static void cortex_m33_initfn(Object *obj) cpu->isar.mvfr2 =3D 0x00000040; cpu->id_pfr0 =3D 0x00000030; cpu->id_pfr1 =3D 0x00000210; - cpu->id_dfr0 =3D 0x00200000; + cpu->isar.id_dfr0 =3D 0x00200000; cpu->id_afr0 =3D 0x00000000; cpu->id_mmfr0 =3D 0x00101F40; cpu->id_mmfr1 =3D 0x00000000; @@ -2231,7 +2231,7 @@ static void cortex_r5_initfn(Object *obj) cpu->midr =3D 0x411fc153; /* r1p3 */ cpu->id_pfr0 =3D 0x0131; cpu->id_pfr1 =3D 0x001; - cpu->id_dfr0 =3D 0x010400; + cpu->isar.id_dfr0 =3D 0x010400; cpu->id_afr0 =3D 0x0; cpu->id_mmfr0 =3D 0x0210030; cpu->id_mmfr1 =3D 0x00000000; @@ -2286,7 +2286,7 @@ static void cortex_a8_initfn(Object *obj) cpu->reset_sctlr =3D 0x00c50078; cpu->id_pfr0 =3D 0x1031; cpu->id_pfr1 =3D 0x11; - cpu->id_dfr0 =3D 0x400; + cpu->isar.id_dfr0 =3D 0x400; cpu->id_afr0 =3D 0; cpu->id_mmfr0 =3D 0x31100003; cpu->id_mmfr1 =3D 0x20000000; @@ -2359,7 +2359,7 @@ static void cortex_a9_initfn(Object *obj) cpu->reset_sctlr =3D 0x00c50078; cpu->id_pfr0 =3D 0x1031; cpu->id_pfr1 =3D 0x11; - cpu->id_dfr0 =3D 0x000; + cpu->isar.id_dfr0 =3D 0x000; cpu->id_afr0 =3D 0; cpu->id_mmfr0 =3D 0x00100103; cpu->id_mmfr1 =3D 0x20000000; @@ -2424,7 +2424,7 @@ static void cortex_a7_initfn(Object *obj) cpu->reset_sctlr =3D 0x00c50078; cpu->id_pfr0 =3D 0x00001131; cpu->id_pfr1 =3D 0x00011011; - cpu->id_dfr0 =3D 0x02010555; + cpu->isar.id_dfr0 =3D 0x02010555; cpu->id_afr0 =3D 0x00000000; cpu->id_mmfr0 =3D 0x10101105; cpu->id_mmfr1 =3D 0x40000000; @@ -2470,7 +2470,7 @@ static void cortex_a15_initfn(Object *obj) cpu->reset_sctlr =3D 0x00c50078; cpu->id_pfr0 =3D 0x00001131; cpu->id_pfr1 =3D 0x00011011; - cpu->id_dfr0 =3D 0x02010555; + cpu->isar.id_dfr0 =3D 0x02010555; cpu->id_afr0 =3D 0x00000000; cpu->id_mmfr0 =3D 0x10201105; cpu->id_mmfr1 =3D 0x20000000; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index f0d98bc79d1..9e4387158f9 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -121,7 +121,7 @@ static void aarch64_a57_initfn(Object *obj) cpu->reset_sctlr =3D 0x00c50838; cpu->id_pfr0 =3D 0x00000131; cpu->id_pfr1 =3D 0x00011011; - cpu->id_dfr0 =3D 0x03010066; + cpu->isar.id_dfr0 =3D 0x03010066; cpu->id_afr0 =3D 0x00000000; cpu->id_mmfr0 =3D 0x10101105; cpu->id_mmfr1 =3D 0x40000000; @@ -175,7 +175,7 @@ static void aarch64_a53_initfn(Object *obj) cpu->reset_sctlr =3D 0x00c50838; cpu->id_pfr0 =3D 0x00000131; cpu->id_pfr1 =3D 0x00011011; - cpu->id_dfr0 =3D 0x03010066; + cpu->isar.id_dfr0 =3D 0x03010066; cpu->id_afr0 =3D 0x00000000; cpu->id_mmfr0 =3D 0x10101105; cpu->id_mmfr1 =3D 0x40000000; @@ -228,7 +228,7 @@ static void aarch64_a72_initfn(Object *obj) cpu->reset_sctlr =3D 0x00c50838; cpu->id_pfr0 =3D 0x00000131; cpu->id_pfr1 =3D 0x00011011; - cpu->id_dfr0 =3D 0x03010066; + cpu->isar.id_dfr0 =3D 0x03010066; cpu->id_afr0 =3D 0x00000000; cpu->id_mmfr0 =3D 0x10201105; cpu->id_mmfr1 =3D 0x40000000; diff --git a/target/arm/helper.c b/target/arm/helper.c index 376c6412f91..048e541eda4 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6381,8 +6381,7 @@ static void define_pmu_regs(ARMCPU *cpu) g_free(pmevtyper_name); g_free(pmevtyper_el0_name); } - if (FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) >=3D 4 && - FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) !=3D 0xf) { + if (cpu_isar_feature(aa32_pmu_8_1, cpu)) { ARMCPRegInfo v81_pmu_regs[] =3D { { .name =3D "PMCEID2", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D = 4, @@ -6856,7 +6855,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 2, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->id_dfr0 }, + .resetvalue =3D cpu->isar.id_dfr0 }, { .name =3D "ID_AFR0", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 3, .access =3D PL1_R, .type =3D ARM_CP_CONST, --=20 2.20.1 From nobody Mon May 6 22:28:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581702881584667.0434119268222; Fri, 14 Feb 2020 09:54:41 -0800 (PST) Received: from localhost ([::1]:42860 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2fAm-0004cD-CZ for importer@patchew.org; Fri, 14 Feb 2020 12:54:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56033) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2f7n-0005w5-Q3 for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:38 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j2f7l-0000nt-LF for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:35 -0500 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:35101) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j2f7l-0000mx-DM for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:33 -0500 Received: by mail-wm1-x342.google.com with SMTP id b17so11574825wmb.0 for ; Fri, 14 Feb 2020 09:51:33 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id v8sm8001857wrw.2.2020.02.14.09.51.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Feb 2020 09:51:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+1O468aAsxmPMNL3BnoErATUsLcXthstaq/0XPSyqIo=; b=pRc2ibr7hwdg7dOwW7sck4nbEns5BsaLDD5UjjoRG5XzfEjjlM/DoMyFIXpmrLKqu6 yE7JG+khoOFZlz59eejFI6CyeCqOASRz0R95cKfczdMVkr0mp+17vp/rW8G0oxOrNwph 0fU2bDNB4DhJK5jBfmwPbAtap1cuNwa7ZOyNu2ofOxly1nuDVwmHJtDc5m0o8t6P+pmI VU3v+9hpRh4RforROyWVvC68jS78apqrrH30+ggSu06YLPIz777adSm2O7T1VRT2EZRa nvz13Zk5ppkwq29WBguuk3+n4kGI0TFUTPicZh7bSWOLBHCxJLZjXtVrzbngMiqiDf2h fqaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+1O468aAsxmPMNL3BnoErATUsLcXthstaq/0XPSyqIo=; b=p5g0bnhO6/22Fv5ONtR8QoByg5ZzR3Jn8OTY9bGRAZU7HSHkB3meXAxQdoIdr0DAfo n8y7PhHqQlWuDklOz1OnVrDuCy2vSQb0sf3ackUf6OH9Txe+tNWYbp0gFKYIWkFAuWPD Tx3v8CfQGAtMesUi9sB0QDygsEgeacSaQVrLrMRmZkBZN5B2IWiNmGOQ+4wboibWtRny aGkOtECOgazgH8dmVaFGehokI2+AJyrjWjO5L/vRkNVqhvsh5efoFZBJDPhXknDmUZbA A5/lxbO4gQHQrRLjsxYVhVPKMvv+Q8Ftbp5JgsB5XVyc+gfKzx+gya2KJ22mo63qKlmb sVSw== X-Gm-Message-State: APjAAAVTKLdz3TEZhEMfXHKdfvyzRYnbzQ6ga1rOX4x94SJBuO4CHRt8 kHNhg89lW3IQjZNpVcg2a7pScg== X-Google-Smtp-Source: APXvYqx2NuTvtEu1u99ZLy6wm57Pjz7Tv4bVfE19Gg+YQIJbMgYi+T2YFEaEmLMZMpfhcSp9iqtZ1w== X-Received: by 2002:a1c:9e13:: with SMTP id h19mr5956238wme.21.1581702692467; Fri, 14 Feb 2020 09:51:32 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 09/21] target/arm: Add _aa64_ and _any_ versions of pmu_8_1 isar checks Date: Fri, 14 Feb 2020 17:51:04 +0000 Message-Id: <20200214175116.9164-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200214175116.9164-1-peter.maydell@linaro.org> References: <20200214175116.9164-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eric Auger , Aaron Lindsay , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Add the 64-bit version of the "is this a v8.1 PMUv3?" ID register check function, and the _any_ version that checks for either AArch32 or AArch64 support. We'll use this in a later commit. We don't (yet) do any isar_feature checks on ID_AA64DFR1_EL1, but we move id_aa64dfr1 into the ARMISARegisters struct with id_aa64dfr0, for consistency. Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- v1->v2: * fix use of FIELD_EX32 in _aa64_ function --- target/arm/cpu.h | 15 +++++++++++++-- target/arm/cpu.c | 3 ++- target/arm/cpu64.c | 6 +++--- target/arm/helper.c | 12 +++++++----- 4 files changed, 25 insertions(+), 11 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 6c6088eb587..98240224c0c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -873,6 +873,8 @@ struct ARMCPU { uint64_t id_aa64mmfr0; uint64_t id_aa64mmfr1; uint64_t id_aa64mmfr2; + uint64_t id_aa64dfr0; + uint64_t id_aa64dfr1; } isar; uint32_t midr; uint32_t revidr; @@ -889,8 +891,6 @@ struct ARMCPU { uint32_t id_mmfr2; uint32_t id_mmfr3; uint32_t id_mmfr4; - uint64_t id_aa64dfr0; - uint64_t id_aa64dfr1; uint64_t id_aa64afr0; uint64_t id_aa64afr1; uint32_t dbgdidr; @@ -3686,6 +3686,12 @@ static inline bool isar_feature_aa64_bti(const ARMIS= ARegisters *id) return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) !=3D 0; } =20 +static inline bool isar_feature_aa64_pmu_8_1(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >=3D 4 && + FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) !=3D 0xf; +} + /* * Feature tests for "does this exist in either 32-bit or 64-bit?" */ @@ -3699,6 +3705,11 @@ static inline bool isar_feature_any_predinv(const AR= MISARegisters *id) return isar_feature_aa64_predinv(id) || isar_feature_aa32_predinv(id); } =20 +static inline bool isar_feature_any_pmu_8_1(const ARMISARegisters *id) +{ + return isar_feature_aa64_pmu_8_1(id) || isar_feature_aa32_pmu_8_1(id); +} + /* * Forward to the above feature tests given an ARMCPU pointer. */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index b85040d36bc..7759e0f9329 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1718,7 +1718,8 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) cpu); #endif } else { - cpu->id_aa64dfr0 =3D FIELD_DP64(cpu->id_aa64dfr0, ID_AA64DFR0, PMU= VER, 0); + cpu->isar.id_aa64dfr0 =3D + FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0); cpu->isar.id_dfr0 =3D FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFM= ON, 0); cpu->pmceid0 =3D 0; cpu->pmceid1 =3D 0; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 9e4387158f9..2030e5e384b 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -135,7 +135,7 @@ static void aarch64_a57_initfn(Object *obj) cpu->isar.id_isar5 =3D 0x00011121; cpu->isar.id_isar6 =3D 0; cpu->isar.id_aa64pfr0 =3D 0x00002222; - cpu->id_aa64dfr0 =3D 0x10305106; + cpu->isar.id_aa64dfr0 =3D 0x10305106; cpu->isar.id_aa64isar0 =3D 0x00011120; cpu->isar.id_aa64mmfr0 =3D 0x00001124; cpu->dbgdidr =3D 0x3516d000; @@ -189,7 +189,7 @@ static void aarch64_a53_initfn(Object *obj) cpu->isar.id_isar5 =3D 0x00011121; cpu->isar.id_isar6 =3D 0; cpu->isar.id_aa64pfr0 =3D 0x00002222; - cpu->id_aa64dfr0 =3D 0x10305106; + cpu->isar.id_aa64dfr0 =3D 0x10305106; cpu->isar.id_aa64isar0 =3D 0x00011120; cpu->isar.id_aa64mmfr0 =3D 0x00001122; /* 40 bit physical addr */ cpu->dbgdidr =3D 0x3516d000; @@ -241,7 +241,7 @@ static void aarch64_a72_initfn(Object *obj) cpu->isar.id_isar4 =3D 0x00011142; cpu->isar.id_isar5 =3D 0x00011121; cpu->isar.id_aa64pfr0 =3D 0x00002222; - cpu->id_aa64dfr0 =3D 0x10305106; + cpu->isar.id_aa64dfr0 =3D 0x10305106; cpu->isar.id_aa64isar0 =3D 0x00011120; cpu->isar.id_aa64mmfr0 =3D 0x00001124; cpu->dbgdidr =3D 0x3516d000; diff --git a/target/arm/helper.c b/target/arm/helper.c index 048e541eda4..11b87723e47 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -25,6 +25,7 @@ #include "hw/semihosting/semihost.h" #include "sysemu/cpus.h" #include "sysemu/kvm.h" +#include "sysemu/tcg.h" #include "qemu/range.h" #include "qapi/qapi-commands-machine-target.h" #include "qapi/error.h" @@ -6266,9 +6267,10 @@ static void define_debug_regs(ARMCPU *cpu) * check that if they both exist then they agree. */ if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - assert(FIELD_EX64(cpu->id_aa64dfr0, ID_AA64DFR0, BRPS) =3D=3D brps= ); - assert(FIELD_EX64(cpu->id_aa64dfr0, ID_AA64DFR0, WRPS) =3D=3D wrps= ); - assert(FIELD_EX64(cpu->id_aa64dfr0, ID_AA64DFR0, CTX_CMPS) =3D=3D = ctx_cmps); + assert(FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, BRPS) =3D=3D= brps); + assert(FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, WRPS) =3D=3D= wrps); + assert(FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS) + =3D=3D ctx_cmps); } =20 define_one_arm_cp_reg(cpu, &dbgdidr); @@ -7010,12 +7012,12 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 0, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->id_aa64dfr0 }, + .resetvalue =3D cpu->isar.id_aa64dfr0 }, { .name =3D "ID_AA64DFR1_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 1, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->id_aa64dfr1 }, + .resetvalue =3D cpu->isar.id_aa64dfr1 }, { .name =3D "ID_AA64DFR2_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 2, .access =3D PL1_R, .type =3D ARM_CP_CONST, --=20 2.20.1 From nobody Mon May 6 22:28:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 15817028003144.4320922790211625; Fri, 14 Feb 2020 09:53:20 -0800 (PST) Received: from localhost ([::1]:42792 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2f9T-0000nr-01 for importer@patchew.org; Fri, 14 Feb 2020 12:53:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56046) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2f7o-0005wb-92 for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:37 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j2f7m-0000p7-RM for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:36 -0500 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]:53791) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j2f7m-0000oH-KI for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:34 -0500 Received: by mail-wm1-x335.google.com with SMTP id s10so10844383wmh.3 for ; Fri, 14 Feb 2020 09:51:34 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id v8sm8001857wrw.2.2020.02.14.09.51.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Feb 2020 09:51:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+RSZKscRdCamXAJ0k30/EyUeGISH+9TDKdteY9Rg/DM=; b=LHd69Z9/E6GbSWIp12Y1fRT6SW8N7Yh8hivs/KTO/v6k1xYl46xC4xfH0aZnceSYt7 QWbvXHvYXXZnryA4BDZj2gAWBy8QmzmkzzRF4ZmmgABKySk8kdbVH0JIwH138MnuKVNA AK2f2g5VstRGczRCOlDzyhHl+0DzPP0DNLHBXNLYFETqe7ObT91TzsiFr83rpwfCIDjW IDlrXh5692JXzmJRL3O2WtQQSsQL8jB4f7od+f/lmW6Al+b8HHjnyv61iqmZWZkIHi0O aYu0NnMZ5w73iKKjMC7TgssmqgWDEhQb8T1dTHiawvul7OQMTEtWdbwRH0HwQiB2kyiR zQ1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+RSZKscRdCamXAJ0k30/EyUeGISH+9TDKdteY9Rg/DM=; b=c0AwIpAQgs8hKViM2XgUjapAiqiBFhnVeHDpSN3MTntLfvUO+0FG6OFk6/78UJKCSl poDchrLc4Wmt7c+qJtRVZGWVdp9Yt/UIltbYaZw0F1FnbmI2mpQwK0RAyQ7SYRN1pEoc 9XbTPnL/2WDWRRnpPq75i/BWvSRQNird1SlP4yFHwyYwJhfNiROAZzvGVbBq5rqJ6dPD cFATHXjJO1mafskoDn9uc/g/WhQ/mdNpnITxFm0s+Fsc7YLjV94byPhIlvVoKEN7ZDkB 1sEDZRI7pv9q8Lizr6spESor89bl10V+5dgOJwS/x66W/bnaQcS5c5ACTX6+XpgCJYW9 PHAw== X-Gm-Message-State: APjAAAUmJaEQL8rcLx0FEDYyFcrbXsYiGuVpHgs68sKRMYueuFI/X2FJ 6wVo2GEBtspiPNzNIdSNIwn5Kg== X-Google-Smtp-Source: APXvYqzlEVGLRn00WqLArkcqinPKewDZWVKDTCAhf8FlkuJ2QG2cMi5qTOMSGCvuoQzwvdknnPaQ+w== X-Received: by 2002:a05:600c:21c5:: with SMTP id x5mr6013917wmj.72.1581702693533; Fri, 14 Feb 2020 09:51:33 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 10/21] target/arm: Stop assuming DBGDIDR always exists Date: Fri, 14 Feb 2020 17:51:05 +0000 Message-Id: <20200214175116.9164-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200214175116.9164-1-peter.maydell@linaro.org> References: <20200214175116.9164-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::335 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eric Auger , Aaron Lindsay , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The AArch32 DBGDIDR defines properties like the number of breakpoints, watchpoints and context-matching comparators. On an AArch64 CPU, the register may not even exist if AArch32 is not supported at EL1. Currently we hard-code use of DBGDIDR to identify the number of breakpoints etc; this works for all our TCG CPUs, but will break if we ever add an AArch64-only CPU. We also have an assert() that the AArch32 and AArch64 registers match, which currently works only by luck for KVM because we don't populate either of these ID registers from the KVM vCPU and so they are both zero. Clean this up so we have functions for finding the number of breakpoints, watchpoints and context comparators which look in the appropriate ID register. This allows us to drop the "check that AArch64 and AArch32 agree on the number of breakpoints etc" asserts: * we no longer look at the AArch32 versions unless that's the right place to be looking * it's valid to have a CPU (eg AArch64-only) where they don't match * we shouldn't have been asserting the validity of ID registers in a codepath used with KVM anyway Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 7 +++++++ target/arm/internals.h | 42 +++++++++++++++++++++++++++++++++++++++ target/arm/debug_helper.c | 6 +++--- target/arm/helper.c | 21 +++++--------------- 4 files changed, 57 insertions(+), 19 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 98240224c0c..0f21b6ed803 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1840,6 +1840,13 @@ FIELD(ID_DFR0, MPROFDBG, 20, 4) FIELD(ID_DFR0, PERFMON, 24, 4) FIELD(ID_DFR0, TRACEFILT, 28, 4) =20 +FIELD(DBGDIDR, SE_IMP, 12, 1) +FIELD(DBGDIDR, NSUHD_IMP, 14, 1) +FIELD(DBGDIDR, VERSION, 16, 4) +FIELD(DBGDIDR, CTX_CMPS, 20, 4) +FIELD(DBGDIDR, BRPS, 24, 4) +FIELD(DBGDIDR, WRPS, 28, 4) + FIELD(MVFR0, SIMDREG, 0, 4) FIELD(MVFR0, FPSP, 4, 4) FIELD(MVFR0, FPDP, 8, 4) diff --git a/target/arm/internals.h b/target/arm/internals.h index 052449b4826..39239186def 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -931,6 +931,48 @@ static inline uint32_t arm_debug_exception_fsr(CPUARMS= tate *env) } } =20 +/** + * arm_num_brps: Return number of implemented breakpoints. + * Note that the ID register BRPS field is "number of bps - 1", + * and we return the actual number of breakpoints. + */ +static inline int arm_num_brps(ARMCPU *cpu) +{ + if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { + return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, BRPS) + 1; + } else { + return FIELD_EX32(cpu->dbgdidr, DBGDIDR, BRPS) + 1; + } +} + +/** + * arm_num_wrps: Return number of implemented watchpoints. + * Note that the ID register WRPS field is "number of wps - 1", + * and we return the actual number of watchpoints. + */ +static inline int arm_num_wrps(ARMCPU *cpu) +{ + if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { + return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, WRPS) + 1; + } else { + return FIELD_EX32(cpu->dbgdidr, DBGDIDR, WRPS) + 1; + } +} + +/** + * arm_num_ctx_cmps: Return number of implemented context comparators. + * Note that the ID register CTX_CMPS field is "number of cmps - 1", + * and we return the actual number of comparators. + */ +static inline int arm_num_ctx_cmps(ARMCPU *cpu) +{ + if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { + return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS) + = 1; + } else { + return FIELD_EX32(cpu->dbgdidr, DBGDIDR, CTX_CMPS) + 1; + } +} + /* Note make_memop_idx reserves 4 bits for mmu_idx, and MO_BSWAP is bit 3. * Thus a TCGMemOpIdx, without any MO_ALIGN bits, fits in 8 bits. */ diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 2e3e90c6a57..2ff72d47d19 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -16,8 +16,8 @@ static bool linked_bp_matches(ARMCPU *cpu, int lbn) { CPUARMState *env =3D &cpu->env; uint64_t bcr =3D env->cp15.dbgbcr[lbn]; - int brps =3D extract32(cpu->dbgdidr, 24, 4); - int ctx_cmps =3D extract32(cpu->dbgdidr, 20, 4); + int brps =3D arm_num_brps(cpu); + int ctx_cmps =3D arm_num_ctx_cmps(cpu); int bt; uint32_t contextidr; uint64_t hcr_el2; @@ -29,7 +29,7 @@ static bool linked_bp_matches(ARMCPU *cpu, int lbn) * case DBGWCR_EL1.LBN must indicate that breakpoint). * We choose the former. */ - if (lbn > brps || lbn < (brps - ctx_cmps)) { + if (lbn >=3D brps || lbn < (brps - ctx_cmps)) { return false; } =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index 11b87723e47..8415cc6b154 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6256,23 +6256,12 @@ static void define_debug_regs(ARMCPU *cpu) }; =20 /* Note that all these register fields hold "number of Xs minus 1". */ - brps =3D extract32(cpu->dbgdidr, 24, 4); - wrps =3D extract32(cpu->dbgdidr, 28, 4); - ctx_cmps =3D extract32(cpu->dbgdidr, 20, 4); + brps =3D arm_num_brps(cpu); + wrps =3D arm_num_wrps(cpu); + ctx_cmps =3D arm_num_ctx_cmps(cpu); =20 assert(ctx_cmps <=3D brps); =20 - /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties - * of the debug registers such as number of breakpoints; - * check that if they both exist then they agree. - */ - if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - assert(FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, BRPS) =3D=3D= brps); - assert(FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, WRPS) =3D=3D= wrps); - assert(FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS) - =3D=3D ctx_cmps); - } - define_one_arm_cp_reg(cpu, &dbgdidr); define_arm_cp_regs(cpu, debug_cp_reginfo); =20 @@ -6280,7 +6269,7 @@ static void define_debug_regs(ARMCPU *cpu) define_arm_cp_regs(cpu, debug_lpae_cp_reginfo); } =20 - for (i =3D 0; i < brps + 1; i++) { + for (i =3D 0; i < brps; i++) { ARMCPRegInfo dbgregs[] =3D { { .name =3D "DBGBVR", .state =3D ARM_CP_STATE_BOTH, .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D i= , .opc2 =3D 4, @@ -6299,7 +6288,7 @@ static void define_debug_regs(ARMCPU *cpu) define_arm_cp_regs(cpu, dbgregs); } =20 - for (i =3D 0; i < wrps + 1; i++) { + for (i =3D 0; i < wrps; i++) { ARMCPRegInfo dbgregs[] =3D { { .name =3D "DBGWVR", .state =3D ARM_CP_STATE_BOTH, .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D i= , .opc2 =3D 6, --=20 2.20.1 From nobody Mon May 6 22:28:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581703018046863.328340385726; Fri, 14 Feb 2020 09:56:58 -0800 (PST) Received: from localhost ([::1]:42950 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2fCy-0000EN-PV for importer@patchew.org; Fri, 14 Feb 2020 12:56:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56121) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2f7t-0005ya-9o for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j2f7q-0000sB-Tx for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:40 -0500 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:35079) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j2f7o-0000pL-7K for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:37 -0500 Received: by mail-wr1-x444.google.com with SMTP id w12so11894048wrt.2 for ; Fri, 14 Feb 2020 09:51:35 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id v8sm8001857wrw.2.2020.02.14.09.51.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Feb 2020 09:51:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dw/oKtuPvdBDo/uw+ysmB9G26Zom6TRdfrmN+nZGS2g=; b=Ph7WIM0M+/oaSmorCsXPKgJGq8/zc+TGGs6DkwcMRbCJBSgdJMpIW8B7reKxumnrZ/ h0/x2oBl+N4apaqLU68eGKd28nieZ2Tmw4seXx43rnZLWQpHNNo7DhP7g4MVrhGfn/X5 NHALJoSAYhzG0nGnXbtdSJoLKxrT987so8TxDQDEijvLPbtDPDvGidh23o2JDQDEZy6o UnHR4PIzOsFzoBxO8yfDYuqIRx6ZtrVhUytGqtw2tyvVNZdIVolzXUZTHEZ7MBw5Ry7X fNKiKsgHxsYkf5mAvpKzrIJm6xUDOMkUGipFaZPltMtoUSTPoVFdCezLHYAFpZ4gFxxo h0Jw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dw/oKtuPvdBDo/uw+ysmB9G26Zom6TRdfrmN+nZGS2g=; b=j3fChaaDMF9UsccOqROdveFPb1Pmm0bhSRVcoqS1Fr+vUTdL4Lt48VxTDs4eaz84jI wzYnUrMxrDvAl8H0G0txQ5CO3q+ymesi5ro3wFaIO1s/Lp/+kvVSkrr8uk0rZ5aNO9R3 dtjPF19VGa4jiILR/pk2p3qSZNd+CA5HBq8hXU78vSoCvGFvY/BKktWtuLNajuuQS/vt lcFKWblGHO24eiRh4qDxnOpxCKn+ZwuQjnPehkw/NlXgAAlyObtE6RK69FIFuMugV6+1 keSGdKjo/XG0rb3FZ+GIeSeybopyPCEkixeysQZknSGR2ecs/BhtEGUmbCNIlQ42HwlZ 3ZRw== X-Gm-Message-State: APjAAAVaIPs7AFNHUfWu7d1pUN5ddM46ZGHn4nuyhmcnDzJuggdqe+Ly FmeI1lfABFuSpvUBGnvSeqkjlBtLVvw= X-Google-Smtp-Source: APXvYqx0nG2dlKhQr8/DJURN9S3a50yxke21GtXA0kNrNU5qe8Mt3g8EZHOgw3rmvF2wFFM3Q0i9xw== X-Received: by 2002:adf:fe50:: with SMTP id m16mr5400914wrs.217.1581702694862; Fri, 14 Feb 2020 09:51:34 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 11/21] target/arm: Move DBGDIDR into ARMISARegisters Date: Fri, 14 Feb 2020 17:51:06 +0000 Message-Id: <20200214175116.9164-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200214175116.9164-1-peter.maydell@linaro.org> References: <20200214175116.9164-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eric Auger , Aaron Lindsay , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" We're going to want to read the DBGDIDR register from KVM in a subsequent commit, which means it needs to be in the ARMISARegisters sub-struct. Move it. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 2 +- target/arm/internals.h | 6 +++--- target/arm/cpu.c | 8 ++++---- target/arm/cpu64.c | 6 +++--- target/arm/helper.c | 2 +- 5 files changed, 12 insertions(+), 12 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0f21b6ed803..3c996db3e45 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -866,6 +866,7 @@ struct ARMCPU { uint32_t mvfr1; uint32_t mvfr2; uint32_t id_dfr0; + uint32_t dbgdidr; uint64_t id_aa64isar0; uint64_t id_aa64isar1; uint64_t id_aa64pfr0; @@ -893,7 +894,6 @@ struct ARMCPU { uint32_t id_mmfr4; uint64_t id_aa64afr0; uint64_t id_aa64afr1; - uint32_t dbgdidr; uint32_t clidr; uint64_t mp_affinity; /* MP ID without feature bits */ /* The elements of this array are the CCSIDR values for each cache, diff --git a/target/arm/internals.h b/target/arm/internals.h index 39239186def..309d2f4ea95 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -941,7 +941,7 @@ static inline int arm_num_brps(ARMCPU *cpu) if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, BRPS) + 1; } else { - return FIELD_EX32(cpu->dbgdidr, DBGDIDR, BRPS) + 1; + return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, BRPS) + 1; } } =20 @@ -955,7 +955,7 @@ static inline int arm_num_wrps(ARMCPU *cpu) if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, WRPS) + 1; } else { - return FIELD_EX32(cpu->dbgdidr, DBGDIDR, WRPS) + 1; + return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, WRPS) + 1; } } =20 @@ -969,7 +969,7 @@ static inline int arm_num_ctx_cmps(ARMCPU *cpu) if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS) + = 1; } else { - return FIELD_EX32(cpu->dbgdidr, DBGDIDR, CTX_CMPS) + 1; + return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, CTX_CMPS) + 1; } } =20 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 7759e0f9329..f58b4da4427 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2298,7 +2298,7 @@ static void cortex_a8_initfn(Object *obj) cpu->isar.id_isar2 =3D 0x21232031; cpu->isar.id_isar3 =3D 0x11112131; cpu->isar.id_isar4 =3D 0x00111142; - cpu->dbgdidr =3D 0x15141000; + cpu->isar.dbgdidr =3D 0x15141000; cpu->clidr =3D (1 << 27) | (2 << 24) | 3; cpu->ccsidr[0] =3D 0xe007e01a; /* 16k L1 dcache. */ cpu->ccsidr[1] =3D 0x2007e01a; /* 16k L1 icache. */ @@ -2371,7 +2371,7 @@ static void cortex_a9_initfn(Object *obj) cpu->isar.id_isar2 =3D 0x21232041; cpu->isar.id_isar3 =3D 0x11112131; cpu->isar.id_isar4 =3D 0x00111142; - cpu->dbgdidr =3D 0x35141000; + cpu->isar.dbgdidr =3D 0x35141000; cpu->clidr =3D (1 << 27) | (1 << 24) | 3; cpu->ccsidr[0] =3D 0xe00fe019; /* 16k L1 dcache. */ cpu->ccsidr[1] =3D 0x200fe019; /* 16k L1 icache. */ @@ -2439,7 +2439,7 @@ static void cortex_a7_initfn(Object *obj) cpu->isar.id_isar2 =3D 0x21232041; cpu->isar.id_isar3 =3D 0x11112131; cpu->isar.id_isar4 =3D 0x10011142; - cpu->dbgdidr =3D 0x3515f005; + cpu->isar.dbgdidr =3D 0x3515f005; cpu->clidr =3D 0x0a200023; cpu->ccsidr[0] =3D 0x701fe00a; /* 32K L1 dcache */ cpu->ccsidr[1] =3D 0x201fe00a; /* 32K L1 icache */ @@ -2482,7 +2482,7 @@ static void cortex_a15_initfn(Object *obj) cpu->isar.id_isar2 =3D 0x21232041; cpu->isar.id_isar3 =3D 0x11112131; cpu->isar.id_isar4 =3D 0x10011142; - cpu->dbgdidr =3D 0x3515f021; + cpu->isar.dbgdidr =3D 0x3515f021; cpu->clidr =3D 0x0a200023; cpu->ccsidr[0] =3D 0x701fe00a; /* 32K L1 dcache */ cpu->ccsidr[1] =3D 0x201fe00a; /* 32K L1 icache */ diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 2030e5e384b..f8f74a7ecda 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -138,7 +138,7 @@ static void aarch64_a57_initfn(Object *obj) cpu->isar.id_aa64dfr0 =3D 0x10305106; cpu->isar.id_aa64isar0 =3D 0x00011120; cpu->isar.id_aa64mmfr0 =3D 0x00001124; - cpu->dbgdidr =3D 0x3516d000; + cpu->isar.dbgdidr =3D 0x3516d000; cpu->clidr =3D 0x0a200023; cpu->ccsidr[0] =3D 0x701fe00a; /* 32KB L1 dcache */ cpu->ccsidr[1] =3D 0x201fe012; /* 48KB L1 icache */ @@ -192,7 +192,7 @@ static void aarch64_a53_initfn(Object *obj) cpu->isar.id_aa64dfr0 =3D 0x10305106; cpu->isar.id_aa64isar0 =3D 0x00011120; cpu->isar.id_aa64mmfr0 =3D 0x00001122; /* 40 bit physical addr */ - cpu->dbgdidr =3D 0x3516d000; + cpu->isar.dbgdidr =3D 0x3516d000; cpu->clidr =3D 0x0a200023; cpu->ccsidr[0] =3D 0x700fe01a; /* 32KB L1 dcache */ cpu->ccsidr[1] =3D 0x201fe00a; /* 32KB L1 icache */ @@ -244,7 +244,7 @@ static void aarch64_a72_initfn(Object *obj) cpu->isar.id_aa64dfr0 =3D 0x10305106; cpu->isar.id_aa64isar0 =3D 0x00011120; cpu->isar.id_aa64mmfr0 =3D 0x00001124; - cpu->dbgdidr =3D 0x3516d000; + cpu->isar.dbgdidr =3D 0x3516d000; cpu->clidr =3D 0x0a200023; cpu->ccsidr[0] =3D 0x701fe00a; /* 32KB L1 dcache */ cpu->ccsidr[1] =3D 0x201fe012; /* 48KB L1 icache */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 8415cc6b154..1dcbb68e49b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6252,7 +6252,7 @@ static void define_debug_regs(ARMCPU *cpu) ARMCPRegInfo dbgdidr =3D { .name =3D "DBGDIDR", .cp =3D 14, .crn =3D 0, .crm =3D 0, .opc1 =3D= 0, .opc2 =3D 0, .access =3D PL0_R, .accessfn =3D access_tda, - .type =3D ARM_CP_CONST, .resetvalue =3D cpu->dbgdidr, + .type =3D ARM_CP_CONST, .resetvalue =3D cpu->isar.dbgdidr, }; =20 /* Note that all these register fields hold "number of Xs minus 1". */ --=20 2.20.1 From nobody Mon May 6 22:28:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581703105641266.60416400621034; Fri, 14 Feb 2020 09:58:25 -0800 (PST) Received: from localhost ([::1]:43006 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2fEN-00030N-Pn for importer@patchew.org; Fri, 14 Feb 2020 12:58:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56134) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2f7t-0005zY-IV for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j2f7s-0000tJ-5p for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:41 -0500 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]:51700) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j2f7r-0000qT-BZ for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:39 -0500 Received: by mail-wm1-x344.google.com with SMTP id t23so10844421wmi.1 for ; Fri, 14 Feb 2020 09:51:37 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id v8sm8001857wrw.2.2020.02.14.09.51.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Feb 2020 09:51:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xVgyB/ZnMXDEzGcspXK1d/y3x9zIzwGPMhddTki8nJw=; b=wMB5gPIeIBSbzlWph6ShtV/PNXzq8bXUx0A7jxEzpExrFvZHZ75yikbukDUu2FgTeB Yte4fS0s+KULHfzRy+GZeD0kmUdCvUn/HSqgevlg28BrSUaIaTj64IoAUxuN38aMvJfT wluZ9eeBOXLw0HdjzhFVtlmurvUjfFUUH+u7x0SH0Ve5oH91tJsPY6423qebavtL85p7 eEiO4OjEwKXxwLCbLuxlmoibYf4yhQJSVIJ+NSD+h0P2u+gAAnw8pLI9VPi/XOmKNOwp 0psbaZ7mxhR/3THr39f6NQjF39kvnMq9/MYo68ERpOGmj1SO53cHr7r8gHuGsv5wAJ9g 6EDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xVgyB/ZnMXDEzGcspXK1d/y3x9zIzwGPMhddTki8nJw=; b=fUnmuG9oprKGrRfqsjia2vimw6WmMg4iC3FC3mBYw8uf6T/CJW96slS3cU0I5ZEhKV ORfkwVpGnvt85DnIRh7FNRqfZj1sDUBRD+u2yxRSlknrF0PgJ0Q7QqLdnTzO85Ki85WZ fhPPZjXYj2vGCeeCAfbBaEw8EU8thSoDbF/qux0b2PwG7UFBteZDbaV8P0pyJbEhHBXI Vj5qjNzGOXkrR5U8NwbWABQulM6L/fHDgsRiJHgBT5Rdxu9KJfKNu9nJXemj6fje31Xg XY6lHDgjrg+pKozFu1ijP7K07rLu+EbABjVRFoKDfzhgHKEk18EE3PEvrXvgDZNSikx3 I8bA== X-Gm-Message-State: APjAAAX1QVnXeQNGC0BT/AsKskmWete4q/DI2BdNNp9BStTexrGJyQmy EXrJduroZGeDRKTIWqvQFw0UJogCMj0= X-Google-Smtp-Source: APXvYqwYZSAfold6XYOIh8pypchVbtZxxRL45ahfE4Td1GUeAUl8GNQgwh0exVMHyXiDnV7AMEmG5w== X-Received: by 2002:a1c:6645:: with SMTP id a66mr6124713wmc.121.1581702696443; Fri, 14 Feb 2020 09:51:36 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 12/21] target/arm: Read debug-related ID registers from KVM Date: Fri, 14 Feb 2020 17:51:07 +0000 Message-Id: <20200214175116.9164-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200214175116.9164-1-peter.maydell@linaro.org> References: <20200214175116.9164-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eric Auger , Aaron Lindsay , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Now we have isar_feature test functions that look at fields in the ID_AA64DFR0_EL1 and ID_DFR0 ID registers, add the code that reads these register values from KVM so that the checks behave correctly when we're using KVM. No isar_feature function tests ID_AA64DFR1_EL1 or DBGDIDR yet, but we add it to maintain the invariant that every field in the ARMISARegisters struct is populated for a KVM CPU and can be relied on. This requirement isn't actually written down yet, so add a note to the relevant comment. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 5 +++++ target/arm/kvm32.c | 8 ++++++++ target/arm/kvm64.c | 36 ++++++++++++++++++++++++++++++++++++ 3 files changed, 49 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 3c996db3e45..e043932fcb1 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -853,6 +853,11 @@ struct ARMCPU { * prefix means a constant register. * Some of these registers are split out into a substructure that * is shared with the translators to control the ISA. + * + * Note that if you add an ID register to the ARMISARegisters struct + * you need to also update the 32-bit and 64-bit versions of the + * kvm_arm_get_host_cpu_features() function to correctly populate the + * field by reading the value from the KVM vCPU. */ struct ARMISARegisters { uint32_t id_isar0; diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c index 3a8b437eef0..bca02553b25 100644 --- a/target/arm/kvm32.c +++ b/target/arm/kvm32.c @@ -97,6 +97,9 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ah= cf) ahcf->isar.id_isar6 =3D 0; } =20 + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0, + ARM_CP15_REG32(0, 0, 1, 2)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0, KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR0); @@ -108,6 +111,11 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures = *ahcf) * Fortunately there is not yet anything in there that affects migrati= on. */ =20 + /* + * There is no way to read DBGDIDR, because currently 32-bit KVM + * doesn't implement debug at all. Leave it at zero. + */ + kvm_arm_destroy_scratch_host_vcpu(fdarray); =20 if (err < 0) { diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 3bae9e4a663..527532f2b37 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -541,6 +541,10 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures = *ahcf) } else { err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr1, ARM64_SYS_REG(3, 0, 0, 4, 1)); + err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr0, + ARM64_SYS_REG(3, 0, 0, 5, 0)); + err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr1, + ARM64_SYS_REG(3, 0, 0, 5, 1)); err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar0, ARM64_SYS_REG(3, 0, 0, 6, 0)); err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar1, @@ -559,6 +563,8 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *= ahcf) * than skipping the reads and leaving 0, as we must avoid * considering the values in every case. */ + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0, + ARM64_SYS_REG(3, 0, 0, 1, 2)); err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0, ARM64_SYS_REG(3, 0, 0, 2, 0)); err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1, @@ -580,6 +586,36 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures = *ahcf) ARM64_SYS_REG(3, 0, 0, 3, 1)); err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr2, ARM64_SYS_REG(3, 0, 0, 3, 2)); + + /* + * DBGDIDR is a bit complicated because the kernel doesn't + * provide an accessor for it in 64-bit mode, which is what this + * scratch VM is in, and there's no architected "64-bit sysreg + * which reads the same as the 32-bit register" the way there is + * for other ID registers. Instead we synthesize a value from the + * AArch64 ID_AA64DFR0, the same way the kernel code in + * arch/arm64/kvm/sys_regs.c:trap_dbgidr() does. + * We only do this if the CPU supports AArch32 at EL1. + */ + if (FIELD_EX32(ahcf->isar.id_aa64pfr0, ID_AA64PFR0, EL1) >=3D 2) { + int wrps =3D FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, W= RPS); + int brps =3D FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, B= RPS); + int ctx_cmps =3D + FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS); + int version =3D 6; /* ARMv8 debug architecture */ + bool has_el3 =3D + !!FIELD_EX32(ahcf->isar.id_aa64pfr0, ID_AA64PFR0, EL3); + uint32_t dbgdidr =3D 0; + + dbgdidr =3D FIELD_DP32(dbgdidr, DBGDIDR, WRPS, wrps); + dbgdidr =3D FIELD_DP32(dbgdidr, DBGDIDR, BRPS, brps); + dbgdidr =3D FIELD_DP32(dbgdidr, DBGDIDR, CTX_CMPS, ctx_cmps); + dbgdidr =3D FIELD_DP32(dbgdidr, DBGDIDR, VERSION, version); + dbgdidr =3D FIELD_DP32(dbgdidr, DBGDIDR, NSUHD_IMP, has_el3); + dbgdidr =3D FIELD_DP32(dbgdidr, DBGDIDR, SE_IMP, has_el3); + dbgdidr |=3D (1 << 16); /* RES1 bit */ + ahcf->isar.dbgdidr =3D dbgdidr; + } } =20 sve_supported =3D ioctl(fdarray[0], KVM_CHECK_EXTENSION, KVM_CAP_ARM_S= VE) > 0; --=20 2.20.1 From nobody Mon May 6 22:28:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581702922022360.48925550013996; Fri, 14 Feb 2020 09:55:22 -0800 (PST) Received: from localhost ([::1]:42886 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2fBQ-000607-PG for importer@patchew.org; Fri, 14 Feb 2020 12:55:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56133) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2f7t-0005zX-IR for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:42 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j2f7s-0000tY-B1 for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:41 -0500 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:38304) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j2f7r-0000r5-Bg for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:39 -0500 Received: by mail-wr1-x441.google.com with SMTP id y17so11882871wrh.5 for ; Fri, 14 Feb 2020 09:51:38 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id v8sm8001857wrw.2.2020.02.14.09.51.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Feb 2020 09:51:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NSiQxcnFeKC6KyTWn4PrMXJIxie/Z4B9EArp8D5QAn8=; b=RvtWl+Sw/xPf0OPNkF8GhOHy0Pr5fEtuJE/ULYUvFUJ6pUJD0MQkU4CcycAaXVNJVq MaTzds596dr78mdCdeczzUCWzqI1tCe2GJDpLgOu4BLFDjE2KOluOvg3cQaDm/IPEQoC zXuHSW7NssQ4wnvqPpJrcgmr3mnFYVjZgPGl14l1gQuM3PcVx8LTEloRHoqi1kkA3X8y yWYP+AWezwP+Oq5pLwWibMrGsqT3NSQy6Tc/Rb9iDrzPjYHn5hovaEWCzqgO4eD+yuCv e32aBWKBOUjroIt+ewgluz7SlZuopCTPzRD7zYp4pzXHSYJmevXS7Ixu2c5XmZr0wP80 FBhQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NSiQxcnFeKC6KyTWn4PrMXJIxie/Z4B9EArp8D5QAn8=; b=PNOscJ/oAwOro9nW0YgbAgZ0N5hRBL/oavWRxU3grLKSoe/TSsNKcFU7pmuqGe0dSv 64rGPMAElnkC3DZgsm0HWfAtSNwBA4HvMiTgsVVdoHymmUrHKdTxb5W9o940+sPnKD2H V7JwJ6SXQjwBRLxMA7uulMpnaUeO6F8UJwFzC63nWsj4V/wDuPS89MEDMjiQoWAQPwiL WW0XprycMYgFUCc8+PYqGU8n6ZgTjqrACb7C+SpjqBjDvPWUapsZICk2/8seWGN3bXtg HqfG/FFC8E191t9dWDAm4fGkDXcrqoCNYN/6lXuRvjS23/LXyEA8pv9l/hTDIBxFoBNS 0h6w== X-Gm-Message-State: APjAAAWE/IDSJAc7PYa/TsaOyn4MLHlMbbDOrm18aConTDqJ9TbHjEOZ kbc3ed+srD4PJBE7g1wk3IQpKA== X-Google-Smtp-Source: APXvYqzJqfJA2DVaLgR+Y9wk1UPuU/scrob9S2QNSABfP54nuPo+zDbZX18zakRdL6yMYweappelkA== X-Received: by 2002:adf:dd0b:: with SMTP id a11mr5462852wrm.150.1581702697631; Fri, 14 Feb 2020 09:51:37 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 13/21] target/arm: Implement ARMv8.1-PMU extension Date: Fri, 14 Feb 2020 17:51:08 +0000 Message-Id: <20200214175116.9164-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200214175116.9164-1-peter.maydell@linaro.org> References: <20200214175116.9164-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eric Auger , Aaron Lindsay , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The ARMv8.1-PMU extension requires: * the evtCount field in PMETYPER_EL0 is 16 bits, not 10 * MDCR_EL2.HPMD allows event counting to be disabled at EL2 * two new required events, STALL_FRONTEND and STALL_BACKEND * ID register bits in ID_AA64DFR0_EL1 and ID_DFR0 We already implement the 16-bit evtCount field and the HPMD bit, so all that is missing is the two new events: STALL_FRONTEND "counts every cycle counted by the CPU_CYCLES event on which no operation was issued because there are no operations available to issue to this PE from the frontend" STALL_BACKEND "counts every cycle counted by the CPU_CYCLES event on which no operation was issued because the backend is unable to accept any available operations from the frontend" QEMU never stalls in this sense, so our implementation is trivial: always return a zero count. Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell --- target/arm/helper.c | 32 ++++++++++++++++++++++++++++++-- 1 file changed, 30 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 1dcbb68e49b..aeb01617150 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1124,6 +1124,24 @@ static int64_t instructions_ns_per(uint64_t icount) } #endif =20 +static bool pmu_8_1_events_supported(CPUARMState *env) +{ + /* For events which are supported in any v8.1 PMU */ + return cpu_isar_feature(any_pmu_8_1, env_archcpu(env)); +} + +static uint64_t zero_event_get_count(CPUARMState *env) +{ + /* For events which on QEMU never fire, so their count is always zero = */ + return 0; +} + +static int64_t zero_event_ns_per(uint64_t cycles) +{ + /* An event which never fires can never overflow */ + return -1; +} + static const pm_event pm_events[] =3D { { .number =3D 0x000, /* SW_INCR */ .supported =3D event_always_supported, @@ -1140,8 +1158,18 @@ static const pm_event pm_events[] =3D { .supported =3D event_always_supported, .get_count =3D cycles_get_count, .ns_per_count =3D cycles_ns_per, - } + }, #endif + { .number =3D 0x023, /* STALL_FRONTEND */ + .supported =3D pmu_8_1_events_supported, + .get_count =3D zero_event_get_count, + .ns_per_count =3D zero_event_ns_per, + }, + { .number =3D 0x024, /* STALL_BACKEND */ + .supported =3D pmu_8_1_events_supported, + .get_count =3D zero_event_get_count, + .ns_per_count =3D zero_event_ns_per, + }, }; =20 /* @@ -1150,7 +1178,7 @@ static const pm_event pm_events[] =3D { * should first be updated to something sparse instead of the current * supported_event_map[] array. */ -#define MAX_EVENT_ID 0x11 +#define MAX_EVENT_ID 0x24 #define UNSUPPORTED_EVENT UINT16_MAX static uint16_t supported_event_map[MAX_EVENT_ID + 1]; =20 --=20 2.20.1 From nobody Mon May 6 22:28:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581703440249894.1729453506164; Fri, 14 Feb 2020 10:04:00 -0800 (PST) Received: from localhost ([::1]:43158 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2fJl-0003E9-OB for importer@patchew.org; Fri, 14 Feb 2020 13:03:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56212) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2f7w-00064p-4d for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j2f7t-0000up-7I for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:43 -0500 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:46886) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j2f7s-0000sV-5R for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:40 -0500 Received: by mail-wr1-x443.google.com with SMTP id z7so11872841wrl.13 for ; Fri, 14 Feb 2020 09:51:39 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id v8sm8001857wrw.2.2020.02.14.09.51.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Feb 2020 09:51:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4BLXsVcN28YFgzh7RunR4by8doFHHVtIkmiy7Jly1NU=; b=bJq6wSO64nQ7655iHrQy8uQ33zF92z6mllFOsd9mCZz9w/YAosZY/9qPsG69XByf4u ZcANLz6nOXrvhQJi4Ybn0eQTHvzbNrNUS8Qf3srvCqzUfQ96ycljrzhaalZYE3CKdpcr BDuP5yjRB9ClLPtg/a7/yseWhUV3a4vRBun+5dT/4Vm5lQLybz6KOZ4yps4GI82zDs22 qojNNb4P3LxD69VBsrF4G1xF2dldKCKJ396BUQF/JMkTSRBIZMiwvA8+fsDpMp/RiLuX z+uN9q/Y2105JXkzLHHyoEU/fneulHwbP8nsDSgnebVUQ1BAXfvpKEahMUAr2Z1DNgkt GZug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4BLXsVcN28YFgzh7RunR4by8doFHHVtIkmiy7Jly1NU=; b=qXu3+wDEH0a5fxem9WJd/zy9c8iuehUZLsp8YYT7GS/TPubytAn12DRcpb5RXwCZAh Tak849R983/0q6S81L5k+1zgILcKhvNnSPqZjPCozWk/Ndztxmf7KCBN/Oq0vBXVpIyH UVODNRgb3WWo9Goufdluob230N+BM9fkr6zlOfW37EZxwnylr1gXdyzXpiEdbovseWcU bpKy/5pLc5no4/JfZn2LOH5gIRJrjWj8Zn2hBT4tR/MYJsiCXgJYKmGI6wIhC6W/rTAt yi+gFHUoQJKloP+0OUYQT+yWxDorMg1UFQOMeF9YY9H8Ee9Sryd3tkYFQ+3FOqOJn4BO uuWg== X-Gm-Message-State: APjAAAWGrh3lKbQrXAv4LNOYunhyTgqM3ulnvwJndTsVWBm6Z/3O6cGY Bbp/RfnnHq0TWB/XermCHy58Qluymts= X-Google-Smtp-Source: APXvYqyAtnb4zGMsTJryfLntnFWOYcBV/xbFG14HBh7YCfI8bZDOSFdCgeWO3rOBAI6QaC0dtygT9w== X-Received: by 2002:adf:b64b:: with SMTP id i11mr5502856wre.58.1581702698797; Fri, 14 Feb 2020 09:51:38 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 14/21] target/arm: Implement ARMv8.4-PMU extension Date: Fri, 14 Feb 2020 17:51:09 +0000 Message-Id: <20200214175116.9164-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200214175116.9164-1-peter.maydell@linaro.org> References: <20200214175116.9164-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eric Auger , Aaron Lindsay , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The ARMv8.4-PMU extension adds: * one new required event, STALL * one new system register PMMIR_EL1 (There are also some more L1-cache related events, but since we don't implement any cache we don't provide these, in the same way we don't provide the base-PMUv3 cache events.) The STALL event "counts every attributable cycle on which no attributable instruction or operation was sent for execution on this PE". QEMU doesn't stall in this sense, so this is another always-reads-zero event. The PMMIR_EL1 register is a read-only register providing implementation-specific information about the PMU; currently it has only one field, SLOTS, which defines behaviour of the STALL_SLOT PMU event. Since QEMU doesn't implement the STALL_SLOT event, we can validly make the register read zero. Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell --- target/arm/cpu.h | 18 ++++++++++++++++++ target/arm/helper.c | 22 +++++++++++++++++++++- 2 files changed, 39 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e043932fcb1..cfa9fd6c1b9 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3519,6 +3519,13 @@ static inline bool isar_feature_aa32_pmu_8_1(const A= RMISARegisters *id) FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) !=3D 0xf; } =20 +static inline bool isar_feature_aa32_pmu_8_4(const ARMISARegisters *id) +{ + /* 0xf means "non-standard IMPDEF PMU" */ + return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >=3D 5 && + FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) !=3D 0xf; +} + /* * 64-bit feature tests via id registers. */ @@ -3704,6 +3711,12 @@ static inline bool isar_feature_aa64_pmu_8_1(const A= RMISARegisters *id) FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) !=3D 0xf; } =20 +static inline bool isar_feature_aa64_pmu_8_4(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >=3D 5 && + FIELD_EX32(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) !=3D 0xf; +} + /* * Feature tests for "does this exist in either 32-bit or 64-bit?" */ @@ -3722,6 +3735,11 @@ static inline bool isar_feature_any_pmu_8_1(const AR= MISARegisters *id) return isar_feature_aa64_pmu_8_1(id) || isar_feature_aa32_pmu_8_1(id); } =20 +static inline bool isar_feature_any_pmu_8_4(const ARMISARegisters *id) +{ + return isar_feature_aa64_pmu_8_4(id) || isar_feature_aa32_pmu_8_4(id); +} + /* * Forward to the above feature tests given an ARMCPU pointer. */ diff --git a/target/arm/helper.c b/target/arm/helper.c index aeb01617150..2feded1518c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1130,6 +1130,12 @@ static bool pmu_8_1_events_supported(CPUARMState *en= v) return cpu_isar_feature(any_pmu_8_1, env_archcpu(env)); } =20 +static bool pmu_8_4_events_supported(CPUARMState *env) +{ + /* For events which are supported in any v8.1 PMU */ + return cpu_isar_feature(any_pmu_8_4, env_archcpu(env)); +} + static uint64_t zero_event_get_count(CPUARMState *env) { /* For events which on QEMU never fire, so their count is always zero = */ @@ -1170,6 +1176,11 @@ static const pm_event pm_events[] =3D { .get_count =3D zero_event_get_count, .ns_per_count =3D zero_event_ns_per, }, + { .number =3D 0x03c, /* STALL */ + .supported =3D pmu_8_4_events_supported, + .get_count =3D zero_event_get_count, + .ns_per_count =3D zero_event_ns_per, + }, }; =20 /* @@ -1178,7 +1189,7 @@ static const pm_event pm_events[] =3D { * should first be updated to something sparse instead of the current * supported_event_map[] array. */ -#define MAX_EVENT_ID 0x24 +#define MAX_EVENT_ID 0x3c #define UNSUPPORTED_EVENT UINT16_MAX static uint16_t supported_event_map[MAX_EVENT_ID + 1]; =20 @@ -6414,6 +6425,15 @@ static void define_pmu_regs(ARMCPU *cpu) }; define_arm_cp_regs(cpu, v81_pmu_regs); } + if (cpu_isar_feature(any_pmu_8_4, cpu)) { + static const ARMCPRegInfo v84_pmmir =3D { + .name =3D "PMMIR_EL1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D 6, + .access =3D PL1_R, .accessfn =3D pmreg_access, .type =3D ARM_C= P_CONST, + .resetvalue =3D 0 + }; + define_one_arm_cp_reg(cpu, &v84_pmmir); + } } =20 /* We don't know until after realize whether there's a GICv3 --=20 2.20.1 From nobody Mon May 6 22:28:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581703234438317.942080486676; Fri, 14 Feb 2020 10:00:34 -0800 (PST) Received: from localhost ([::1]:43046 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2fGH-0005YW-2E for importer@patchew.org; Fri, 14 Feb 2020 13:00:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56208) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2f7v-00064a-V8 for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j2f7t-0000wG-Fy for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:42 -0500 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:35103) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j2f7t-0000tP-7V for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:41 -0500 Received: by mail-wm1-x343.google.com with SMTP id b17so11575236wmb.0 for ; Fri, 14 Feb 2020 09:51:40 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id v8sm8001857wrw.2.2020.02.14.09.51.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Feb 2020 09:51:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VbLItfxzzwVIogOn7W2BSKPPHmmspgIMmaJYOYePbHA=; b=NcHHIMcrfMMDyIWzSxccuCJZQIr4b2c9J6b/8eEQ6kX6D4/KeCDV4KyvZ7Y88F8A6g QTGojyP3Sl2htawQ8RGQ0U00aF8SDOVytmOd8LBqqpmMXd7o7hPwPqCA8fuLLPpvlHGO kcJyxjAcOMcV+oPyNoB2zabt7YA/Rz9LBhbH2lxrsS/W2aTLKCSMT4eDsQBUt4UdiakM XtdqEXrLFHzfPYBLAyrWfTE1Msmy9fuG0+U5Di1MjAD4Ai3uuVKTwAX9vkVsIGYciIHF 1PL6dnjVJmN9VYxipwjgAhtUWQflXcRWo3QRnSArQhfaaHVLPBhRmJLwAhgkXOnVwy7B 2m1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VbLItfxzzwVIogOn7W2BSKPPHmmspgIMmaJYOYePbHA=; b=pWhVj9aDdLyqfEHES4XmkhOlAz03xa3dXMkcPXfCrdzFl1hpTXICsyv+Mc25sOhim5 XFptsQFs+m0Yhk7/ucF1CM7PyXGwNueiXQ2OGLYEYZNsJcz5QwSUH4yugIuy4tqbAwwq RKmE4i5NMgaE0wZ1bOMXz9EpQmkvvA2GjZc50PjYtgRSMnpl7rLXzXDu5ZZmnj7V1xqG OljTEHkQz1C7J64TYXJdz+XetLwPfU7+hS8O1oskPDRVTPwg87qNSm8nMqs96cTxs4ix 0arFgqCEnW38fL8iYRjEps5TBzk8mzAM2Y2HePe217hlew8VLTCebPs9U24W2mvb9kJA /gSw== X-Gm-Message-State: APjAAAX88R6UxHp4ixj5lQ2Gb5Wzq5+TRHWJklT3VtVRp0hCPO5/hzkD ZxgeEgWoRPGkBLFj4HfR/9peYg== X-Google-Smtp-Source: APXvYqw0IUGZmGesAQ4cxyEP3kKbZKKR2Sgxzv6pMnIOngCoFxiVHhYjStl1GwlxQa0OKnaod8IuMw== X-Received: by 2002:a7b:c416:: with SMTP id k22mr6069503wmi.10.1581702699939; Fri, 14 Feb 2020 09:51:39 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 15/21] target/arm: Provide ARMv8.4-PMU in '-cpu max' Date: Fri, 14 Feb 2020 17:51:10 +0000 Message-Id: <20200214175116.9164-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200214175116.9164-1-peter.maydell@linaro.org> References: <20200214175116.9164-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eric Auger , Aaron Lindsay , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Set the ID register bits to provide ARMv8.4-PMU (and implicitly also ARMv8.1-PMU) in the 'max' CPU. Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell --- v1->v2: use FIELD_DP64 for 64-bit idreg --- target/arm/cpu64.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index f8f74a7ecda..c9452894035 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -703,6 +703,14 @@ static void aarch64_max_initfn(Object *obj) u =3D FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */ cpu->id_mmfr3 =3D u; =20 + u =3D cpu->isar.id_aa64dfr0; + u =3D FIELD_DP64(u, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */ + cpu->isar.id_aa64dfr0 =3D u; + + u =3D cpu->isar.id_dfr0; + u =3D FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ + cpu->isar.id_dfr0 =3D u; + /* * FIXME: We do not yet support ARMv8.2-fp16 for AArch32 yet, * so do not set MVFR1.FPHP. Strictly speaking this is not legal, --=20 2.20.1 From nobody Mon May 6 22:28:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581703342210428.1231404358466; Fri, 14 Feb 2020 10:02:22 -0800 (PST) Received: from localhost ([::1]:43114 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2fIC-00005i-P6 for importer@patchew.org; Fri, 14 Feb 2020 13:02:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56217) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2f7w-00064v-Cn for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j2f7u-0000yV-4l for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:43 -0500 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:42751) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j2f7t-0000vY-UJ for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:42 -0500 Received: by mail-wr1-x444.google.com with SMTP id k11so11876547wrd.9 for ; Fri, 14 Feb 2020 09:51:41 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id v8sm8001857wrw.2.2020.02.14.09.51.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Feb 2020 09:51:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5mQrhAitCaw5RJP1dOPrlxLmDz4jgnDL2MRmgAJnH5M=; b=mhVWUbZC1r417E2WBJRppYnXh+oa3UhaBZaPXQ2um10Xhq0mDR/gQIll9X5WyBzlyA jzGcm33iRJu6CIaab75gZ03feDNF9W8K393MpXCTzbcLdfXX+hhuSZpHxoROw2ffwufs 7fzQQtXtXuKtSaVoJLOhpaZzQ9BrNlZW0C7PN0HV7n3sn3WZnZOUZaYyLSAq1MtCUQ90 iFFlmy7l/Fu82NEDs6qN3vlDB1RHw7/Pf2m+sm4oZZx1fE0Szpp09uoMmhpHaLG/hHZD cz5HvdcAcehr74vmH+TXhtzgrXkKq9wjUU2jZA+VzlKn6Ozxi9MSssUJb54/ZVeR9+Ex 03wQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5mQrhAitCaw5RJP1dOPrlxLmDz4jgnDL2MRmgAJnH5M=; b=H9m6IgsvP6REkKkp50kLTmvRGJRujsOpgUMt/Pqhr26OJYCYm+tzxwJk4VCnhvzNv2 fCsr7jeVdpKeo0qzfy4AdjYf+uDuZvT+0M13fZfYefW/AKjVQDC/6qWWpVpTfzsKDrx9 jvTSfj0cxd6LqRK7hKJIresclbGY6zUNSnHSqwQvdvWooaxi6AsA+Ic19oKrdxCVTXaY YT/DZrNUPKoT4zIfaVVAWbInQlkufY3s5dRLZLj5Q4LUcMF6Y3Ro0ID9dAUl3miH17QV BMR+ujA/201AUxdYruPLxSL7jRfDpKD08bz0D1gRSOQR8xbU4eQQ0odgh5xzZZ/I9me0 A32w== X-Gm-Message-State: APjAAAUZcGCjkYn3cXAAQcwxHCOiaKv4KNndCKN0MX6ul6OEYZIU2LNo RZLWD5npqlKbMlcji9sT63kHpghL1I4= X-Google-Smtp-Source: APXvYqz3gYgWNr/GT/bTIJCoA3+GqfVcQNpY6DAOrtW7VGOn3P0MYHWrvWmZ8b0Vdah47HB0lkiEDQ== X-Received: by 2002:a5d:474b:: with SMTP id o11mr5342789wrs.255.1581702701013; Fri, 14 Feb 2020 09:51:41 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 16/21] target/arm: Correct definition of PMCRDP Date: Fri, 14 Feb 2020 17:51:11 +0000 Message-Id: <20200214175116.9164-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200214175116.9164-1-peter.maydell@linaro.org> References: <20200214175116.9164-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eric Auger , Aaron Lindsay , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) The PMCR_EL0.DP bit is bit 5, which is 0x20, not 0x10. 0x10 is 'X'. Correct our #define of PMCRDP and add the missing PMCRX. We do have the correct behaviour for handling the DP bit being set, so this fixes a guest-visible bug. Fixes: 033614c47de Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell --- target/arm/helper.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 2feded1518c..2ebfa6c6545 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1017,7 +1017,8 @@ static const ARMCPRegInfo v6_cp_reginfo[] =3D { #define PMCRN_MASK 0xf800 #define PMCRN_SHIFT 11 #define PMCRLC 0x40 -#define PMCRDP 0x10 +#define PMCRDP 0x20 +#define PMCRX 0x10 #define PMCRD 0x8 #define PMCRC 0x4 #define PMCRP 0x2 --=20 2.20.1 From nobody Mon May 6 22:28:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581703415810412.6022002427063; Fri, 14 Feb 2020 10:03:35 -0800 (PST) Received: from localhost ([::1]:43154 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2fJO-0002lg-5N for importer@patchew.org; Fri, 14 Feb 2020 13:03:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56271) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2f7x-00069A-OC for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j2f7w-00015L-Ij for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:45 -0500 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:40899) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j2f7w-0000zN-Bh for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:44 -0500 Received: by mail-wm1-x343.google.com with SMTP id t14so11551442wmi.5 for ; Fri, 14 Feb 2020 09:51:43 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id v8sm8001857wrw.2.2020.02.14.09.51.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Feb 2020 09:51:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vPNGprCOMcg0mBZ7UWesyY+l4Nq3dOFKdfD9K6E8o5Y=; b=fZ/DlAqoLG6noh2KEyBpJOnoWSqe8nLugbokpyEiB+RCEud6RDqwBJCWa18Ygo+zVv uj9B2KfA18hBmI6o920dald9AxfPdUOBAbACJ9uQS50xzdbSgppAC5tkCd7DaTJAeGEf vi3UJEVAnBEgFl4MNTED9oz9Q082DrPCdSlOmwv9rxhSN8BsjEn5GjhIYHVPMsKi8Q83 nlyzFqPINTUTmDr0u6ctzxOThfZNP6m8509ELEYHBOwxsfmwufDugNGVHQWR8n4XGmud dzVmazI9r2+v7Jp1hcPsYEUoIRRw6PR9IGNRn+mkBFMxmEghGDA6IYssaOyHNtXkF4PK tsfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vPNGprCOMcg0mBZ7UWesyY+l4Nq3dOFKdfD9K6E8o5Y=; b=i+Nm5w2fMfuTFYaQ0qCOb61EN48tC7A1Mrsd486wVoce3MZ0jl0k102Q9yPJ2M4+Ry eAKEj8Vykk1RvHmpqoenXa8hnr+PlScw9EFpnmHohnslxUREqHRHBGy8m91Hg7aEfC1z qgSkVxUmAqJrzp8YhzyLaxQKv4e5m2NNEtn8uz84BLXopnJxYksDBW4cst80mWOSKZC9 PzdLi/YcODN314r06boejB1NWRrzCuiZCMNejwBDvglBcumsOQQqP6GW+1yZMiu0FFlG NfshxkES3pGcjb/EGDOBXn/FKXzGPoK2lS8GyEcg8QlMedG5D/iX/8x/EE7MBku7IJ+J Bd4w== X-Gm-Message-State: APjAAAUpNHp+PsL75Wz6jpDyGCJBI/Oupn3krRcyZhefR8+CjVPTPZVJ iNppiSr4sDt3QJIlv7qzeqzn2A== X-Google-Smtp-Source: APXvYqzx7EpzyD7roVoNtWBfLOfGKMFdJSOTZJTG7jEISbiBUY2RR172xi9wnNi2s7SCCB9cBlcGrw== X-Received: by 2002:a05:600c:294:: with SMTP id 20mr5973217wmk.135.1581702702178; Fri, 14 Feb 2020 09:51:42 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 17/21] target/arm: Correct handling of PMCR_EL0.LC bit Date: Fri, 14 Feb 2020 17:51:12 +0000 Message-Id: <20200214175116.9164-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200214175116.9164-1-peter.maydell@linaro.org> References: <20200214175116.9164-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eric Auger , Aaron Lindsay , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) The LC bit in the PMCR_EL0 register is supposed to be: * read/write * RES1 on an AArch64-only implementation * an architecturally UNKNOWN value on reset (and use of LC=3D=3D0 by software is deprecated). We were implementing it incorrectly as read-only always zero, though we do have all the code needed to test it and behave accordingly. Instead make it a read-write bit which resets to 1 always, which satisfies all the architectural requirements above. Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/helper.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 2ebfa6c6545..468e4e89848 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1023,6 +1023,11 @@ static const ARMCPRegInfo v6_cp_reginfo[] =3D { #define PMCRC 0x4 #define PMCRP 0x2 #define PMCRE 0x1 +/* + * Mask of PMCR bits writeable by guest (not including WO bits like C, P, + * which can be written as 1 to trigger behaviour but which stay RAZ). + */ +#define PMCR_WRITEABLE_MASK (PMCRLC | PMCRDP | PMCRX | PMCRD | PMCRE) =20 #define PMXEVTYPER_P 0x80000000 #define PMXEVTYPER_U 0x40000000 @@ -1577,9 +1582,8 @@ static void pmcr_write(CPUARMState *env, const ARMCPR= egInfo *ri, } } =20 - /* only the DP, X, D and E bits are writable */ - env->cp15.c9_pmcr &=3D ~0x39; - env->cp15.c9_pmcr |=3D (value & 0x39); + env->cp15.c9_pmcr &=3D ~PMCR_WRITEABLE_MASK; + env->cp15.c9_pmcr |=3D (value & PMCR_WRITEABLE_MASK); =20 pmu_op_finish(env); } @@ -6370,7 +6374,8 @@ static void define_pmu_regs(ARMCPU *cpu) .access =3D PL0_RW, .accessfn =3D pmreg_access, .type =3D ARM_CP_IO, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmcr), - .resetvalue =3D (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHIFT), + .resetvalue =3D (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHIFT) | + PMCRLC, .writefn =3D pmcr_write, .raw_writefn =3D raw_write, }; define_one_arm_cp_reg(cpu, &pmcr); --=20 2.20.1 From nobody Mon May 6 22:28:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581703005429193.43177515445393; Fri, 14 Feb 2020 09:56:45 -0800 (PST) Received: from localhost ([::1]:42946 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2fCl-0008Mj-1i for importer@patchew.org; Fri, 14 Feb 2020 12:56:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56311) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2f7z-0006Bu-4v for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j2f7w-00016S-VR for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:47 -0500 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:45251) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j2f7w-00013P-MI for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:44 -0500 Received: by mail-wr1-x441.google.com with SMTP id g3so11869408wrs.12 for ; Fri, 14 Feb 2020 09:51:44 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id v8sm8001857wrw.2.2020.02.14.09.51.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Feb 2020 09:51:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QJEg/HbNShyyNFEksYvrdPfffEtZWxgEaTJmxp/tP2k=; b=Yurh1NTFNOE5oCZEwGcmyWRnqazdAgcsag4w1y57LNSt/LDy25EahlXaxlZn0W27Dq d0+Bz28ws698PcPLsjBrFmzaoN6jY1+nrvALBF1HiUVmOa4VhYviQ72uJY0fRoAwnZg9 7OEoAfGlncXZP4Vzzu1fZjjDuQY4IMv7Jc7NTi+QUNRxprPCSl04+fdvV99GLSefMrI9 z/AUVbHH9E/LcNDA93D8myG3Vncjb7fjuKPfNdc+OEf7R62mBjV1noCTVFnIDPB8D95H TpKjMNrI+2lRxWvgqHGf9oR1WWlOLgALRMksH0jUap+7R3rlAwxs6zYVUAnx1rLKObDz 5yJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QJEg/HbNShyyNFEksYvrdPfffEtZWxgEaTJmxp/tP2k=; b=SWaAa+8ez/KZCJ5Py3QJtdGXNcAQqAccm62IB3da5miS8sDcdqFRfVDb7JoyL0GO/3 DiwzQo2Blcp6A4Qay8ABBa2VO3jAnk0pS+WxwDPQ/amsTrXZftdMlxlOuL6A2TjpaKGs TMAUNA8MurIYN4WfWu0h2ZWuPwqm/9Ag3l0ggkJlap9NoKine48xm+SvaFkxj64PlEEJ r/eebbRV2ZW97qiXz6qiKg2Dlz8G+B4Q9KvtDm1Il9VhPihCkhTq9hyQP6AfmxVA/22A zcLfZg1w2lUG/NvlW8gxB5fXlaD39OKVvxEBwZz4DOWlTu6ODN/GRQkNMLY5vBxn+2Ne 4uhg== X-Gm-Message-State: APjAAAXEjoTXZ70gzmthBFVmZxWthTTq6cIMBGPge7k4YofiQjeZDsXu uBRR3DG7Jr7DRQoGae41zLecuA== X-Google-Smtp-Source: APXvYqyrLjpUQdZgQLpydo3Cnc6g6jscV0sOLjWU58grOqEUIo/qZqPDo8ojdLRIxuwe5NgzeshUHw== X-Received: by 2002:adf:9c8d:: with SMTP id d13mr5493858wre.392.1581702703524; Fri, 14 Feb 2020 09:51:43 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 18/21] target/arm: Test correct register in aa32_pan and aa32_ats1e1 checks Date: Fri, 14 Feb 2020 17:51:13 +0000 Message-Id: <20200214175116.9164-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200214175116.9164-1-peter.maydell@linaro.org> References: <20200214175116.9164-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eric Auger , Aaron Lindsay , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The isar_feature_aa32_pan and isar_feature_aa32_ats1e1 functions are supposed to be testing fields in ID_MMFR3; but a cut-and-paste error meant we were looking at MVFR0 instead. Fix the functions to look at the right register; this requires us to move at least id_mmfr3 to the ARMISARegisters struct; we choose to move all the ID_MMFRn registers for consistency. Fixes: 3d6ad6bb466f Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 14 +++--- hw/intc/armv7m_nvic.c | 8 ++-- target/arm/cpu.c | 104 +++++++++++++++++++++--------------------- target/arm/cpu64.c | 28 ++++++------ target/arm/helper.c | 12 ++--- target/arm/kvm32.c | 17 +++++++ target/arm/kvm64.c | 10 ++++ 7 files changed, 110 insertions(+), 83 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index cfa9fd6c1b9..ba97fc75c1d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -867,6 +867,11 @@ struct ARMCPU { uint32_t id_isar4; uint32_t id_isar5; uint32_t id_isar6; + uint32_t id_mmfr0; + uint32_t id_mmfr1; + uint32_t id_mmfr2; + uint32_t id_mmfr3; + uint32_t id_mmfr4; uint32_t mvfr0; uint32_t mvfr1; uint32_t mvfr2; @@ -892,11 +897,6 @@ struct ARMCPU { uint64_t pmceid0; uint64_t pmceid1; uint32_t id_afr0; - uint32_t id_mmfr0; - uint32_t id_mmfr1; - uint32_t id_mmfr2; - uint32_t id_mmfr3; - uint32_t id_mmfr4; uint64_t id_aa64afr0; uint64_t id_aa64afr1; uint32_t clidr; @@ -3504,12 +3504,12 @@ static inline bool isar_feature_aa32_vminmaxnm(cons= t ARMISARegisters *id) =20 static inline bool isar_feature_aa32_pan(const ARMISARegisters *id) { - return FIELD_EX64(id->mvfr0, ID_MMFR3, PAN) !=3D 0; + return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) !=3D 0; } =20 static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id) { - return FIELD_EX64(id->mvfr0, ID_MMFR3, PAN) >=3D 2; + return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) >=3D 2; } =20 static inline bool isar_feature_aa32_pmu_8_1(const ARMISARegisters *id) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 5a403fc9704..22a43e49847 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1231,13 +1231,13 @@ static uint32_t nvic_readl(NVICState *s, uint32_t o= ffset, MemTxAttrs attrs) case 0xd4c: /* AFR0. */ return cpu->id_afr0; case 0xd50: /* MMFR0. */ - return cpu->id_mmfr0; + return cpu->isar.id_mmfr0; case 0xd54: /* MMFR1. */ - return cpu->id_mmfr1; + return cpu->isar.id_mmfr1; case 0xd58: /* MMFR2. */ - return cpu->id_mmfr2; + return cpu->isar.id_mmfr2; case 0xd5c: /* MMFR3. */ - return cpu->id_mmfr3; + return cpu->isar.id_mmfr3; case 0xd60: /* ISAR0. */ return cpu->isar.id_isar0; case 0xd64: /* ISAR1. */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index f58b4da4427..c46bb5a5c09 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1960,9 +1960,9 @@ static void arm1136_r2_initfn(Object *obj) cpu->id_pfr1 =3D 0x1; cpu->isar.id_dfr0 =3D 0x2; cpu->id_afr0 =3D 0x3; - cpu->id_mmfr0 =3D 0x01130003; - cpu->id_mmfr1 =3D 0x10030302; - cpu->id_mmfr2 =3D 0x01222110; + cpu->isar.id_mmfr0 =3D 0x01130003; + cpu->isar.id_mmfr1 =3D 0x10030302; + cpu->isar.id_mmfr2 =3D 0x01222110; cpu->isar.id_isar0 =3D 0x00140011; cpu->isar.id_isar1 =3D 0x12002111; cpu->isar.id_isar2 =3D 0x11231111; @@ -1992,9 +1992,9 @@ static void arm1136_initfn(Object *obj) cpu->id_pfr1 =3D 0x1; cpu->isar.id_dfr0 =3D 0x2; cpu->id_afr0 =3D 0x3; - cpu->id_mmfr0 =3D 0x01130003; - cpu->id_mmfr1 =3D 0x10030302; - cpu->id_mmfr2 =3D 0x01222110; + cpu->isar.id_mmfr0 =3D 0x01130003; + cpu->isar.id_mmfr1 =3D 0x10030302; + cpu->isar.id_mmfr2 =3D 0x01222110; cpu->isar.id_isar0 =3D 0x00140011; cpu->isar.id_isar1 =3D 0x12002111; cpu->isar.id_isar2 =3D 0x11231111; @@ -2025,9 +2025,9 @@ static void arm1176_initfn(Object *obj) cpu->id_pfr1 =3D 0x11; cpu->isar.id_dfr0 =3D 0x33; cpu->id_afr0 =3D 0; - cpu->id_mmfr0 =3D 0x01130003; - cpu->id_mmfr1 =3D 0x10030302; - cpu->id_mmfr2 =3D 0x01222100; + cpu->isar.id_mmfr0 =3D 0x01130003; + cpu->isar.id_mmfr1 =3D 0x10030302; + cpu->isar.id_mmfr2 =3D 0x01222100; cpu->isar.id_isar0 =3D 0x0140011; cpu->isar.id_isar1 =3D 0x12002111; cpu->isar.id_isar2 =3D 0x11231121; @@ -2055,9 +2055,9 @@ static void arm11mpcore_initfn(Object *obj) cpu->id_pfr1 =3D 0x1; cpu->isar.id_dfr0 =3D 0; cpu->id_afr0 =3D 0x2; - cpu->id_mmfr0 =3D 0x01100103; - cpu->id_mmfr1 =3D 0x10020302; - cpu->id_mmfr2 =3D 0x01222000; + cpu->isar.id_mmfr0 =3D 0x01100103; + cpu->isar.id_mmfr1 =3D 0x10020302; + cpu->isar.id_mmfr2 =3D 0x01222000; cpu->isar.id_isar0 =3D 0x00100011; cpu->isar.id_isar1 =3D 0x12002111; cpu->isar.id_isar2 =3D 0x11221011; @@ -2087,10 +2087,10 @@ static void cortex_m3_initfn(Object *obj) cpu->id_pfr1 =3D 0x00000200; cpu->isar.id_dfr0 =3D 0x00100000; cpu->id_afr0 =3D 0x00000000; - cpu->id_mmfr0 =3D 0x00000030; - cpu->id_mmfr1 =3D 0x00000000; - cpu->id_mmfr2 =3D 0x00000000; - cpu->id_mmfr3 =3D 0x00000000; + cpu->isar.id_mmfr0 =3D 0x00000030; + cpu->isar.id_mmfr1 =3D 0x00000000; + cpu->isar.id_mmfr2 =3D 0x00000000; + cpu->isar.id_mmfr3 =3D 0x00000000; cpu->isar.id_isar0 =3D 0x01141110; cpu->isar.id_isar1 =3D 0x02111000; cpu->isar.id_isar2 =3D 0x21112231; @@ -2118,10 +2118,10 @@ static void cortex_m4_initfn(Object *obj) cpu->id_pfr1 =3D 0x00000200; cpu->isar.id_dfr0 =3D 0x00100000; cpu->id_afr0 =3D 0x00000000; - cpu->id_mmfr0 =3D 0x00000030; - cpu->id_mmfr1 =3D 0x00000000; - cpu->id_mmfr2 =3D 0x00000000; - cpu->id_mmfr3 =3D 0x00000000; + cpu->isar.id_mmfr0 =3D 0x00000030; + cpu->isar.id_mmfr1 =3D 0x00000000; + cpu->isar.id_mmfr2 =3D 0x00000000; + cpu->isar.id_mmfr3 =3D 0x00000000; cpu->isar.id_isar0 =3D 0x01141110; cpu->isar.id_isar1 =3D 0x02111000; cpu->isar.id_isar2 =3D 0x21112231; @@ -2149,10 +2149,10 @@ static void cortex_m7_initfn(Object *obj) cpu->id_pfr1 =3D 0x00000200; cpu->isar.id_dfr0 =3D 0x00100000; cpu->id_afr0 =3D 0x00000000; - cpu->id_mmfr0 =3D 0x00100030; - cpu->id_mmfr1 =3D 0x00000000; - cpu->id_mmfr2 =3D 0x01000000; - cpu->id_mmfr3 =3D 0x00000000; + cpu->isar.id_mmfr0 =3D 0x00100030; + cpu->isar.id_mmfr1 =3D 0x00000000; + cpu->isar.id_mmfr2 =3D 0x01000000; + cpu->isar.id_mmfr3 =3D 0x00000000; cpu->isar.id_isar0 =3D 0x01101110; cpu->isar.id_isar1 =3D 0x02112000; cpu->isar.id_isar2 =3D 0x20232231; @@ -2182,10 +2182,10 @@ static void cortex_m33_initfn(Object *obj) cpu->id_pfr1 =3D 0x00000210; cpu->isar.id_dfr0 =3D 0x00200000; cpu->id_afr0 =3D 0x00000000; - cpu->id_mmfr0 =3D 0x00101F40; - cpu->id_mmfr1 =3D 0x00000000; - cpu->id_mmfr2 =3D 0x01000000; - cpu->id_mmfr3 =3D 0x00000000; + cpu->isar.id_mmfr0 =3D 0x00101F40; + cpu->isar.id_mmfr1 =3D 0x00000000; + cpu->isar.id_mmfr2 =3D 0x01000000; + cpu->isar.id_mmfr3 =3D 0x00000000; cpu->isar.id_isar0 =3D 0x01101110; cpu->isar.id_isar1 =3D 0x02212000; cpu->isar.id_isar2 =3D 0x20232232; @@ -2234,10 +2234,10 @@ static void cortex_r5_initfn(Object *obj) cpu->id_pfr1 =3D 0x001; cpu->isar.id_dfr0 =3D 0x010400; cpu->id_afr0 =3D 0x0; - cpu->id_mmfr0 =3D 0x0210030; - cpu->id_mmfr1 =3D 0x00000000; - cpu->id_mmfr2 =3D 0x01200000; - cpu->id_mmfr3 =3D 0x0211; + cpu->isar.id_mmfr0 =3D 0x0210030; + cpu->isar.id_mmfr1 =3D 0x00000000; + cpu->isar.id_mmfr2 =3D 0x01200000; + cpu->isar.id_mmfr3 =3D 0x0211; cpu->isar.id_isar0 =3D 0x02101111; cpu->isar.id_isar1 =3D 0x13112111; cpu->isar.id_isar2 =3D 0x21232141; @@ -2289,10 +2289,10 @@ static void cortex_a8_initfn(Object *obj) cpu->id_pfr1 =3D 0x11; cpu->isar.id_dfr0 =3D 0x400; cpu->id_afr0 =3D 0; - cpu->id_mmfr0 =3D 0x31100003; - cpu->id_mmfr1 =3D 0x20000000; - cpu->id_mmfr2 =3D 0x01202000; - cpu->id_mmfr3 =3D 0x11; + cpu->isar.id_mmfr0 =3D 0x31100003; + cpu->isar.id_mmfr1 =3D 0x20000000; + cpu->isar.id_mmfr2 =3D 0x01202000; + cpu->isar.id_mmfr3 =3D 0x11; cpu->isar.id_isar0 =3D 0x00101111; cpu->isar.id_isar1 =3D 0x12112111; cpu->isar.id_isar2 =3D 0x21232031; @@ -2362,10 +2362,10 @@ static void cortex_a9_initfn(Object *obj) cpu->id_pfr1 =3D 0x11; cpu->isar.id_dfr0 =3D 0x000; cpu->id_afr0 =3D 0; - cpu->id_mmfr0 =3D 0x00100103; - cpu->id_mmfr1 =3D 0x20000000; - cpu->id_mmfr2 =3D 0x01230000; - cpu->id_mmfr3 =3D 0x00002111; + cpu->isar.id_mmfr0 =3D 0x00100103; + cpu->isar.id_mmfr1 =3D 0x20000000; + cpu->isar.id_mmfr2 =3D 0x01230000; + cpu->isar.id_mmfr3 =3D 0x00002111; cpu->isar.id_isar0 =3D 0x00101111; cpu->isar.id_isar1 =3D 0x13112111; cpu->isar.id_isar2 =3D 0x21232041; @@ -2427,10 +2427,10 @@ static void cortex_a7_initfn(Object *obj) cpu->id_pfr1 =3D 0x00011011; cpu->isar.id_dfr0 =3D 0x02010555; cpu->id_afr0 =3D 0x00000000; - cpu->id_mmfr0 =3D 0x10101105; - cpu->id_mmfr1 =3D 0x40000000; - cpu->id_mmfr2 =3D 0x01240000; - cpu->id_mmfr3 =3D 0x02102211; + cpu->isar.id_mmfr0 =3D 0x10101105; + cpu->isar.id_mmfr1 =3D 0x40000000; + cpu->isar.id_mmfr2 =3D 0x01240000; + cpu->isar.id_mmfr3 =3D 0x02102211; /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but * table 4-41 gives 0x02101110, which includes the arm div insns. */ @@ -2473,10 +2473,10 @@ static void cortex_a15_initfn(Object *obj) cpu->id_pfr1 =3D 0x00011011; cpu->isar.id_dfr0 =3D 0x02010555; cpu->id_afr0 =3D 0x00000000; - cpu->id_mmfr0 =3D 0x10201105; - cpu->id_mmfr1 =3D 0x20000000; - cpu->id_mmfr2 =3D 0x01240000; - cpu->id_mmfr3 =3D 0x02102211; + cpu->isar.id_mmfr0 =3D 0x10201105; + cpu->isar.id_mmfr1 =3D 0x20000000; + cpu->isar.id_mmfr2 =3D 0x01240000; + cpu->isar.id_mmfr3 =3D 0x02102211; cpu->isar.id_isar0 =3D 0x02101110; cpu->isar.id_isar1 =3D 0x13112111; cpu->isar.id_isar2 =3D 0x21232041; @@ -2712,13 +2712,13 @@ static void arm_max_initfn(Object *obj) t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ cpu->isar.mvfr2 =3D t; =20 - t =3D cpu->id_mmfr3; + t =3D cpu->isar.id_mmfr3; t =3D FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ - cpu->id_mmfr3 =3D t; + cpu->isar.id_mmfr3 =3D t; =20 - t =3D cpu->id_mmfr4; + t =3D cpu->isar.id_mmfr4; t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ - cpu->id_mmfr4 =3D t; + cpu->isar.id_mmfr4 =3D t; } #endif } diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index c9452894035..8430d432943 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -123,10 +123,10 @@ static void aarch64_a57_initfn(Object *obj) cpu->id_pfr1 =3D 0x00011011; cpu->isar.id_dfr0 =3D 0x03010066; cpu->id_afr0 =3D 0x00000000; - cpu->id_mmfr0 =3D 0x10101105; - cpu->id_mmfr1 =3D 0x40000000; - cpu->id_mmfr2 =3D 0x01260000; - cpu->id_mmfr3 =3D 0x02102211; + cpu->isar.id_mmfr0 =3D 0x10101105; + cpu->isar.id_mmfr1 =3D 0x40000000; + cpu->isar.id_mmfr2 =3D 0x01260000; + cpu->isar.id_mmfr3 =3D 0x02102211; cpu->isar.id_isar0 =3D 0x02101110; cpu->isar.id_isar1 =3D 0x13112111; cpu->isar.id_isar2 =3D 0x21232042; @@ -177,10 +177,10 @@ static void aarch64_a53_initfn(Object *obj) cpu->id_pfr1 =3D 0x00011011; cpu->isar.id_dfr0 =3D 0x03010066; cpu->id_afr0 =3D 0x00000000; - cpu->id_mmfr0 =3D 0x10101105; - cpu->id_mmfr1 =3D 0x40000000; - cpu->id_mmfr2 =3D 0x01260000; - cpu->id_mmfr3 =3D 0x02102211; + cpu->isar.id_mmfr0 =3D 0x10101105; + cpu->isar.id_mmfr1 =3D 0x40000000; + cpu->isar.id_mmfr2 =3D 0x01260000; + cpu->isar.id_mmfr3 =3D 0x02102211; cpu->isar.id_isar0 =3D 0x02101110; cpu->isar.id_isar1 =3D 0x13112111; cpu->isar.id_isar2 =3D 0x21232042; @@ -230,10 +230,10 @@ static void aarch64_a72_initfn(Object *obj) cpu->id_pfr1 =3D 0x00011011; cpu->isar.id_dfr0 =3D 0x03010066; cpu->id_afr0 =3D 0x00000000; - cpu->id_mmfr0 =3D 0x10201105; - cpu->id_mmfr1 =3D 0x40000000; - cpu->id_mmfr2 =3D 0x01260000; - cpu->id_mmfr3 =3D 0x02102211; + cpu->isar.id_mmfr0 =3D 0x10201105; + cpu->isar.id_mmfr1 =3D 0x40000000; + cpu->isar.id_mmfr2 =3D 0x01260000; + cpu->isar.id_mmfr3 =3D 0x02102211; cpu->isar.id_isar0 =3D 0x02101110; cpu->isar.id_isar1 =3D 0x13112111; cpu->isar.id_isar2 =3D 0x21232042; @@ -699,9 +699,9 @@ static void aarch64_max_initfn(Object *obj) u =3D FIELD_DP32(u, ID_ISAR6, SPECRES, 1); cpu->isar.id_isar6 =3D u; =20 - u =3D cpu->id_mmfr3; + u =3D cpu->isar.id_mmfr3; u =3D FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */ - cpu->id_mmfr3 =3D u; + cpu->isar.id_mmfr3 =3D u; =20 u =3D cpu->isar.id_aa64dfr0; u =3D FIELD_DP64(u, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 468e4e89848..492741a2b0b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6910,22 +6910,22 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 4, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->id_mmfr0 }, + .resetvalue =3D cpu->isar.id_mmfr0 }, { .name =3D "ID_MMFR1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 5, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->id_mmfr1 }, + .resetvalue =3D cpu->isar.id_mmfr1 }, { .name =3D "ID_MMFR2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 6, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->id_mmfr2 }, + .resetvalue =3D cpu->isar.id_mmfr2 }, { .name =3D "ID_MMFR3", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 7, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->id_mmfr3 }, + .resetvalue =3D cpu->isar.id_mmfr3 }, { .name =3D "ID_ISAR0", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 0, .access =3D PL1_R, .type =3D ARM_CP_CONST, @@ -6960,7 +6960,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 6, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->id_mmfr4 }, + .resetvalue =3D cpu->isar.id_mmfr4 }, { .name =3D "ID_ISAR6", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 7, .access =3D PL1_R, .type =3D ARM_CP_CONST, @@ -7409,7 +7409,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); define_arm_cp_regs(cpu, vmsa_cp_reginfo); /* TTCBR2 is introduced with ARMv8.2-A32HPD. */ - if (FIELD_EX32(cpu->id_mmfr4, ID_MMFR4, HPDS) !=3D 0) { + if (FIELD_EX32(cpu->isar.id_mmfr4, ID_MMFR4, HPDS) !=3D 0) { define_one_arm_cp_reg(cpu, &ttbcr2_reginfo); } } diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c index bca02553b25..7981ae3bc4e 100644 --- a/target/arm/kvm32.c +++ b/target/arm/kvm32.c @@ -111,6 +111,23 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures = *ahcf) * Fortunately there is not yet anything in there that affects migrati= on. */ =20 + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0, + ARM_CP15_REG32(0, 0, 1, 4)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr1, + ARM_CP15_REG32(0, 0, 1, 5)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr2, + ARM_CP15_REG32(0, 0, 1, 6)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr3, + ARM_CP15_REG32(0, 0, 1, 7)); + if (read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr4, + ARM_CP15_REG32(0, 0, 2, 6))) { + /* + * Older kernels don't support reading ID_MMFR4 (a new in v8 + * register); assume it's zero. + */ + ahcf->isar.id_mmfr4 =3D 0; + } + /* * There is no way to read DBGDIDR, because currently 32-bit KVM * doesn't implement debug at all. Leave it at zero. diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 527532f2b37..5e29b3bb456 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -565,6 +565,14 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures = *ahcf) */ err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0, ARM64_SYS_REG(3, 0, 0, 1, 2)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0, + ARM64_SYS_REG(3, 0, 0, 1, 4)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr1, + ARM64_SYS_REG(3, 0, 0, 1, 5)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr2, + ARM64_SYS_REG(3, 0, 0, 1, 6)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr3, + ARM64_SYS_REG(3, 0, 0, 1, 7)); err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0, ARM64_SYS_REG(3, 0, 0, 2, 0)); err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1, @@ -577,6 +585,8 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *= ahcf) ARM64_SYS_REG(3, 0, 0, 2, 4)); err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5, ARM64_SYS_REG(3, 0, 0, 2, 5)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr4, + ARM64_SYS_REG(3, 0, 0, 2, 6)); err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6, ARM64_SYS_REG(3, 0, 0, 2, 7)); =20 --=20 2.20.1 From nobody Mon May 6 22:28:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581703536100607.5061933213567; Fri, 14 Feb 2020 10:05:36 -0800 (PST) Received: from localhost ([::1]:43196 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2fLK-0005Xd-Sz for importer@patchew.org; Fri, 14 Feb 2020 13:05:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56299) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2f7z-0006Bg-Om for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j2f7x-00018n-KP for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:46 -0500 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:36995) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j2f7x-00016E-Dt for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:45 -0500 Received: by mail-wm1-x341.google.com with SMTP id a6so11579423wme.2 for ; Fri, 14 Feb 2020 09:51:45 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id v8sm8001857wrw.2.2020.02.14.09.51.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Feb 2020 09:51:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=I7VGzJKa0emO5iag6GpwHNYHbTYM9xvXNaLqgVHooL4=; b=mKoc/y89McFeR3+YyDh2nlQqYLnNRHzAyph+9ZMPYXnpyCs23OVW2JrjyDK/6bqERB FD9eXNOnHA9s7hz0LWQKGo+eWKMgJqT3f5gzjWNwJtcBF612R69bfky9l9M+IMgUDzbS cKBJR1woYwsVVNLsDL6gxs8usCzeo2ajQzjGuU0OuBV2a1sqjO8YJhsFJVojkA1/vUKd LMwNvTUNz2MJbdrffZQVBVHwV9kvMSn0eJM4y9oLCMkSpT9TOkXSrJ8FQ4FHkFxZzB9J u/eiVSmK8pOLwGaIjffPIQ/F0t8HPfwK94n50GJDJ2HNcLysTEnsJIiyp/mZXOGpwYB9 aoPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=I7VGzJKa0emO5iag6GpwHNYHbTYM9xvXNaLqgVHooL4=; b=Wejjd00TiOpW94H/EVZMSpcV8OnsZdGoQiNRDc4XOlE7ofq6Nn3weLGDHyuO6FPCjQ BXHbzxj8MycIxLDU5TKFHRDwIJDHblSdUsO9whroXh3m29y1/j+VtJaUBH1yAqKTjAl+ B17NTWfUvOycS+OGOlsX/QZWN8RNQTgncsQzCeKsnOS+8dM1h5z9FZbfL0rYso5+e3PL KrQ2cncEGESz+bxf+XZtTX9PU8boTGO0pnaA8jWnka93ozXeXpZVdChu7tWVHYZJ2eAl yu5slaG5Tpki+TUgp3rBMllSk7XB5cnsrfKXBxbJt8rkgGNeLMuibdr8NmFmb3KSmYjL IHwA== X-Gm-Message-State: APjAAAUq+JNT8Y5Pl10PoiKsit28AM6S7Zliis6YOrfH/OTx5Og9t+vw Q/P5iHiP1wGzzmu7+m+AJDSP4w== X-Google-Smtp-Source: APXvYqwRJD9PQmGiAa66bf7koHyx8+0nw8fZzOIRho0EOnbMYHPsVmNwOqtKsVMZTSPkC61jEjFhig== X-Received: by 2002:a05:600c:228f:: with SMTP id 15mr6110868wmf.56.1581702704511; Fri, 14 Feb 2020 09:51:44 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 19/21] target/arm: Use isar_feature function for testing AA32HPD feature Date: Fri, 14 Feb 2020 17:51:14 +0000 Message-Id: <20200214175116.9164-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200214175116.9164-1-peter.maydell@linaro.org> References: <20200214175116.9164-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eric Auger , Aaron Lindsay , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Now we have moved ID_MMFR4 into the ARMISARegisters struct, we can define and use an isar_feature for the presence of the ARMv8.2-AA32HPD feature, rather than open-coding the test. While we're here, correct a comment typo which missed an 'A' from the feature name. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 5 +++++ target/arm/helper.c | 4 ++-- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ba97fc75c1d..276030a5cf3 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3526,6 +3526,11 @@ static inline bool isar_feature_aa32_pmu_8_4(const A= RMISARegisters *id) FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) !=3D 0xf; } =20 +static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_mmfr4, ID_MMFR4, HPDS) !=3D 0; +} + /* * 64-bit feature tests via id registers. */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 492741a2b0b..56b1c08f027 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7408,8 +7408,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) } else { define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); define_arm_cp_regs(cpu, vmsa_cp_reginfo); - /* TTCBR2 is introduced with ARMv8.2-A32HPD. */ - if (FIELD_EX32(cpu->isar.id_mmfr4, ID_MMFR4, HPDS) !=3D 0) { + /* TTCBR2 is introduced with ARMv8.2-AA32HPD. */ + if (cpu_isar_feature(aa32_hpd, cpu)) { define_one_arm_cp_reg(cpu, &ttbcr2_reginfo); } } --=20 2.20.1 From nobody Mon May 6 22:28:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581703508144648.8914918032981; Fri, 14 Feb 2020 10:05:08 -0800 (PST) Received: from localhost ([::1]:43184 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2fKs-0004TB-R6 for importer@patchew.org; Fri, 14 Feb 2020 13:05:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56331) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2f80-0006DG-13 for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j2f7y-00019w-Rv for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:47 -0500 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]:35922) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j2f7y-00019O-M2 for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:46 -0500 Received: by mail-wm1-x330.google.com with SMTP id p17so11556211wma.1 for ; Fri, 14 Feb 2020 09:51:46 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id v8sm8001857wrw.2.2020.02.14.09.51.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Feb 2020 09:51:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gwjHIqzoFrNguGa6rFd3Yw+93bK6HEFcxL1oIdQTlPE=; b=HAapWzTQPSkjNJfzWOqLKcvQqesRABnCUBA1RS/jBGOQF2dliLnIpJHKVM8+3u3x5V CMMGDDCIjC968NsIJmfni3J7xQOQrXnVJEm3HjCfK3CVUjzLT328iI18ETj4NtnQ+chP T18rsdlfu8MeRUZdFcu/hPOeT7Z0KAhWQHMviO8539lX3hsqaplN0Ok0+LoI9bf0U1Su 0wmJ4g7f4mSan5mDsfGojca8gmfvJCMQgwnIl+JRjoGYlCLz8zPAdkwXUYB/Oc7Rvaxg mfFhDB+SmC6B0ZcgbcQ+sj3Nq6uu9q+g3sOXFYPmTGham2kk8fNjBPzupkZfudde63xG REuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gwjHIqzoFrNguGa6rFd3Yw+93bK6HEFcxL1oIdQTlPE=; b=TtDCp466nNBoO3p+36OSu7+7u0qvCJ2lr/hwjS+obHTb10GnnwPDGAMIs/+Yy2KyK+ Uwe9r6AqNkARuUI9WWVGx7B5YkOJwcpNH8YlcJCwas0nV5iAMpdC+4IS6+xBgXN+Ll9p /kAgVaul/GmUf0g+a4jWrg5jyiIUSdeg/wcbjLo6ndwJOpWN+BX5ZEc3+ey7YFjpwvWf OmQ9mxP3OHQ9UxAm9+RSVOFDMDbVwUwIB2355f03Zs4yfpqKtg9U7YgLDiIQDSkU8EnI GUgXh2zCECDnvZk4t8CF85q5loLRF/gMssNl/xyiwYThxzje69MCXjnn5epuddu4tGgf TFYg== X-Gm-Message-State: APjAAAVEAfxNxNpusAbktQyYr554wyMiW74Blbo6DtMQsDpLG55wh1/+ CcA0saI2dCXLDuCSFHaqufAyFg== X-Google-Smtp-Source: APXvYqwoNLJuEV2dO3gJMpTOVCGjIeb9fezspxNrQ0OGZOY+Pa4xwfU1gUNdpYDIP/UWU4Ah4Ug2bA== X-Received: by 2002:a05:600c:2255:: with SMTP id a21mr5882419wmm.79.1581702705723; Fri, 14 Feb 2020 09:51:45 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 20/21] target/arm: Use FIELD_EX32 for testing 32-bit fields Date: Fri, 14 Feb 2020 17:51:15 +0000 Message-Id: <20200214175116.9164-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200214175116.9164-1-peter.maydell@linaro.org> References: <20200214175116.9164-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::330 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eric Auger , Aaron Lindsay , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Cut-and-paste errors mean we're using FIELD_EX64() to extract fields from some 32-bit ID register fields. Use FIELD_EX32() instead. (This makes no difference in behaviour, it's just more consistent.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 276030a5cf3..c6af3290caf 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3453,18 +3453,18 @@ static inline bool isar_feature_aa32_fp16_arith(con= st ARMISARegisters *id) static inline bool isar_feature_aa32_fp_d32(const ARMISARegisters *id) { /* Return true if D16-D31 are implemented */ - return FIELD_EX64(id->mvfr0, MVFR0, SIMDREG) >=3D 2; + return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) >=3D 2; } =20 static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id) { - return FIELD_EX64(id->mvfr0, MVFR0, FPSHVEC) > 0; + return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0; } =20 static inline bool isar_feature_aa32_fpdp(const ARMISARegisters *id) { /* Return true if CPU supports double precision floating point */ - return FIELD_EX64(id->mvfr0, MVFR0, FPDP) > 0; + return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0; } =20 /* @@ -3474,32 +3474,32 @@ static inline bool isar_feature_aa32_fpdp(const ARM= ISARegisters *id) */ static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id) { - return FIELD_EX64(id->mvfr1, MVFR1, FPHP) > 0; + return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 0; } =20 static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id) { - return FIELD_EX64(id->mvfr1, MVFR1, FPHP) > 1; + return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1; } =20 static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id) { - return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >=3D 1; + return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >=3D 1; } =20 static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id) { - return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >=3D 2; + return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >=3D 2; } =20 static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id) { - return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >=3D 3; + return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >=3D 3; } =20 static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id) { - return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >=3D 4; + return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >=3D 4; } =20 static inline bool isar_feature_aa32_pan(const ARMISARegisters *id) --=20 2.20.1 From nobody Mon May 6 22:28:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581703630544500.56947664326754; Fri, 14 Feb 2020 10:07:10 -0800 (PST) Received: from localhost ([::1]:43250 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2fMr-0007tM-CY for importer@patchew.org; Fri, 14 Feb 2020 13:07:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56368) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2f81-0006Ht-GC for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j2f80-0001BT-3r for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:49 -0500 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:55848) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j2f7z-0001AT-T5 for qemu-devel@nongnu.org; Fri, 14 Feb 2020 12:51:48 -0500 Received: by mail-wm1-x343.google.com with SMTP id q9so10829876wmj.5 for ; Fri, 14 Feb 2020 09:51:47 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id v8sm8001857wrw.2.2020.02.14.09.51.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Feb 2020 09:51:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6KTNckWA4+ATf5z/mBrn8Lcv/aBBE2/oWgefPULbIw0=; b=xmkcU+orzKzljDZz60HJPquXMNvZrrirlkMCapLPwLD/z31OvkB3OCG5UlPyK45BgD opLSNY4PUkx9ypxds4CflLaTfp5opUklKscOEpLR7wX8jL+xyiK28r+xXhx2ktAaOkzB SOWGnBfgiQZq6u5leJMd7X6jYpe3f84IgnhUB52OUggp9TsiarFifmCrldCXQupvBHQn LsjEw4Z9TfKBCz/ynsaRDAT58X9Ap3EsG4HxfVe0B8kUK0Ymm64WhUb8qOHK2cajliN7 JRgLzcmCMKXHbZv90Qw1IyvxMIAsP0MvhGvrc7SBS5PvY7Uk5+lJhocPQ8CEFfuSFe6X oIZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6KTNckWA4+ATf5z/mBrn8Lcv/aBBE2/oWgefPULbIw0=; b=EcWyB5xCFsX1fkiqtJ4Kqg3e+anf2sFiN0idvMXfo1Yfv7gvqKbWv+slaMv8PAdl2W x2HYGRhUHT8vdukZIgUVGt83au8q7b/+h/zrm11yJ5fbANtPMqzSplnUllB9wPjrXof8 io8IzL+yPrSgP2oNWZ14zP0i9aqeGO3Yegj/q4iH9u9xQ8kFlhWqJnZPcKdwE2RG09Hy hfWtdkv5nxFpD1Nq4z1dNoHyZ+mkylhPVdwNo5cSKtHBQ4cEIDU1TiSLiPLyWE99NddF XO0gbFTg+Ia2xKnIbSeXI6RBl5XMimlvLbmONxG7SSqff2myZ63Hog9tXep4t7EFQF7l A8Yw== X-Gm-Message-State: APjAAAUSNAwwgKQAEOCsyLyiBz1QdQGlLboLn5/s3Z46q1lXxkzi+3J+ KApeYrbFQVKR5RZLypZRbZmuXw== X-Google-Smtp-Source: APXvYqx7WH2v6/xtGWAIansO3priUF8nzgK8bgy33UVia/oOToZukQY+9+ns+i5tfyQx1oJxKLZxbw== X-Received: by 2002:a1c:6645:: with SMTP id a66mr6125346wmc.121.1581702706955; Fri, 14 Feb 2020 09:51:46 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 21/21] target/arm: Correctly implement ACTLR2, HACTLR2 Date: Fri, 14 Feb 2020 17:51:16 +0000 Message-Id: <20200214175116.9164-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200214175116.9164-1-peter.maydell@linaro.org> References: <20200214175116.9164-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eric Auger , Aaron Lindsay , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The ACTLR2 and HACTLR2 AArch32 system registers didn't exist in ARMv7 or the original ARMv8. They were later added as optional registers, whose presence is signaled by the ID_MMFR4.AC2 field. From ARMv8.2 they are mandatory (ie ID_MMFR4.AC2 must be non-zero). We implemented HACTLR2 in commit 0e0456ab8895a5e85, but we incorrectly made it exist for all v8 CPUs, and we didn't implement ACTLR2 at all. Sort this out by implementing both registers only when they are supposed to exist, and setting the ID_MMFR4 bit for -cpu max. Note that this removes HACTLR2 from our Cortex-A53, -A47 and -A72 CPU models; this is correct, because those CPUs do not implement this register. Fixes: 0e0456ab8895a5e85 Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 5 +++++ target/arm/cpu.c | 1 + target/arm/cpu64.c | 4 ++++ target/arm/helper.c | 32 +++++++++++++++++++++++--------- 4 files changed, 33 insertions(+), 9 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c6af3290caf..b4c83a1cb52 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3531,6 +3531,11 @@ static inline bool isar_feature_aa32_hpd(const ARMIS= ARegisters *id) return FIELD_EX32(id->id_mmfr4, ID_MMFR4, HPDS) !=3D 0; } =20 +static inline bool isar_feature_aa32_ac2(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_mmfr4, ID_MMFR4, AC2) !=3D 0; +} + /* * 64-bit feature tests via id registers. */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index c46bb5a5c09..9f618e120aa 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2718,6 +2718,7 @@ static void arm_max_initfn(Object *obj) =20 t =3D cpu->isar.id_mmfr4; t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ + t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ cpu->isar.id_mmfr4 =3D t; } #endif diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 8430d432943..32cf8ee98b0 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -703,6 +703,10 @@ static void aarch64_max_initfn(Object *obj) u =3D FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */ cpu->isar.id_mmfr3 =3D u; =20 + u =3D cpu->isar.id_mmfr4; + u =3D FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 implemen= ted */ + cpu->isar.id_mmfr4 =3D u; + u =3D cpu->isar.id_aa64dfr0; u =3D FIELD_DP64(u, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */ cpu->isar.id_aa64dfr0 =3D u; diff --git a/target/arm/helper.c b/target/arm/helper.c index 56b1c08f027..513f4edbb46 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6862,6 +6862,27 @@ static const ARMCPRegInfo ats1cp_reginfo[] =3D { }; #endif =20 +/* + * ACTLR2 and HACTLR2 map to ACTLR_EL1[63:32] and + * ACTLR_EL2[63:32]. They exist only if the ID_MMFR4.AC2 field + * is non-zero, which is never for ARMv7, optionally in ARMv8 + * and mandatorily for ARMv8.2 and up. + * ACTLR2 is banked for S and NS if EL3 is AArch32. Since QEMU's + * implementation is RAZ/WI we can ignore this detail, as we + * do for ACTLR. + */ +static const ARMCPRegInfo actlr2_hactlr2_reginfo[] =3D { + { .name =3D "ACTLR2", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 =3D 3, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "HACTLR2", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 4, .crn =3D 1, .crm =3D 0, .opc2 =3D 3, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + REGINFO_SENTINEL +}; + void register_cp_regs_for_features(ARMCPU *cpu) { /* Register all the coprocessor registers based on feature bits */ @@ -7623,15 +7644,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) REGINFO_SENTINEL }; define_arm_cp_regs(cpu, auxcr_reginfo); - if (arm_feature(env, ARM_FEATURE_V8)) { - /* HACTLR2 maps to ACTLR_EL2[63:32] and is not in ARMv7 */ - ARMCPRegInfo hactlr2_reginfo =3D { - .name =3D "HACTLR2", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 4, .crn =3D 1, .crm =3D 0, .opc2 =3D= 3, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 - }; - define_one_arm_cp_reg(cpu, &hactlr2_reginfo); + if (cpu_isar_feature(aa32_ac2, cpu)) { + define_arm_cp_regs(cpu, actlr2_hactlr2_reginfo); } } =20 --=20 2.20.1