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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id e22sm3362454wme.45.2020.02.13.06.42.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Feb 2020 06:42:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=io7OAgKGiS3YeaCrWPyK/MAdXhm40+eWtarxm3Kge30=; b=V2kB4yHQ+xdxJ1KcY7NNn82D4JlZGJ0Ww1IcYDQDDzMQxwKfuxd61TQGb3oS1qLM6k 18mxDcKYn97AO+UmdLtZX7LgQ6afFPy3S4M1bH8YbzaMckDzo2oePdQLcFotX0F2Diue snCwrBWL9/9PA8dTBygMCJRJQ0alcHzdDf8ueFleZeAL81DplgZFRMDOznyDDKny7lkI q7jo3/Lb+78f/UBGFbNq1JaHjWfkcUeD2GDdx9fgv4yqr+U4aeGGipV5JPACN+F/eItb mrBXtzLvJASltSdasknomfMPL3jc4JaR0Y4KgqqyNyh1CdMNjKR2dsoeoZo9h+PaHyi7 0uZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=io7OAgKGiS3YeaCrWPyK/MAdXhm40+eWtarxm3Kge30=; b=QKGrFw8RbtQ8xieG9P1eKCxYp0sNhBGpU922isoKAg0mYXY1JpvB/8LK7Q69nYej/4 leN01zC9wNsY3l6/IOWasI2UW5QGISXmhxiERQn+1XDvdh5ScRRP2BigFp2SaRI1kWjS Com6XeUahvEt19YuINoDVGLoEuLUrwu7H2WQLI3oPxBUBx7sQIkh6UDoKmld3PD6m1ZV uFFFzIo5lhDs/UFdm1KF9REjaRR+7U36jn3jdOvcH7ZLiFQuOgorN4JVTjOq2evUpDSJ INY1LqEyLqJAI7G+JFwMkT3neQ7WtIjpQd6ccT/sAeWmSkpeWFzMTD6gmBafhOnHGIKj ycqg== X-Gm-Message-State: APjAAAVSLpoHgv6XQorvuTB+kCFaAULSaErsgXIdQXxALbLFEoskAKQ4 7TJTtAD3mTi02Obj/8O7nnzohV2GWNs= X-Google-Smtp-Source: APXvYqw1S4yUbSOJIutHtRO5210ep052YhbzC3CRlq90xCPq4eU3Ho+R7fe/5X43+rnHbXPZQhK4Og== X-Received: by 2002:adf:c453:: with SMTP id a19mr22318723wrg.341.1581604935917; Thu, 13 Feb 2020 06:42:15 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/46] target/arm: Implement ATS1E1 system registers Date: Thu, 13 Feb 2020 14:41:23 +0000 Message-Id: <20200213144145.818-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200213144145.818-1-peter.maydell@linaro.org> References: <20200213144145.818-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson This is a minor enhancement over ARMv8.1-PAN. The *_PAN mmu_idx are used with the existing do_ats_write. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200208125816.14954-16-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 56 ++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 50 insertions(+), 6 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index de16ce79add..d99661d4ea5 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3409,16 +3409,21 @@ static void ats_write(CPUARMState *env, const ARMCP= RegInfo *ri, uint64_t value) =20 switch (ri->opc2 & 6) { case 0: - /* stage 1 current state PL1: ATS1CPR, ATS1CPW */ + /* stage 1 current state PL1: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP= */ switch (el) { case 3: mmu_idx =3D ARMMMUIdx_SE3; break; case 2: - mmu_idx =3D ARMMMUIdx_Stage1_E1; - break; + g_assert(!secure); /* TODO: ARMv8.4-SecEL2 */ + /* fall through */ case 1: - mmu_idx =3D secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_Stage1_E1; + if (ri->crm =3D=3D 9 && (env->uncached_cpsr & CPSR_PAN)) { + mmu_idx =3D (secure ? ARMMMUIdx_SE10_1_PAN + : ARMMMUIdx_Stage1_E1_PAN); + } else { + mmu_idx =3D secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_Stage1_E= 1; + } break; default: g_assert_not_reached(); @@ -3487,8 +3492,13 @@ static void ats_write64(CPUARMState *env, const ARMC= PRegInfo *ri, switch (ri->opc2 & 6) { case 0: switch (ri->opc1) { - case 0: /* AT S1E1R, AT S1E1W */ - mmu_idx =3D secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_Stage1_E1; + case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */ + if (ri->crm =3D=3D 9 && (env->pstate & PSTATE_PAN)) { + mmu_idx =3D (secure ? ARMMMUIdx_SE10_1_PAN + : ARMMMUIdx_Stage1_E1_PAN); + } else { + mmu_idx =3D secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_Stage1_E= 1; + } break; case 4: /* AT S1E2R, AT S1E2W */ mmu_idx =3D ARMMMUIdx_E2; @@ -6683,6 +6693,32 @@ static const ARMCPRegInfo vhe_reginfo[] =3D { REGINFO_SENTINEL }; =20 +#ifndef CONFIG_USER_ONLY +static const ARMCPRegInfo ats1e1_reginfo[] =3D { + { .name =3D "AT_S1E1R", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 9, .opc2 =3D 0, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn =3D ats_write64 }, + { .name =3D "AT_S1E1W", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 9, .opc2 =3D 1, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn =3D ats_write64 }, + REGINFO_SENTINEL +}; + +static const ARMCPRegInfo ats1cp_reginfo[] =3D { + { .name =3D "ATS1CPRP", + .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 9, .opc2 =3D 0, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn =3D ats_write }, + { .name =3D "ATS1CPWP", + .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 9, .opc2 =3D 1, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn =3D ats_write }, + REGINFO_SENTINEL +}; +#endif + void register_cp_regs_for_features(ARMCPU *cpu) { /* Register all the coprocessor registers based on feature bits */ @@ -7620,6 +7656,14 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_pan, cpu)) { define_one_arm_cp_reg(cpu, &pan_reginfo); } +#ifndef CONFIG_USER_ONLY + if (cpu_isar_feature(aa64_ats1e1, cpu)) { + define_arm_cp_regs(cpu, ats1e1_reginfo); + } + if (cpu_isar_feature(aa32_ats1e1, cpu)) { + define_arm_cp_regs(cpu, ats1cp_reginfo); + } +#endif =20 if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu= )) { define_arm_cp_regs(cpu, vhe_reginfo); --=20 2.20.1