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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id e22sm3362454wme.45.2020.02.13.06.42.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Feb 2020 06:42:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=+ZCL+35F1Ez3bM5+edPRdLJ0LuMquABU+ROVw/U0SwM=; b=PstuYtpgEPP12b6vN8PiJ6mYqNJM419/x9HUH3AuAXnhfsDySteIO9PrRZFO3dAzOd bHOr4S4djzBikcecXMazQL5LjZn1hLEg2rn6NrFuCXEovvHLaBAXDefx6bLzv364yifj GGEjKXbCnqjMkMa8eSNeulhh9oveMuPUaEu4C1Dcv9yRpxu0YaOLI0FPVbU0iRecUbj1 5vLn1tA4Ef3DfaWlDeDqJV5ZdxYxhNT/bPydWOi/2Uq0t069FQ5JJJXikRM9dnoUaD7l NhES/FpM4s6pCLscJxufNHKT5pRSinuZzayPcK4AEXdl0plViDYUkdIZzapj+Wmg4io3 wI1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+ZCL+35F1Ez3bM5+edPRdLJ0LuMquABU+ROVw/U0SwM=; b=CM89X0lmGR9rI+VtwIDshu3fapXd1s51KEbqXAJVBlE/RqiMRberu4KFhy5ximkeng luFmxByRcpTCKcnbJbg/cGWKlXxf80wbcs8EY38h9TkcdFSJ31F+IFQygOVX3MC9DZPK zGU8Q3jcmBGoroEO9UePreJ0JsW/jMv0LFAcHOFKbhSXETmwMm9qlc97THytmrh1dAiu OPxJSa3OAsfU27wjwO4mPx6K1I0NZoHBcngbvcVoidjjTIumb32dVOCDWEH+n1aicJT6 DE93wkWUQwmWxV4Icl119YtE7QDHyQN39/S46+pgBWDu3akq4oufgWyxWxPSuWrSGSvI 8+2w== X-Gm-Message-State: APjAAAVDps1SKdxJ92orl1SgtzLv2minRRtj9R/aIFqBVdo9XAxDPMm+ aH3OYUxW+PJJAj46dWXLqNjGMR+8/SQ= X-Google-Smtp-Source: APXvYqx8MFq3e5zSpxMldtUrG5JWaJJfxXrTE8vn9hQ4Q00e2vufO+plELhOnA43vQm2EEG3wCwUNQ== X-Received: by 2002:a5d:4d4a:: with SMTP id a10mr23349659wru.220.1581604931778; Thu, 13 Feb 2020 06:42:11 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/46] target/arm: Update MSR access for PAN Date: Thu, 13 Feb 2020 14:41:19 +0000 Message-Id: <20200213144145.818-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200213144145.818-1-peter.maydell@linaro.org> References: <20200213144145.818-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson For aarch64, there's a dedicated msr (imm, reg) insn. For aarch32, this is done via msr to cpsr. Writes from el0 are ignored, which is already handled by the CPSR_USER mask. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200208125816.14954-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 2 ++ target/arm/internals.h | 6 ++++++ target/arm/helper.c | 21 +++++++++++++++++++++ target/arm/translate-a64.c | 14 ++++++++++++++ 4 files changed, 43 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c6dff1d55b6..65a0ef8cd6b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1186,6 +1186,7 @@ void pmu_init(ARMCPU *cpu); #define CPSR_IT_2_7 (0xfc00U) #define CPSR_GE (0xfU << 16) #define CPSR_IL (1U << 20) +#define CPSR_PAN (1U << 22) #define CPSR_J (1U << 24) #define CPSR_IT_0_1 (3U << 25) #define CPSR_Q (1U << 27) @@ -1250,6 +1251,7 @@ void pmu_init(ARMCPU *cpu); #define PSTATE_BTYPE (3U << 10) #define PSTATE_IL (1U << 20) #define PSTATE_SS (1U << 21) +#define PSTATE_PAN (1U << 22) #define PSTATE_V (1U << 28) #define PSTATE_C (1U << 29) #define PSTATE_Z (1U << 30) diff --git a/target/arm/internals.h b/target/arm/internals.h index 034d98ad538..f6709a2b08d 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1081,6 +1081,9 @@ static inline uint32_t aarch32_cpsr_valid_mask(uint64= _t features, if (isar_feature_jazelle(id)) { valid |=3D CPSR_J; } + if (isar_feature_aa32_pan(id)) { + valid |=3D CPSR_PAN; + } =20 return valid; } @@ -1093,6 +1096,9 @@ static inline uint32_t aarch64_pstate_valid_mask(cons= t ARMISARegisters *id) if (isar_feature_aa64_bti(id)) { valid |=3D PSTATE_BTYPE; } + if (isar_feature_aa64_pan(id)) { + valid |=3D PSTATE_PAN; + } =20 return valid; } diff --git a/target/arm/helper.c b/target/arm/helper.c index e4f17c7e839..058fb239592 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4163,6 +4163,24 @@ static void aa64_daif_write(CPUARMState *env, const = ARMCPRegInfo *ri, env->daif =3D value & PSTATE_DAIF; } =20 +static uint64_t aa64_pan_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->pstate & PSTATE_PAN; +} + +static void aa64_pan_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + env->pstate =3D (env->pstate & ~PSTATE_PAN) | (value & PSTATE_PAN); +} + +static const ARMCPRegInfo pan_reginfo =3D { + .name =3D "PAN", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 4, .crm =3D 2, .opc2 =3D 3, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_RW, + .readfn =3D aa64_pan_read, .writefn =3D aa64_pan_write +}; + static CPAccessResult aa64_cacheop_access(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) @@ -7599,6 +7617,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_lor, cpu)) { define_arm_cp_regs(cpu, lor_reginfo); } + if (cpu_isar_feature(aa64_pan, cpu)) { + define_one_arm_cp_reg(cpu, &pan_reginfo); + } =20 if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu= )) { define_arm_cp_regs(cpu, vhe_reginfo); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 49631c23404..d8ba240a155 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1602,6 +1602,20 @@ static void handle_msr_i(DisasContext *s, uint32_t i= nsn, s->base.is_jmp =3D DISAS_NEXT; break; =20 + case 0x04: /* PAN */ + if (!dc_isar_feature(aa64_pan, s) || s->current_el =3D=3D 0) { + goto do_unallocated; + } + if (crm & 1) { + set_pstate_bits(PSTATE_PAN); + } else { + clear_pstate_bits(PSTATE_PAN); + } + t1 =3D tcg_const_i32(s->current_el); + gen_helper_rebuild_hflags_a64(cpu_env, t1); + tcg_temp_free_i32(t1); + break; + case 0x05: /* SPSel */ if (s->current_el =3D=3D 0) { goto do_unallocated; --=20 2.20.1