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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id e22sm3362454wme.45.2020.02.13.06.42.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Feb 2020 06:42:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=UM5sTdj2EYOtgEuwYW49VvaCFPwcbtuVqRLWhdo1ojU=; b=uxH3ziJk0qIPc1YVZiQQH+XoWOHB5dpNXtOuw2FKgNoVQv5xi0MmKvYZmZhB1VUt5A lHqQ6Nr0McGN5Z/dAOrkxHfk0aulpd6UBN8Dd7ZTcgTzkmYB9YSITIUgcE7Rp+UvEj4h DX2TcpIAKfG7HqDRIziSSu0l1guaZsoZtNCffPQV7+6NVPlFEeNI7iBACv3wD8c/hgBS UElWmnU3pzy/RpYBJ4Xcc4ltC5bBaDTJk4WnBU1BwHGGt26hc/U9e421QQvRIMJDsyet s2EaNr5A5uW3piTymqzeaQjfijtGzuxFjkss+DFGEz5rfV7gQItl6Qhu2r+7N/SMexaD qYJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UM5sTdj2EYOtgEuwYW49VvaCFPwcbtuVqRLWhdo1ojU=; b=ICPdakCVMMU2oguG77aPLnBTZw+JTdmEpYFR44yhz0pBIex7S8PjqyDi4hGrAOAhl+ e4MsEZyV0OcULXyHLRDASyTLhdWL3Y23hgLy+UIYRJ03qxHxtgFyMyhRfI7rkxVPWK2A o6zTB6+zesRj721JV5paXzGWOucKmstIKXSrDios1rx/ca3fTRIVj2cRaKhNLTfD5gRf S0UHBG1KiT45Sd/eymwc4oBqOxCK8GCsSmX/HPEhc4LLG3KvhCy2OIvajutFOVnNg0od xhJLk4qpIR1bkGASsxuZF7AlwFtI14Gz9dMWc6XoFIYjkNWMnoV/JoP+cjjvgz0Ip/8k 4u3g== X-Gm-Message-State: APjAAAX9sgBs8K/SS76a/KyKUTp5/0w5anf7NjM4tMFKyU9/6n9r3jJ3 ImyG7Z9Lzzn4ChMNd+aDFi9HC3pWsZ0= X-Google-Smtp-Source: APXvYqziaRDFKqcP9fPh/ja2IXC4Q/rOn/gUaeO2ip1QZbl/l0zqs8RHl33ZH3OwcZ7Og0NxYUjwXQ== X-Received: by 2002:adf:c453:: with SMTP id a19mr22318154wrg.341.1581604927704; Thu, 13 Feb 2020 06:42:07 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/46] target/arm: Replace CPSR_ERET_MASK with aarch32_cpsr_valid_mask Date: Thu, 13 Feb 2020 14:41:15 +0000 Message-Id: <20200213144145.818-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200213144145.818-1-peter.maydell@linaro.org> References: <20200213144145.818-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42a X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson CPSR_ERET_MASK was a useless renaming of CPSR_RESERVED. The function also takes into account bits that the cpu does not support. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200208125816.14954-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 2 -- target/arm/op_helper.c | 5 ++++- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 08b2f5d73e4..694b0742983 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1209,8 +1209,6 @@ void pmu_init(ARMCPU *cpu); #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE) /* Execution state bits. MRS read as zero, MSR writes ignored. */ #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) -/* Mask of bits which may be set by exception return copying them from SPS= R */ -#define CPSR_ERET_MASK (~CPSR_RESERVED) =20 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ #define XPSR_EXCP 0x1ffU diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 27d16ad9ad9..acf1815ea3e 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -400,11 +400,14 @@ void HELPER(cpsr_write)(CPUARMState *env, uint32_t va= l, uint32_t mask) /* Write the CPSR for a 32-bit exception return */ void HELPER(cpsr_write_eret)(CPUARMState *env, uint32_t val) { + uint32_t mask; + qemu_mutex_lock_iothread(); arm_call_pre_el_change_hook(env_archcpu(env)); qemu_mutex_unlock_iothread(); =20 - cpsr_write(env, val, CPSR_ERET_MASK, CPSRWriteExceptionReturn); + mask =3D aarch32_cpsr_valid_mask(env->features, &env_archcpu(env)->isa= r); + cpsr_write(env, val, mask, CPSRWriteExceptionReturn); =20 /* Generated code has already stored the new PC value, but * without masking out its low bits, because which bits need --=20 2.20.1