From nobody Tue Feb 10 13:17:16 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581601614897196.48814618408596; Thu, 13 Feb 2020 05:46:54 -0800 (PST) Received: from localhost ([::1]:52586 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2EpR-0008VW-I0 for importer@patchew.org; Thu, 13 Feb 2020 08:46:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58109) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j29GN-00029h-EE for qemu-devel@nongnu.org; Thu, 13 Feb 2020 02:50:20 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j29GM-0000wD-Dz for qemu-devel@nongnu.org; Thu, 13 Feb 2020 02:50:19 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:44310 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j29GM-0000pf-1Y for qemu-devel@nongnu.org; Thu, 13 Feb 2020 02:50:18 -0500 Received: from DGGEMS407-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id B2CD2914015217E4814B; Thu, 13 Feb 2020 15:50:06 +0800 (CST) Received: from DESKTOP-D7EVK5B.china.huawei.com (10.173.221.29) by DGGEMS407-HUB.china.huawei.com (10.3.19.207) with Microsoft SMTP Server id 14.3.439.0; Thu, 13 Feb 2020 15:50:00 +0800 From: Yubo Miao To: , Subject: [RFC 2/2] pci-expender-bus:Add pcie-root-port to pxb-pcie under arm. Date: Thu, 13 Feb 2020 15:49:52 +0800 Message-ID: <20200213074952.544-3-miaoyubo@huawei.com> X-Mailer: git-send-email 2.24.1.windows.2 In-Reply-To: <20200213074952.544-1-miaoyubo@huawei.com> References: <20200213074952.544-1-miaoyubo@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.173.221.29] X-CFilter-Loop: Reflected Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.35 X-Mailman-Approved-At: Thu, 13 Feb 2020 08:44:55 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: imammedo@redhat.com, miaoyubo@huawei.com, qemu-devel@nongnu.org, xiexiangyou@huawei.com, mst@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: miaoyubo Since devices could not directly plugged into pxb-pcie, under arm, one pcie-root port is plugged into pxb-pcie. Due to the bus for each pxb-pcie is defined as 2 in acpi dsdt tables(one for pxb-pcie, one for pcie-root-por= t), only one device could be plugged into one pxb-pcie. Signed-off-by: miaoyubo --- hw/pci-bridge/pci_expander_bridge.c | 9 +++++++++ include/hw/pci/pcie_port.h | 1 + 2 files changed, 10 insertions(+) diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expand= er_bridge.c index 47aaaf8fd1..3d896dd452 100644 --- a/hw/pci-bridge/pci_expander_bridge.c +++ b/hw/pci-bridge/pci_expander_bridge.c @@ -15,6 +15,7 @@ #include "hw/pci/pci.h" #include "hw/pci/pci_bus.h" #include "hw/pci/pci_host.h" +#include "hw/pci/pcie_port.h" #include "hw/qdev-properties.h" #include "hw/pci/pci_bridge.h" #include "qemu/range.h" @@ -233,7 +234,15 @@ static void pxb_dev_realize_common(PCIDevice *dev, boo= l pcie, Error **errp) =20 ds =3D qdev_create(NULL, TYPE_PXB_HOST); if (pcie) { +#ifdef __aarch64__ + bus =3D pci_root_bus_new(ds, "pxb-pcie-internal", + NULL, NULL, 0, TYPE_PXB_PCIE_BUS); + bds =3D qdev_create(BUS(bus), "pcie-root-port"); + bds->id =3D dev_name; + qdev_prop_set_uint8(bds, PCIE_ROOT_PORT_PROP_CHASSIS, pxb->bus_nr); +#else bus =3D pci_root_bus_new(ds, dev_name, NULL, NULL, 0, TYPE_PXB_PCI= E_BUS); +#endif } else { bus =3D pci_root_bus_new(ds, "pxb-internal", NULL, NULL, 0, TYPE_P= XB_BUS); bds =3D qdev_create(BUS(bus), "pci-bridge"); diff --git a/include/hw/pci/pcie_port.h b/include/hw/pci/pcie_port.h index 4b3d254b08..b41d473220 100644 --- a/include/hw/pci/pcie_port.h +++ b/include/hw/pci/pcie_port.h @@ -64,6 +64,7 @@ int pcie_chassis_add_slot(struct PCIESlot *slot); void pcie_chassis_del_slot(PCIESlot *s); =20 #define TYPE_PCIE_ROOT_PORT "pcie-root-port-base" +#define PCIE_ROOT_PORT_PROP_CHASSIS "chassis" #define PCIE_ROOT_PORT_CLASS(klass) \ OBJECT_CLASS_CHECK(PCIERootPortClass, (klass), TYPE_PCIE_ROOT_PORT) #define PCIE_ROOT_PORT_GET_CLASS(obj) \ --=20 2.19.1