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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id l15sm536067pgi.31.2020.02.12.19.22.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Feb 2020 19:22:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hRsQ7XlJN4rMifYbK1S2B4u9AT4d8Fx9ZqVq28vUwr8=; b=l0j9dxdzytU2BofWbBFLt+92/1oDuW3FSzq/JoTfrGb93GIpGcaR/InhGpzg8KKbmy jsBvuMcn6le2JfX4L1Z0pqMtzkvuhyv5Quzh0/m35/8bpF5YbTUhqfEoIPiUGuaSHGGN 6hhHSU51ctjE4HqvZp6zBpJYnr+wc8HeJK8mKPaptz/ctnnCXPGvRNNHP5Ce5oI4JYQC dKFdaNPfJP2sMuXd3o8uZQH3iJlYFYVESclVCnTeGwor8/zqT+1FLnTzFezv6+3HE1vZ 3r4ITl93TNuTxck+jRbrrnytqGB5uIZIfb3mu25DjbekgM8oR2ZYcsyXWtwZmi/DGa0G 36DA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hRsQ7XlJN4rMifYbK1S2B4u9AT4d8Fx9ZqVq28vUwr8=; b=bcMOX00oHEr/HuAAiPxpOmitOU6s5Vp86IB7cLigjzK388jZhiMVU3oiXSaDwZiNgU nvsRxGpqsU8CyWwDLyTQo5sxNRrPihMRut5VRiWySZOoJqQ5VV9Y1R5u7CDUy0U+tUwI Z0iO97DCygIysTAj3WU1scdipCwrIYslj4ednYfQ8rATYMOKBeBpfzVt4ReLZZ1wgSk7 mA/NviKdjeUZtHAhVD7z2mOW6oQSuiEnZSYoSnrudWHEwxteKU1FTLXEiTUAg0A6eikr LJOzB8H0dmON6O87BJTmFEH82j3ih9e6PN+1bW4X12UaoZ7d+qWtaPv0SiegTG0e8+A6 TizA== X-Gm-Message-State: APjAAAVVYNdFF3Tme0xAvN+CCXQjSRqNjFBJOGEdLUZCLKxLGwpSigct x6MWSG5H4qghRumHLeAThz3LwbXw93E= X-Google-Smtp-Source: APXvYqwvdaS/KDpDdl1vmq4Rni302aXJ1WGoT4oKpV2DlvdlJlbmvT+hn3usDSptN8b7qPYZn8Gwqw== X-Received: by 2002:a17:90a:7187:: with SMTP id i7mr2553289pjk.6.1581564149193; Wed, 12 Feb 2020 19:22:29 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 3/5] linux-user/i386: Emulate x86_64 vsyscalls Date: Wed, 12 Feb 2020 19:22:21 -0800 Message-Id: <20200213032223.14643-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200213032223.14643-1-richard.henderson@linaro.org> References: <20200213032223.14643-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1041 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , laurent@vivier.eu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Notice the magic page during translate, much like we already do for the arm32 commpage. At runtime, raise an exception to return cpu_loop for emulation. Reviewed-by: Paolo Bonzini Signed-off-by: Richard Henderson --- v3: Adjust the gotos. Define TARGET_VSYSCALL_PAGE. --- target/i386/cpu.h | 7 +++ linux-user/i386/cpu_loop.c | 108 +++++++++++++++++++++++++++++++++++++ target/i386/translate.c | 14 ++++- 3 files changed, 128 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 08b4422f36..39be555db3 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1001,6 +1001,7 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS]; =20 #define EXCP_VMEXIT 0x100 /* only for system emulation */ #define EXCP_SYSCALL 0x101 /* only for user emulation */ +#define EXCP_VSYSCALL 0x102 /* only for user emulation */ =20 /* i386-specific interrupt pending bits. */ #define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1 @@ -2215,4 +2216,10 @@ static inline bool hyperv_feat_enabled(X86CPU *cpu, = int feat) return !!(cpu->hyperv_features & BIT(feat)); } =20 +#if defined(TARGET_X86_64) && \ + defined(CONFIG_USER_ONLY) && \ + defined(CONFIG_LINUX) +# define TARGET_VSYSCALL_PAGE (UINT64_C(-10) << 20) +#endif + #endif /* I386_CPU_H */ diff --git a/linux-user/i386/cpu_loop.c b/linux-user/i386/cpu_loop.c index e217cca5ee..70cde417e6 100644 --- a/linux-user/i386/cpu_loop.c +++ b/linux-user/i386/cpu_loop.c @@ -92,6 +92,109 @@ static void gen_signal(CPUX86State *env, int sig, int c= ode, abi_ptr addr) queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); } =20 +#ifdef TARGET_X86_64 +static bool write_ok_or_segv(CPUX86State *env, abi_ptr addr, size_t len) +{ + /* + * For all the vsyscalls, NULL means "don't write anything" not + * "write it at address 0". + */ + if (addr =3D=3D 0 || access_ok(VERIFY_WRITE, addr, len)) { + return true; + } + + env->error_code =3D PG_ERROR_W_MASK | PG_ERROR_U_MASK; + gen_signal(env, TARGET_SIGSEGV, TARGET_SEGV_MAPERR, addr); + return false; +} + +/* + * Since v3.1, the kernel traps and emulates the vsyscall page. + * Entry points other than the official generate SIGSEGV. + */ +static void emulate_vsyscall(CPUX86State *env) +{ + int syscall; + abi_ulong ret; + uint64_t caller; + + /* + * Validate the entry point. We have already validated the page + * during translation to get here; now verify the offset. + */ + switch (env->eip & ~TARGET_PAGE_MASK) { + case 0x000: + syscall =3D TARGET_NR_gettimeofday; + break; + case 0x400: + syscall =3D TARGET_NR_time; + break; + case 0x800: + syscall =3D TARGET_NR_getcpu; + break; + default: + goto sigsegv; + } + + /* + * Validate the return address. + * Note that the kernel treats this the same as an invalid entry point. + */ + if (get_user_u64(caller, env->regs[R_ESP])) { + goto sigsegv; + } + + /* + * Validate the the pointer arguments. + */ + switch (syscall) { + case TARGET_NR_gettimeofday: + if (!write_ok_or_segv(env, env->regs[R_EDI], + sizeof(struct target_timeval)) || + !write_ok_or_segv(env, env->regs[R_ESI], + sizeof(struct target_timezone))) { + return; + } + break; + case TARGET_NR_time: + if (!write_ok_or_segv(env, env->regs[R_EDI], sizeof(abi_long))) { + return; + } + break; + case TARGET_NR_getcpu: + if (!write_ok_or_segv(env, env->regs[R_EDI], sizeof(uint32_t)) || + !write_ok_or_segv(env, env->regs[R_ESI], sizeof(uint32_t))) { + return; + } + break; + default: + g_assert_not_reached(); + } + + /* + * Perform the syscall. None of the vsyscalls should need restarting. + */ + ret =3D do_syscall(env, syscall, env->regs[R_EDI], env->regs[R_ESI], + env->regs[R_EDX], env->regs[10], env->regs[8], + env->regs[9], 0, 0); + g_assert(ret !=3D -TARGET_ERESTARTSYS); + g_assert(ret !=3D -TARGET_QEMU_ESIGRETURN); + if (ret =3D=3D -TARGET_EFAULT) { + goto sigsegv; + } + env->regs[R_EAX] =3D ret; + + /* Emulate a ret instruction to leave the vsyscall page. */ + env->eip =3D caller; + env->regs[R_ESP] +=3D 8; + return; + + sigsegv: + /* Like force_sig(SIGSEGV). */ + gen_signal(env, TARGET_SIGSEGV, TARGET_SI_KERNEL, 0); +} +#endif + void cpu_loop(CPUX86State *env) { CPUState *cs =3D env_cpu(env); @@ -141,6 +244,11 @@ void cpu_loop(CPUX86State *env) env->regs[R_EAX] =3D ret; } break; +#endif +#ifdef TARGET_X86_64 + case EXCP_VSYSCALL: + emulate_vsyscall(env); + break; #endif case EXCP0B_NOSEG: case EXCP0C_STACK: diff --git a/target/i386/translate.c b/target/i386/translate.c index d9af8f4078..5e5dbb41b0 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -8555,7 +8555,19 @@ static bool i386_tr_breakpoint_check(DisasContextBas= e *dcbase, CPUState *cpu, static void i386_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); - target_ulong pc_next =3D disas_insn(dc, cpu); + target_ulong pc_next; + +#ifdef TARGET_VSYSCALL_PAGE + /* + * Detect entry into the vsyscall page and invoke the syscall. + */ + if ((dc->base.pc_next & TARGET_PAGE_MASK) =3D=3D TARGET_VSYSCALL_PAGE)= { + gen_exception(dc, EXCP_VSYSCALL, dc->base.pc_next); + return; + } +#endif + + pc_next =3D disas_insn(dc, cpu); =20 if (dc->tf || (dc->base.tb->flags & HF_INHIBIT_IRQ_MASK)) { /* if single step mode, we generate only one instruction and --=20 2.20.1