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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id b18sm5306281pfd.63.2020.02.11.11.42.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Feb 2020 11:42:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mkTZ+wCNqBwcUD+aN0bjpxQ/XJFdk1zV/Sm4bYszhRs=; b=JcqKBNjvIE9Tt3WfUpQnlCU8e2n9cGD4SP3/p14cQeobNXYwtc3BNl+78P2VFl88p3 phFS2NrN1n4030GR8sUP6+/LL8y/8M5SsFoXToWMJucNcuHO6O8wK9nYf4S0Vao6zBK3 6k43WhZPTAq05h/bFhZEeqJ0/oSt+GecM1h9uziFGEN6+/825B+0bqQekywYHtULOqoB JyiQBLdfS2WklsPaI0h8e8VZ9Oz0UBxtK+MY6UBSBlpWu/IMqk+c5/hIx4dYLoMJlhxN wfIzNroUChpQZeAeesenihWDlmac4UgAvveZlo75JbTSmNh9XUb3vMO2UsL7umTlhUgF xDkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mkTZ+wCNqBwcUD+aN0bjpxQ/XJFdk1zV/Sm4bYszhRs=; b=a1HzoiMcCdP5SJozOz8LG4e1VzFtamXw25hdpO0t5zJSc6l5C3jMMHnBiWfafN4zC5 DQxs9tczPjFr7c173GrZS+da3tz6aXgt80tLYh3DcsPxIjcjuAUopX6OosrOTpTBf8YE qwKAJlDUpH70nymvVj+swKig4is+RzWyjIx85x7mIMCVZ273VdUu6FJlYb3a9p2dbfUg W3YZFAVepk3LzUNovWw6dsyDl1V3ZJsJh3YQKBq12nVPCO+kB2YpHlfihlq4BITPNpam /tE2NwZruLfFQxYIii1Dz6q2aDj5d0lySuwAcTCZGCH40f8tlvSEE+eCt9cgU8y4BTRI NI4w== X-Gm-Message-State: APjAAAWfxzwZT6CWekYWaxyjBQS5I2X1GcvizJJUhfSLt+PRiob2/7tm VfPRszaPbiSOrrhXAZWFmzStarZYhBk= X-Google-Smtp-Source: APXvYqy2BNG5e+WTAes6FRx4JuB9xXFLVxGjSsCj6BmTkYFR+9HBQ5uXm6aLDj64T12hvGhAG6POpw== X-Received: by 2002:a17:902:968c:: with SMTP id n12mr4736917plp.144.1581450150854; Tue, 11 Feb 2020 11:42:30 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 1/2] target/arm: Fix select for aa64_va_parameters_both Date: Tue, 11 Feb 2020 11:42:27 -0800 Message-Id: <20200211194228.16907-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200211194228.16907-1-richard.henderson@linaro.org> References: <20200211194228.16907-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1043 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Select should always be 0 for a regime with one range. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.c | 46 +++++++++++++++++++++++---------------------- 1 file changed, 24 insertions(+), 22 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 7d15d5c933..a008c70c87 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10074,13 +10074,8 @@ ARMVAParameters aa64_va_parameters_both(CPUARMStat= e *env, uint64_t va, bool tbi, tbid, epd, hpd, using16k, using64k; int select, tsz; =20 - /* - * Bit 55 is always between the two regions, and is canonical for - * determining if address tagging is enabled. - */ - select =3D extract64(va, 55, 1); - if (!regime_has_2_ranges(mmu_idx)) { + select =3D 0; tsz =3D extract32(tcr, 0, 6); using64k =3D extract32(tcr, 14, 1); using16k =3D extract32(tcr, 15, 1); @@ -10093,23 +10088,30 @@ ARMVAParameters aa64_va_parameters_both(CPUARMSta= te *env, uint64_t va, tbid =3D extract32(tcr, 29, 1); } epd =3D false; - } else if (!select) { - tsz =3D extract32(tcr, 0, 6); - epd =3D extract32(tcr, 7, 1); - using64k =3D extract32(tcr, 14, 1); - using16k =3D extract32(tcr, 15, 1); - tbi =3D extract64(tcr, 37, 1); - hpd =3D extract64(tcr, 41, 1); - tbid =3D extract64(tcr, 51, 1); } else { - int tg =3D extract32(tcr, 30, 2); - using16k =3D tg =3D=3D 1; - using64k =3D tg =3D=3D 3; - tsz =3D extract32(tcr, 16, 6); - epd =3D extract32(tcr, 23, 1); - tbi =3D extract64(tcr, 38, 1); - hpd =3D extract64(tcr, 42, 1); - tbid =3D extract64(tcr, 52, 1); + /* + * Bit 55 is always between the two regions, and is canonical for + * determining if address tagging is enabled. + */ + select =3D extract64(va, 55, 1); + if (!select) { + tsz =3D extract32(tcr, 0, 6); + epd =3D extract32(tcr, 7, 1); + using64k =3D extract32(tcr, 14, 1); + using16k =3D extract32(tcr, 15, 1); + tbi =3D extract64(tcr, 37, 1); + hpd =3D extract64(tcr, 41, 1); + tbid =3D extract64(tcr, 51, 1); + } else { + int tg =3D extract32(tcr, 30, 2); + using16k =3D tg =3D=3D 1; + using64k =3D tg =3D=3D 3; + tsz =3D extract32(tcr, 16, 6); + epd =3D extract32(tcr, 23, 1); + tbi =3D extract64(tcr, 38, 1); + hpd =3D extract64(tcr, 42, 1); + tbid =3D extract64(tcr, 52, 1); + } } tsz =3D MIN(tsz, 39); /* TODO: ARMv8.4-TTST */ tsz =3D MAX(tsz, 16); /* TODO: ARMv8.2-LVA */ --=20 2.20.1 From nobody Thu Nov 13 14:55:57 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581450308532465.57692534428907; Tue, 11 Feb 2020 11:45:08 -0800 (PST) Received: from localhost ([::1]:56512 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j1bT0-0005er-Ps for importer@patchew.org; Tue, 11 Feb 2020 14:45:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33625) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j1bQZ-00038D-1W for qemu-devel@nongnu.org; Tue, 11 Feb 2020 14:42:36 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j1bQX-000275-Ln for qemu-devel@nongnu.org; Tue, 11 Feb 2020 14:42:34 -0500 Received: from mail-pf1-x443.google.com ([2607:f8b0:4864:20::443]:46471) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j1bQX-000257-Fr for qemu-devel@nongnu.org; Tue, 11 Feb 2020 14:42:33 -0500 Received: by mail-pf1-x443.google.com with SMTP id k29so5985470pfp.13 for ; Tue, 11 Feb 2020 11:42:33 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id b18sm5306281pfd.63.2020.02.11.11.42.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Feb 2020 11:42:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cuIlZvUXMnVPxJ3FgP3jCwxFvB2IJPIWn75y+XC+HB0=; b=kVIrv8KNznyyr35Wb8dBxsS5No5cIV2FxJPS4OBmMFTW+0waDjoNPNdjdaox9rznOO Nw40AsEZmj6q7PaEL8byPVWhzBCcg/51IaPOKwGSgaxlkM4Jf4o2JlhJ6QreMNcOaLzV aHPBQy538pz7u+u4nattRixtiLcholEoQBMd1C52Q+khjZnwiKFQi3NGL1LRQQ1eSTlJ azAVcoJQRxpP7+RtyUhkXvOij2KRSx4J4G7MUGUJktmLxEEqWfkBatMpJTIGRcPUwB0/ vgYf9PYFTxQBR3SH26Mb12zZEaEbR3Y2feyluEKOOtKobGDxNkInP13yzdEk6mHGr7NJ 4Xng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cuIlZvUXMnVPxJ3FgP3jCwxFvB2IJPIWn75y+XC+HB0=; b=i4qC9IsDu3PcjIueYWQ3Sv0APDSroPbtTNUkWJK3WmSr4nL1PNrB1tOhC0IPowYxJG RPO1K+mHQpwD7bXwQbDyyol5RrWOD3jd6gVZtZDD8FR9FzWFa5uzCN9yV9ZrlwlxqTiT xVDYI9jtTFrblSneR9rd9mUjhK1MEQx4SrKWC6ApBTTt0jvRp1/rFh0gJ7ldP9bcbuf1 rFmt6tHCjv3SkGREVqbSjJdRSfZiieeqduJHhC14GPGWSYweq9zJYWrImcyH4NteTEK3 JtYD+tt6MHeui1Xhsde/3f226N+y+wYJ26Qhp3KPwmnf7bgMgz0wZzqkDCvSHFW0NO6K ua7g== X-Gm-Message-State: APjAAAV026J7vm89cH5RAOiuJrQ/qhGp+nPh+5dV22mpfVKqnYkx0yzS t7ESeZqOThQLkoJGmbgNv/ZHiQAZS8A= X-Google-Smtp-Source: APXvYqztrVHkJawv27iuRxx0N+94cQKYfeOk6Qfj9Ssc0J/KNCcgph2bzEtypZXv6mr2Q64ukYRmvg== X-Received: by 2002:aa7:96b0:: with SMTP id g16mr4461787pfk.99.1581450152039; Tue, 11 Feb 2020 11:42:32 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 2/2] target/arm: Split out aa64_va_parameter_tbi, aa64_va_parameter_tbid Date: Tue, 11 Feb 2020 11:42:28 -0800 Message-Id: <20200211194228.16907-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200211194228.16907-1-richard.henderson@linaro.org> References: <20200211194228.16907-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" For the purpose of rebuild_hflags_a64, we do not need to compute all of the va parameters, only tbi. Moreover, we can compute them in a form that is more useful to storing in hflags. This eliminates the need for aa64_va_parameter_both, so fold that in to aa64_va_parameter. The remaining calls to aa64_va_parameter are in get_phys_addr_lpae and in pauth_helper.c. This reduces the total cpu consumption of aa64_va_parameter in a kernel boot plus a kvm guest kernel boot from 3% to 0.5%. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/internals.h | 3 -- target/arm/helper.c | 68 +++++++++++++++++++++++------------------- 2 files changed, 37 insertions(+), 34 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 6d4a942bde..6ac84bbca7 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1042,15 +1042,12 @@ typedef struct ARMVAParameters { unsigned tsz : 8; unsigned select : 1; bool tbi : 1; - bool tbid : 1; bool epd : 1; bool hpd : 1; bool using16k : 1; bool using64k : 1; } ARMVAParameters; =20 -ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, - ARMMMUIdx mmu_idx); ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, ARMMMUIdx mmu_idx, bool data); =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index a008c70c87..9ebd7e9459 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10067,12 +10067,34 @@ static uint8_t convert_stage2_attrs(CPUARMState *= env, uint8_t s2attrs) } #endif /* !CONFIG_USER_ONLY */ =20 -ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, - ARMMMUIdx mmu_idx) +static int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx) +{ + if (regime_has_2_ranges(mmu_idx)) { + return extract64(tcr, 37, 2); + } else if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { + return 0; /* VTCR_EL2 */ + } else { + return extract32(tcr, 20, 1); + } +} + +static int aa64_va_parameter_tbid(uint64_t tcr, ARMMMUIdx mmu_idx) +{ + if (regime_has_2_ranges(mmu_idx)) { + return extract64(tcr, 51, 2); + } else if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { + return 0; /* VTCR_EL2 */ + } else { + return extract32(tcr, 29, 1); + } +} + +ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, + ARMMMUIdx mmu_idx, bool data) { uint64_t tcr =3D regime_tcr(env, mmu_idx)->raw_tcr; - bool tbi, tbid, epd, hpd, using16k, using64k; - int select, tsz; + bool epd, hpd, using16k, using64k; + int select, tsz, tbi; =20 if (!regime_has_2_ranges(mmu_idx)) { select =3D 0; @@ -10081,11 +10103,9 @@ ARMVAParameters aa64_va_parameters_both(CPUARMStat= e *env, uint64_t va, using16k =3D extract32(tcr, 15, 1); if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { /* VTCR_EL2 */ - tbi =3D tbid =3D hpd =3D false; + hpd =3D false; } else { - tbi =3D extract32(tcr, 20, 1); hpd =3D extract32(tcr, 24, 1); - tbid =3D extract32(tcr, 29, 1); } epd =3D false; } else { @@ -10099,28 +10119,30 @@ ARMVAParameters aa64_va_parameters_both(CPUARMSta= te *env, uint64_t va, epd =3D extract32(tcr, 7, 1); using64k =3D extract32(tcr, 14, 1); using16k =3D extract32(tcr, 15, 1); - tbi =3D extract64(tcr, 37, 1); hpd =3D extract64(tcr, 41, 1); - tbid =3D extract64(tcr, 51, 1); } else { int tg =3D extract32(tcr, 30, 2); using16k =3D tg =3D=3D 1; using64k =3D tg =3D=3D 3; tsz =3D extract32(tcr, 16, 6); epd =3D extract32(tcr, 23, 1); - tbi =3D extract64(tcr, 38, 1); hpd =3D extract64(tcr, 42, 1); - tbid =3D extract64(tcr, 52, 1); } } tsz =3D MIN(tsz, 39); /* TODO: ARMv8.4-TTST */ tsz =3D MAX(tsz, 16); /* TODO: ARMv8.2-LVA */ =20 + /* Present TBI as a composite with TBID. */ + tbi =3D aa64_va_parameter_tbi(tcr, mmu_idx); + if (!data) { + tbi &=3D ~aa64_va_parameter_tbid(tcr, mmu_idx); + } + tbi =3D (tbi >> select) & 1; + return (ARMVAParameters) { .tsz =3D tsz, .select =3D select, .tbi =3D tbi, - .tbid =3D tbid, .epd =3D epd, .hpd =3D hpd, .using16k =3D using16k, @@ -10128,16 +10150,6 @@ ARMVAParameters aa64_va_parameters_both(CPUARMStat= e *env, uint64_t va, }; } =20 -ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, - ARMMMUIdx mmu_idx, bool data) -{ - ARMVAParameters ret =3D aa64_va_parameters_both(env, va, mmu_idx); - - /* Present TBI as a composite with TBID. */ - ret.tbi &=3D (data || !ret.tbid); - return ret; -} - #ifndef CONFIG_USER_ONLY static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va, ARMMMUIdx mmu_idx) @@ -11957,21 +11969,15 @@ static uint32_t rebuild_hflags_a64(CPUARMState *e= nv, int el, int fp_el, { uint32_t flags =3D rebuild_hflags_aprofile(env); ARMMMUIdx stage1 =3D stage_1_mmu_idx(mmu_idx); - ARMVAParameters p0 =3D aa64_va_parameters_both(env, 0, stage1); + uint64_t tcr =3D regime_tcr(env, mmu_idx)->raw_tcr; uint64_t sctlr; int tbii, tbid; =20 flags =3D FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1); =20 /* Get control bits for tagged addresses. */ - if (regime_has_2_ranges(mmu_idx)) { - ARMVAParameters p1 =3D aa64_va_parameters_both(env, -1, stage1); - tbid =3D (p1.tbi << 1) | p0.tbi; - tbii =3D tbid & ~((p1.tbid << 1) | p0.tbid); - } else { - tbid =3D p0.tbi; - tbii =3D tbid & !p0.tbid; - } + tbid =3D aa64_va_parameter_tbi(tcr, mmu_idx); + tbii =3D tbid & ~aa64_va_parameter_tbid(tcr, mmu_idx); =20 flags =3D FIELD_DP32(flags, TBFLAG_A64, TBII, tbii); flags =3D FIELD_DP32(flags, TBFLAG_A64, TBID, tbid); --=20 2.20.1