From nobody Thu Nov 13 16:18:21 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581322432698212.56521618004945; Mon, 10 Feb 2020 00:13:52 -0800 (PST) Received: from localhost ([::1]:58134 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j14CV-00055m-1C for importer@patchew.org; Mon, 10 Feb 2020 03:13:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36605) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j14Bi-0003pS-78 for qemu-devel@nongnu.org; Mon, 10 Feb 2020 03:13:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j14Bg-0008Fx-Qq for qemu-devel@nongnu.org; Mon, 10 Feb 2020 03:13:02 -0500 Received: from smtp2200-217.mail.aliyun.com ([121.197.200.217]:33823) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j14Bf-0008Ba-C2; Mon, 10 Feb 2020 03:13:00 -0500 Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.GmO5bfp_1581322371) by smtp.aliyun-inc.com(10.147.40.44); Mon, 10 Feb 2020 16:12:52 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07436321|-1; CH=green; DM=CONTINUE|CONTINUE|true|0.180639-0.0234635-0.795898; DS=CONTINUE|ham_system_inform|0.0341154-9.33865e-05-0.965791; FP=0|0|0|0|0|-1|-1|-1; HT=e02c03296; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=9; RT=9; SR=0; TI=SMTPD_---.GmO5bfp_1581322371; From: LIU Zhiwei To: richard.henderson@linaro.org, alistair23@gmail.com, chihmin.chao@sifive.com, palmer@dabbelt.com Subject: [PATCH v4 2/4] target/riscv: configure and turn on vector extension from command line Date: Mon, 10 Feb 2020 16:12:38 +0800 Message-Id: <20200210081240.11481-3-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200210081240.11481-1-zhiwei_liu@c-sky.com> References: <20200210081240.11481-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 121.197.200.217 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wenmeng_zhang@c-sky.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, wxy194768@alibaba-inc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Vector extension is default on only for "any" cpu. It can be turned on by command line "-cpu rv64,v=3Dtrue,vlen=3D128,elen=3D64,vext_spec=3Dv0.= 7.1". vlen is the vector register length, default value is 128 bit. elen is the max operator size in bits, default value is 64 bit. vext_spec is the vector specification version, default value is v0.7.1. Thest properties and cpu can be specified with other values. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/cpu.c | 48 ++++++++++++++++++++++++++++++++++++++++++++-- target/riscv/cpu.h | 8 ++++++++ 2 files changed, 54 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8c86ebc109..95fdb6261e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -98,6 +98,11 @@ static void set_priv_version(CPURISCVState *env, int pri= v_ver) env->priv_ver =3D priv_ver; } =20 +static void set_vext_version(CPURISCVState *env, int vext_ver) +{ + env->vext_ver =3D vext_ver; +} + static void set_feature(CPURISCVState *env, int feature) { env->features |=3D (1ULL << feature); @@ -113,7 +118,7 @@ static void set_resetvec(CPURISCVState *env, int resetv= ec) static void riscv_any_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; - set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU); + set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU | RVV); set_priv_version(env, PRIV_VERSION_1_11_0); set_resetvec(env, DEFAULT_RSTVEC); } @@ -320,6 +325,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error *= *errp) CPURISCVState *env =3D &cpu->env; RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(dev); int priv_version =3D PRIV_VERSION_1_11_0; + int vext_version =3D VEXT_VERSION_0_07_1; target_ulong target_misa =3D 0; Error *local_err =3D NULL; =20 @@ -343,8 +349,18 @@ static void riscv_cpu_realize(DeviceState *dev, Error = **errp) return; } } - + if (cpu->cfg.vext_spec) { + if (!g_strcmp0(cpu->cfg.vext_spec, "v0.7.1")) { + vext_version =3D VEXT_VERSION_0_07_1; + } else { + error_setg(errp, + "Unsupported vector spec version '%s'", + cpu->cfg.vext_spec); + return; + } + } set_priv_version(env, priv_version); + set_vext_version(env, vext_version); set_resetvec(env, DEFAULT_RSTVEC); =20 if (cpu->cfg.mmu) { @@ -409,6 +425,30 @@ static void riscv_cpu_realize(DeviceState *dev, Error = **errp) if (cpu->cfg.ext_u) { target_misa |=3D RVU; } + if (cpu->cfg.ext_v) { + target_misa |=3D RVV; + if (!is_power_of_2(cpu->cfg.vlen)) { + error_setg(errp, + "Vector extension VLEN must be power of 2"); + return; + } + if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { + error_setg(errp, + "Vector extension implementation only supports VLEN= " + "in the range [128, %d]", RV_VLEN_MAX); + return; + } + if (!is_power_of_2(cpu->cfg.elen)) { + error_setg(errp, + "Vector extension ELEN must be power of 2"); + return; + } + if (cpu->cfg.elen > 64) { + error_setg(errp, + "Vector extension ELEN must <=3D 64"); + return; + } + } =20 set_misa(env, RVXLEN | target_misa); } @@ -444,10 +484,14 @@ static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), + DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), + DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), + DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), + DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), DEFINE_PROP_END_OF_LIST(), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 07e63016a7..bf2b4b55af 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -64,6 +64,7 @@ #define RVA RV('A') #define RVF RV('F') #define RVD RV('D') +#define RVV RV('V') #define RVC RV('C') #define RVS RV('S') #define RVU RV('U') @@ -82,6 +83,8 @@ enum { #define PRIV_VERSION_1_10_0 0x00011000 #define PRIV_VERSION_1_11_0 0x00011100 =20 +#define VEXT_VERSION_0_07_1 0x00000701 + #define TRANSLATE_PMP_FAIL 2 #define TRANSLATE_FAIL 1 #define TRANSLATE_SUCCESS 0 @@ -118,6 +121,7 @@ struct CPURISCVState { target_ulong badaddr; =20 target_ulong priv_ver; + target_ulong vext_ver; target_ulong misa; target_ulong misa_mask; =20 @@ -226,12 +230,16 @@ typedef struct RISCVCPU { bool ext_c; bool ext_s; bool ext_u; + bool ext_v; bool ext_counters; bool ext_ifencei; bool ext_icsr; =20 char *priv_spec; char *user_spec; + char *vext_spec; + uint16_t vlen; + uint16_t elen; bool mmu; bool pmp; } cfg; --=20 2.23.0