From nobody Thu Nov 13 16:18:22 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581322507539589.6979812399333; Mon, 10 Feb 2020 00:15:07 -0800 (PST) Received: from localhost ([::1]:58146 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j14Dh-0006MQ-PC for importer@patchew.org; Mon, 10 Feb 2020 03:15:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36572) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j14Bh-0003o5-9m for qemu-devel@nongnu.org; Mon, 10 Feb 2020 03:13:02 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j14Bf-0008FA-VP for qemu-devel@nongnu.org; Mon, 10 Feb 2020 03:13:00 -0500 Received: from smtp2200-217.mail.aliyun.com ([121.197.200.217]:35109) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j14Bf-0008BZ-GH; Mon, 10 Feb 2020 03:12:59 -0500 Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.GmO5bfp_1581322371) by smtp.aliyun-inc.com(10.147.40.44); Mon, 10 Feb 2020 16:12:52 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.1258004|-1; CH=green; DM=CONTINUE|CONTINUE|true|0.163513-0.02035-0.816137; DS=CONTINUE|ham_system_inform|0.0341501-0.000480858-0.965369; FP=0|0|0|0|0|-1|-1|-1; HT=e02c03306; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=9; RT=9; SR=0; TI=SMTPD_---.GmO5bfp_1581322371; From: LIU Zhiwei To: richard.henderson@linaro.org, alistair23@gmail.com, chihmin.chao@sifive.com, palmer@dabbelt.com Subject: [PATCH v4 1/4] target/riscv: add vector extension field in CPURISCVState Date: Mon, 10 Feb 2020 16:12:37 +0800 Message-Id: <20200210081240.11481-2-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200210081240.11481-1-zhiwei_liu@c-sky.com> References: <20200210081240.11481-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 121.197.200.217 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wenmeng_zhang@c-sky.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, wxy194768@alibaba-inc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The 32 vector registers will be viewed as a continuous memory block. It avoids the convension between element index and (regno,offset). Thus elements can be directly accessed by offset from the first vector base address. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/cpu.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index de0a8d893a..07e63016a7 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -93,9 +93,22 @@ typedef struct CPURISCVState CPURISCVState; =20 #include "pmp.h" =20 +#define RV_VLEN_MAX 512 + struct CPURISCVState { target_ulong gpr[32]; uint64_t fpr[32]; /* assume both F and D extensions */ + + /* vector coprocessor state. */ + struct { + uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); + target_ulong vxrm; + target_ulong vxsat; + target_ulong vl; + target_ulong vstart; + target_ulong vtype; + } vext; + target_ulong pc; target_ulong load_res; target_ulong load_val; --=20 2.23.0