From nobody Thu Nov 13 14:54:33 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581322507539589.6979812399333; Mon, 10 Feb 2020 00:15:07 -0800 (PST) Received: from localhost ([::1]:58146 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j14Dh-0006MQ-PC for importer@patchew.org; Mon, 10 Feb 2020 03:15:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36572) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j14Bh-0003o5-9m for qemu-devel@nongnu.org; Mon, 10 Feb 2020 03:13:02 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j14Bf-0008FA-VP for qemu-devel@nongnu.org; Mon, 10 Feb 2020 03:13:00 -0500 Received: from smtp2200-217.mail.aliyun.com ([121.197.200.217]:35109) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j14Bf-0008BZ-GH; Mon, 10 Feb 2020 03:12:59 -0500 Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.GmO5bfp_1581322371) by smtp.aliyun-inc.com(10.147.40.44); Mon, 10 Feb 2020 16:12:52 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.1258004|-1; CH=green; DM=CONTINUE|CONTINUE|true|0.163513-0.02035-0.816137; DS=CONTINUE|ham_system_inform|0.0341501-0.000480858-0.965369; FP=0|0|0|0|0|-1|-1|-1; HT=e02c03306; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=9; RT=9; SR=0; TI=SMTPD_---.GmO5bfp_1581322371; From: LIU Zhiwei To: richard.henderson@linaro.org, alistair23@gmail.com, chihmin.chao@sifive.com, palmer@dabbelt.com Subject: [PATCH v4 1/4] target/riscv: add vector extension field in CPURISCVState Date: Mon, 10 Feb 2020 16:12:37 +0800 Message-Id: <20200210081240.11481-2-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200210081240.11481-1-zhiwei_liu@c-sky.com> References: <20200210081240.11481-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 121.197.200.217 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wenmeng_zhang@c-sky.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, wxy194768@alibaba-inc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The 32 vector registers will be viewed as a continuous memory block. It avoids the convension between element index and (regno,offset). Thus elements can be directly accessed by offset from the first vector base address. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/cpu.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index de0a8d893a..07e63016a7 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -93,9 +93,22 @@ typedef struct CPURISCVState CPURISCVState; =20 #include "pmp.h" =20 +#define RV_VLEN_MAX 512 + struct CPURISCVState { target_ulong gpr[32]; uint64_t fpr[32]; /* assume both F and D extensions */ + + /* vector coprocessor state. */ + struct { + uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); + target_ulong vxrm; + target_ulong vxsat; + target_ulong vl; + target_ulong vstart; + target_ulong vtype; + } vext; + target_ulong pc; target_ulong load_res; target_ulong load_val; --=20 2.23.0 From nobody Thu Nov 13 14:54:33 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581322432698212.56521618004945; Mon, 10 Feb 2020 00:13:52 -0800 (PST) Received: from localhost ([::1]:58134 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j14CV-00055m-1C for importer@patchew.org; Mon, 10 Feb 2020 03:13:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36605) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j14Bi-0003pS-78 for qemu-devel@nongnu.org; Mon, 10 Feb 2020 03:13:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j14Bg-0008Fx-Qq for qemu-devel@nongnu.org; Mon, 10 Feb 2020 03:13:02 -0500 Received: from smtp2200-217.mail.aliyun.com ([121.197.200.217]:33823) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j14Bf-0008Ba-C2; Mon, 10 Feb 2020 03:13:00 -0500 Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.GmO5bfp_1581322371) by smtp.aliyun-inc.com(10.147.40.44); Mon, 10 Feb 2020 16:12:52 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07436321|-1; CH=green; DM=CONTINUE|CONTINUE|true|0.180639-0.0234635-0.795898; DS=CONTINUE|ham_system_inform|0.0341154-9.33865e-05-0.965791; FP=0|0|0|0|0|-1|-1|-1; HT=e02c03296; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=9; RT=9; SR=0; TI=SMTPD_---.GmO5bfp_1581322371; From: LIU Zhiwei To: richard.henderson@linaro.org, alistair23@gmail.com, chihmin.chao@sifive.com, palmer@dabbelt.com Subject: [PATCH v4 2/4] target/riscv: configure and turn on vector extension from command line Date: Mon, 10 Feb 2020 16:12:38 +0800 Message-Id: <20200210081240.11481-3-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200210081240.11481-1-zhiwei_liu@c-sky.com> References: <20200210081240.11481-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 121.197.200.217 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wenmeng_zhang@c-sky.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, wxy194768@alibaba-inc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Vector extension is default on only for "any" cpu. It can be turned on by command line "-cpu rv64,v=3Dtrue,vlen=3D128,elen=3D64,vext_spec=3Dv0.= 7.1". vlen is the vector register length, default value is 128 bit. elen is the max operator size in bits, default value is 64 bit. vext_spec is the vector specification version, default value is v0.7.1. Thest properties and cpu can be specified with other values. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/cpu.c | 48 ++++++++++++++++++++++++++++++++++++++++++++-- target/riscv/cpu.h | 8 ++++++++ 2 files changed, 54 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8c86ebc109..95fdb6261e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -98,6 +98,11 @@ static void set_priv_version(CPURISCVState *env, int pri= v_ver) env->priv_ver =3D priv_ver; } =20 +static void set_vext_version(CPURISCVState *env, int vext_ver) +{ + env->vext_ver =3D vext_ver; +} + static void set_feature(CPURISCVState *env, int feature) { env->features |=3D (1ULL << feature); @@ -113,7 +118,7 @@ static void set_resetvec(CPURISCVState *env, int resetv= ec) static void riscv_any_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; - set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU); + set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU | RVV); set_priv_version(env, PRIV_VERSION_1_11_0); set_resetvec(env, DEFAULT_RSTVEC); } @@ -320,6 +325,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error *= *errp) CPURISCVState *env =3D &cpu->env; RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(dev); int priv_version =3D PRIV_VERSION_1_11_0; + int vext_version =3D VEXT_VERSION_0_07_1; target_ulong target_misa =3D 0; Error *local_err =3D NULL; =20 @@ -343,8 +349,18 @@ static void riscv_cpu_realize(DeviceState *dev, Error = **errp) return; } } - + if (cpu->cfg.vext_spec) { + if (!g_strcmp0(cpu->cfg.vext_spec, "v0.7.1")) { + vext_version =3D VEXT_VERSION_0_07_1; + } else { + error_setg(errp, + "Unsupported vector spec version '%s'", + cpu->cfg.vext_spec); + return; + } + } set_priv_version(env, priv_version); + set_vext_version(env, vext_version); set_resetvec(env, DEFAULT_RSTVEC); =20 if (cpu->cfg.mmu) { @@ -409,6 +425,30 @@ static void riscv_cpu_realize(DeviceState *dev, Error = **errp) if (cpu->cfg.ext_u) { target_misa |=3D RVU; } + if (cpu->cfg.ext_v) { + target_misa |=3D RVV; + if (!is_power_of_2(cpu->cfg.vlen)) { + error_setg(errp, + "Vector extension VLEN must be power of 2"); + return; + } + if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { + error_setg(errp, + "Vector extension implementation only supports VLEN= " + "in the range [128, %d]", RV_VLEN_MAX); + return; + } + if (!is_power_of_2(cpu->cfg.elen)) { + error_setg(errp, + "Vector extension ELEN must be power of 2"); + return; + } + if (cpu->cfg.elen > 64) { + error_setg(errp, + "Vector extension ELEN must <=3D 64"); + return; + } + } =20 set_misa(env, RVXLEN | target_misa); } @@ -444,10 +484,14 @@ static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), + DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), + DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), + DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), + DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), DEFINE_PROP_END_OF_LIST(), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 07e63016a7..bf2b4b55af 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -64,6 +64,7 @@ #define RVA RV('A') #define RVF RV('F') #define RVD RV('D') +#define RVV RV('V') #define RVC RV('C') #define RVS RV('S') #define RVU RV('U') @@ -82,6 +83,8 @@ enum { #define PRIV_VERSION_1_10_0 0x00011000 #define PRIV_VERSION_1_11_0 0x00011100 =20 +#define VEXT_VERSION_0_07_1 0x00000701 + #define TRANSLATE_PMP_FAIL 2 #define TRANSLATE_FAIL 1 #define TRANSLATE_SUCCESS 0 @@ -118,6 +121,7 @@ struct CPURISCVState { target_ulong badaddr; =20 target_ulong priv_ver; + target_ulong vext_ver; target_ulong misa; target_ulong misa_mask; =20 @@ -226,12 +230,16 @@ typedef struct RISCVCPU { bool ext_c; bool ext_s; bool ext_u; + bool ext_v; bool ext_counters; bool ext_ifencei; bool ext_icsr; =20 char *priv_spec; char *user_spec; + char *vext_spec; + uint16_t vlen; + uint16_t elen; bool mmu; bool pmp; } cfg; --=20 2.23.0 From nobody Thu Nov 13 14:54:33 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581322594425265.0331653428675; Mon, 10 Feb 2020 00:16:34 -0800 (PST) Received: from localhost ([::1]:58174 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j14F7-0007MR-0b for importer@patchew.org; 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MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=9; RT=9; SR=0; TI=SMTPD_---.GmO5bfp_1581322371; From: LIU Zhiwei To: richard.henderson@linaro.org, alistair23@gmail.com, chihmin.chao@sifive.com, palmer@dabbelt.com Subject: [PATCH v4 3/4] target/riscv: support vector extension csr Date: Mon, 10 Feb 2020 16:12:39 +0800 Message-Id: <20200210081240.11481-4-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200210081240.11481-1-zhiwei_liu@c-sky.com> References: <20200210081240.11481-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 121.197.200.217 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wenmeng_zhang@c-sky.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, wxy194768@alibaba-inc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The v0.7.1 specification does not define vector status within mstatus. A future revision will define the privileged portion of the vector status. Signed-off-by: LIU Zhiwei --- target/riscv/cpu_bits.h | 15 +++++++++ target/riscv/csr.c | 72 +++++++++++++++++++++++++++++++++++++++-- 2 files changed, 84 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index e99834856c..1f588ebc14 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -29,6 +29,14 @@ #define FSR_NXA (FPEXC_NX << FSR_AEXC_SHIFT) #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_N= XA) =20 +/* Vector Fixed-Point round model */ +#define FSR_VXRM_SHIFT 9 +#define FSR_VXRM (0x3 << FSR_VXRM_SHIFT) + +/* Vector Fixed-Point saturation flag */ +#define FSR_VXSAT_SHIFT 8 +#define FSR_VXSAT (0x1 << FSR_VXSAT_SHIFT) + /* Control and Status Registers */ =20 /* User Trap Setup */ @@ -48,6 +56,13 @@ #define CSR_FRM 0x002 #define CSR_FCSR 0x003 =20 +/* User Vector CSRs */ +#define CSR_VSTART 0x008 +#define CSR_VXSAT 0x009 +#define CSR_VXRM 0x00a +#define CSR_VL 0xc20 +#define CSR_VTYPE 0xc21 + /* User Timers and Counters */ #define CSR_CYCLE 0xc00 #define CSR_TIME 0xc01 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 0e34c292c5..4696c8c180 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -46,6 +46,10 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *= ops) static int fs(CPURISCVState *env, int csrno) { #if !defined(CONFIG_USER_ONLY) + /* loose check condition for fcsr in vector extension */ + if ((csrno =3D=3D CSR_FCSR) && (env->misa & RVV)) { + return 0; + } if (!env->debugger && !riscv_cpu_fp_enabled(env)) { return -1; } @@ -53,6 +57,11 @@ static int fs(CPURISCVState *env, int csrno) return 0; } =20 +static int vs(CPURISCVState *env, int csrno) +{ + return 0; +} + static int ctr(CPURISCVState *env, int csrno) { #if !defined(CONFIG_USER_ONLY) @@ -158,8 +167,10 @@ static int read_fcsr(CPURISCVState *env, int csrno, ta= rget_ulong *val) return -1; } #endif - *val =3D (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT) - | (env->frm << FSR_RD_SHIFT); + *val =3D (env->vext.vxrm << FSR_VXRM_SHIFT) + | (env->vext.vxsat << FSR_VXSAT_SHIFT) + | (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT) + | (env->frm << FSR_RD_SHIFT); return 0; } =20 @@ -172,10 +183,60 @@ static int write_fcsr(CPURISCVState *env, int csrno, = target_ulong val) env->mstatus |=3D MSTATUS_FS; #endif env->frm =3D (val & FSR_RD) >> FSR_RD_SHIFT; + env->vext.vxrm =3D (val & FSR_VXRM) >> FSR_VXRM_SHIFT; + env->vext.vxsat =3D (val & FSR_VXSAT) >> FSR_VXSAT_SHIFT; riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT); return 0; } =20 +static int read_vtype(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->vext.vtype; + return 0; +} + +static int read_vl(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->vext.vl; + return 0; +} + +static int read_vxrm(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->vext.vxrm; + return 0; +} + +static int read_vxsat(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->vext.vxsat; + return 0; +} + +static int read_vstart(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->vext.vstart; + return 0; +} + +static int write_vxrm(CPURISCVState *env, int csrno, target_ulong val) +{ + env->vext.vxrm =3D val; + return 0; +} + +static int write_vxsat(CPURISCVState *env, int csrno, target_ulong val) +{ + env->vext.vxsat =3D val; + return 0; +} + +static int write_vstart(CPURISCVState *env, int csrno, target_ulong val) +{ + env->vext.vstart =3D val; + return 0; +} + /* User Timers and Counters */ static int read_instret(CPURISCVState *env, int csrno, target_ulong *val) { @@ -877,7 +938,12 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = =3D { [CSR_FFLAGS] =3D { fs, read_fflags, write_fflags = }, [CSR_FRM] =3D { fs, read_frm, write_frm = }, [CSR_FCSR] =3D { fs, read_fcsr, write_fcsr = }, - + /* Vector CSRs */ + [CSR_VSTART] =3D { vs, read_vstart, write_vstart = }, + [CSR_VXSAT] =3D { vs, read_vxsat, write_vxsat = }, + [CSR_VXRM] =3D { vs, read_vxrm, write_vxrm = }, + [CSR_VL] =3D { vs, read_vl = }, + [CSR_VTYPE] =3D { vs, read_vtype = }, /* User Timers and Counters */ [CSR_CYCLE] =3D { ctr, read_instret = }, [CSR_INSTRET] =3D { ctr, read_instret = }, --=20 2.23.0 From nobody Thu Nov 13 14:54:33 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Mon, 10 Feb 2020 03:13:00 -0500 Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.GmO5bfp_1581322371) by smtp.aliyun-inc.com(10.147.40.44); Mon, 10 Feb 2020 16:12:53 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07436282|-1; CH=green; DM=CONTINUE|CONTINUE|true|0.5349-0.0192359-0.445864; DS=CONTINUE|ham_alarm|0.0401062-0.000542533-0.959351; FP=0|0|0|0|0|-1|-1|-1; HT=e01l07447; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=9; RT=9; SR=0; TI=SMTPD_---.GmO5bfp_1581322371; From: LIU Zhiwei To: richard.henderson@linaro.org, alistair23@gmail.com, chihmin.chao@sifive.com, palmer@dabbelt.com Subject: [PATCH v4 4/4] target/riscv: add vector configure instruction Date: Mon, 10 Feb 2020 16:12:40 +0800 Message-Id: <20200210081240.11481-5-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200210081240.11481-1-zhiwei_liu@c-sky.com> References: <20200210081240.11481-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 121.197.200.217 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wenmeng_zhang@c-sky.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, wxy194768@alibaba-inc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags should update after configure instructions. The (ill, lmul, sew ) of vtype and the bit of (VSTART =3D=3D 0 && VL =3D=3D VLMAX) will be placed within t= b_flags. Signed-off-by: LIU Zhiwei --- MAINTAINERS | 1 + target/riscv/Makefile.objs | 2 +- target/riscv/cpu.h | 61 +++++++++++++++++++--- target/riscv/helper.h | 2 + target/riscv/insn32.decode | 5 ++ target/riscv/insn_trans/trans_rvv.inc.c | 69 +++++++++++++++++++++++++ target/riscv/translate.c | 17 +++++- target/riscv/vector_helper.c | 49 ++++++++++++++++++ 8 files changed, 195 insertions(+), 11 deletions(-) create mode 100644 target/riscv/insn_trans/trans_rvv.inc.c create mode 100644 target/riscv/vector_helper.c diff --git a/MAINTAINERS b/MAINTAINERS index e72b5e5f69..015e9239b5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -266,6 +266,7 @@ M: Palmer Dabbelt M: Alistair Francis M: Sagar Karandikar M: Bastian Koppelmann +M: LIU Zhiwei L: qemu-riscv@nongnu.org S: Supported F: target/riscv/ diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs index ff651f69f6..ff38df6219 100644 --- a/target/riscv/Makefile.objs +++ b/target/riscv/Makefile.objs @@ -1,4 +1,4 @@ -obj-y +=3D translate.o op_helper.o cpu_helper.o cpu.o csr.o fpu_helper.o g= dbstub.o +obj-y +=3D translate.o op_helper.o cpu_helper.o cpu.o csr.o fpu_helper.o v= ector_helper.o gdbstub.o obj-$(CONFIG_SOFTMMU) +=3D pmp.o =20 ifeq ($(CONFIG_SOFTMMU),y) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index bf2b4b55af..f857845285 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -21,6 +21,7 @@ #define RISCV_CPU_H =20 #include "hw/core/cpu.h" +#include "hw/registerfields.h" #include "exec/cpu-defs.h" #include "fpu/softfloat-types.h" =20 @@ -98,6 +99,10 @@ typedef struct CPURISCVState CPURISCVState; =20 #define RV_VLEN_MAX 512 =20 +FIELD(VTYPE, LMUL, 0, 2) +FIELD(VTYPE, SEW, 2, 3) +FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 2, 1) + struct CPURISCVState { target_ulong gpr[32]; uint64_t fpr[32]; /* assume both F and D extensions */ @@ -306,16 +311,61 @@ void riscv_cpu_set_fflags(CPURISCVState *env, target_= ulong); #define TB_FLAGS_MMU_MASK 3 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS =20 +typedef CPURISCVState CPUArchState; +typedef RISCVCPU ArchCPU; +#include "exec/cpu-all.h" + +FIELD(TB_FLAGS, VL_EQ_VLMAX, 2, 1) +FIELD(TB_FLAGS, LMUL, 3, 2) +FIELD(TB_FLAGS, SEW, 5, 3) +FIELD(TB_FLAGS, VILL, 8, 1) + +/* + * A simplification for VLMAX + * =3D (1 << LMUL) * VLEN / (8 * (1 << SEW)) + * =3D (VLEN << LMUL) / (8 << SEW) + * =3D (VLEN << LMUL) >> (SEW + 3) + * =3D VLEN >> (SEW + 3 - LMUL) + */ +static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) +{ + uint8_t sew, lmul; + + sew =3D FIELD_EX64(vtype, VTYPE, SEW); + lmul =3D FIELD_EX64(vtype, VTYPE, LMUL); + return cpu->cfg.vlen >> (sew + 3 - lmul); +} + static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *= pc, - target_ulong *cs_base, uint32_t *f= lags) + target_ulong *cs_base, uint32_t *p= flags) { + uint32_t flags =3D 0; + uint32_t vlmax; + uint8_t vl_eq_vlmax; + *pc =3D env->pc; *cs_base =3D 0; + + if (env->misa & RVV) { + vlmax =3D vext_get_vlmax(env_archcpu(env), env->vext.vtype); + vl_eq_vlmax =3D (env->vext.vstart =3D=3D 0) && (vlmax =3D=3D env->= vext.vl); + flags =3D FIELD_DP32(flags, TB_FLAGS, VILL, + FIELD_EX64(env->vext.vtype, VTYPE, VILL)); + flags =3D FIELD_DP32(flags, TB_FLAGS, SEW, + FIELD_EX64(env->vext.vtype, VTYPE, SEW)); + flags =3D FIELD_DP32(flags, TB_FLAGS, LMUL, + FIELD_EX64(env->vext.vtype, VTYPE, LMUL)); + flags =3D FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); + } else { + flags =3D FIELD_DP32(flags, TB_FLAGS, VILL, 1); + } + #ifdef CONFIG_USER_ONLY - *flags =3D TB_FLAGS_MSTATUS_FS; + flags |=3D TB_FLAGS_MSTATUS_FS; #else - *flags =3D cpu_mmu_index(env, 0) | (env->mstatus & MSTATUS_FS); + flags |=3D cpu_mmu_index(env, 0) | (env->mstatus & MSTATUS_FS); #endif + *pflags =3D flags; } =20 int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, @@ -356,9 +406,4 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations = *ops); =20 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); =20 -typedef CPURISCVState CPUArchState; -typedef RISCVCPU ArchCPU; - -#include "exec/cpu-all.h" - #endif /* RISCV_CPU_H */ diff --git a/target/riscv/helper.h b/target/riscv/helper.h index debb22a480..3c28c7e407 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -76,3 +76,5 @@ DEF_HELPER_2(mret, tl, env, tl) DEF_HELPER_1(wfi, void, env) DEF_HELPER_1(tlb_flush, void, env) #endif +/* Vector functions */ +DEF_HELPER_3(vsetvl, tl, env, tl, tl) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 77f794ed70..5dc009c3cd 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -62,6 +62,7 @@ @r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd @r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd @r2 ....... ..... ..... ... ..... ....... %rs1 %rd +@r2_zimm . zimm:11 ..... ... ..... ....... %rs1 %rd =20 @sfence_vma ....... ..... ..... ... ..... ....... %rs2 %rs1 @sfence_vm ....... ..... ..... ... ..... ....... %rs1 @@ -203,3 +204,7 @@ fcvt_w_d 1100001 00000 ..... ... ..... 1010011 @r2_rm fcvt_wu_d 1100001 00001 ..... ... ..... 1010011 @r2_rm fcvt_d_w 1101001 00000 ..... ... ..... 1010011 @r2_rm fcvt_d_wu 1101001 00001 ..... ... ..... 1010011 @r2_rm + +# *** RV32V Extension *** +vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm +vsetvl 1000000 ..... ..... 111 ..... 1010111 @r diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_tr= ans/trans_rvv.inc.c new file mode 100644 index 0000000000..da82c72bbf --- /dev/null +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -0,0 +1,69 @@ +/* + * RISC-V translation routines for the RVV Standard Extension. + * + * Copyright (c) 2020 C-SKY Limited. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl * a) +{ + TCGv s1, s2, dst; + s2 =3D tcg_temp_new(); + dst =3D tcg_temp_new(); + + /* Using x0 as the rs1 register specifier, encodes an infinite AVL */ + if (a->rs1 =3D=3D 0) { + /* As the mask is at least one bit, RV_VLEN_MAX is >=3D VLMAX */ + s1 =3D tcg_const_tl(RV_VLEN_MAX); + } else { + s1 =3D tcg_temp_new(); + gen_get_gpr(s1, a->rs1); + } + gen_get_gpr(s2, a->rs2); + gen_helper_vsetvl(dst, cpu_env, s1, s2); + gen_set_gpr(a->rd, dst); + tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); + exit_tb(ctx); + ctx->base.is_jmp =3D DISAS_NORETURN; + + tcg_temp_free(s1); + tcg_temp_free(s2); + tcg_temp_free(dst); + return true; +} + +static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli * a) +{ + TCGv s1, s2, dst; + s2 =3D tcg_const_tl(a->zimm); + dst =3D tcg_temp_new(); + + /* Using x0 as the rs1 register specifier, encodes an infinite AVL */ + if (a->rs1 =3D=3D 0) { + /* As the mask is at least one bit, RV_VLEN_MAX is >=3D VLMAX */ + s1 =3D tcg_const_tl(RV_VLEN_MAX); + } else { + s1 =3D tcg_temp_new(); + gen_get_gpr(s1, a->rs1); + } + gen_helper_vsetvl(dst, cpu_env, s1, s2); + gen_set_gpr(a->rd, dst); + gen_goto_tb(ctx, 0, ctx->pc_succ_insn); + ctx->base.is_jmp =3D DISAS_NORETURN; + + tcg_temp_free(s1); + tcg_temp_free(s2); + tcg_temp_free(dst); + return true; +} diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 14dc71156b..cc356aabd8 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -55,6 +55,12 @@ typedef struct DisasContext { to reset this known value. */ int frm; bool ext_ifencei; + /* vector extension */ + bool vill; + uint8_t lmul; + uint8_t sew; + uint16_t vlen; + bool vl_eq_vlmax; } DisasContext; =20 #ifdef TARGET_RISCV64 @@ -704,6 +710,7 @@ static bool gen_shift(DisasContext *ctx, arg_r *a, #include "insn_trans/trans_rva.inc.c" #include "insn_trans/trans_rvf.inc.c" #include "insn_trans/trans_rvd.inc.c" +#include "insn_trans/trans_rvv.inc.c" #include "insn_trans/trans_privileged.inc.c" =20 /* Include the auto-generated decoder for 16 bit insn */ @@ -735,14 +742,20 @@ static void riscv_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) DisasContext *ctx =3D container_of(dcbase, DisasContext, base); CPURISCVState *env =3D cs->env_ptr; RISCVCPU *cpu =3D RISCV_CPU(cs); + uint32_t tb_flags =3D ctx->base.tb->flags; =20 ctx->pc_succ_insn =3D ctx->base.pc_first; - ctx->mem_idx =3D ctx->base.tb->flags & TB_FLAGS_MMU_MASK; - ctx->mstatus_fs =3D ctx->base.tb->flags & TB_FLAGS_MSTATUS_FS; + ctx->mem_idx =3D tb_flags & TB_FLAGS_MMU_MASK; + ctx->mstatus_fs =3D tb_flags & TB_FLAGS_MSTATUS_FS; ctx->priv_ver =3D env->priv_ver; ctx->misa =3D env->misa; ctx->frm =3D -1; /* unknown rounding mode */ ctx->ext_ifencei =3D cpu->cfg.ext_ifencei; + ctx->vlen =3D cpu->cfg.vlen; + ctx->vill =3D FIELD_EX32(tb_flags, TB_FLAGS, VILL); + ctx->sew =3D FIELD_EX32(tb_flags, TB_FLAGS, SEW); + ctx->lmul =3D FIELD_EX32(tb_flags, TB_FLAGS, LMUL); + ctx->vl_eq_vlmax =3D FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); } =20 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c new file mode 100644 index 0000000000..e0f2415345 --- /dev/null +++ b/target/riscv/vector_helper.c @@ -0,0 +1,49 @@ +/* + * RISC-V Vector Extension Helpers for QEMU. + * + * Copyright (c) 2020 C-SKY Limited. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "exec/exec-all.h" +#include "exec/helper-proto.h" +#include + +target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1, + target_ulong s2) +{ + int vlmax, vl; + RISCVCPU *cpu =3D env_archcpu(env); + uint16_t sew =3D 1 << FIELD_EX64(s2, VTYPE, SEW); + + if (sew > cpu->cfg.elen) { /* only set vill bit. */ + env->vext.vtype =3D FIELD_DP64(0, VTYPE, VILL, 1); + env->vext.vl =3D 0; + env->vext.vstart =3D 0; + return 0; + } + + vlmax =3D vext_get_vlmax(cpu, s2); + if (s1 <=3D vlmax) { + vl =3D s1; + } else { + vl =3D vlmax; + } + env->vext.vl =3D vl; + env->vext.vtype =3D s2; + env->vext.vstart =3D 0; + return vl; +} --=20 2.23.0