From nobody Thu Nov 13 13:33:30 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581167031786365.01185126101325; Sat, 8 Feb 2020 05:03:51 -0800 (PST) Received: from localhost ([::1]:41073 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j0Pm2-0001xa-Nr for importer@patchew.org; Sat, 08 Feb 2020 08:03:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41354) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j0Pgm-0000OW-8V for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:25 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j0Pgl-0004cL-4q for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:24 -0500 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:43667) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j0Pgk-0004bd-VC for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:23 -0500 Received: by mail-wr1-x443.google.com with SMTP id z9so2005071wrs.10 for ; Sat, 08 Feb 2020 04:58:22 -0800 (PST) Received: from localhost.localdomain ([82.3.55.76]) by smtp.gmail.com with ESMTPSA id p5sm7490534wrt.79.2020.02.08.04.58.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Feb 2020 04:58:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Xngl1cCVNWBf5Cw2CDK8Z2YQwTs9m5X5G+obWGPZ0QA=; b=LWk7/n+pQ2K9hZ6tRT6LiceM3s6pSMhAvCYxDFMThl1whClL/r76NN8WLMhL2iVhc9 0ACHrMdAj9QrNNldc2fwWnR6B6ozWr7/yWznfyjnpuv5EnGHoXP/4YJreiW06u7Dif9X vG5ya3O3SiUlyIlo3NxFhnEqPTtvh/6EhKoMzn8EV2Bb2jELNgfhCUYReP0OtVqVH2wP E9njuPVvrP8E4lvB+j1LUZ2jQ1kRtdWu95vcZLxZ/TBHiiSu81e1VbiqWpzu1YL8JL5a R78IAEchsbjYHBD1/KsPqyKe+xJ6MeYK2Wnek9cGaQ8OKijVEOYr6k9MAryJW2qEpRB+ vztQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Xngl1cCVNWBf5Cw2CDK8Z2YQwTs9m5X5G+obWGPZ0QA=; b=VxqkYJw3UnxNKcNITemFv1j5aeanvcSrynB2LNBnJL2eyoF8Lx++frhrqueOIOO9IZ MVRG8mLOIkwOhDlrV9N5O+T/56QBnm/E7opEAzPAGKCbEFaFCA28AmDkRaGgih7PMbRh wPtbSvvZIvq82hIv2mSsNfQ9xd7k9IHN+pwSIQFUkaJsnTDC5UOgnVdJfuGfeAzn6Feq SWDYUuJSSWCjPdJs5TLf2F/nHeplWBea0sH8EFYZpQtE9++8L+r+n5ds/pN+NMilsl3D LxObe2jEW17Vr0bKkU+zPiFBxWsEmVLrY3dy5bsZj2EwnCXcCQNPmSRLfsdxZHy8b2Ic OMEQ== X-Gm-Message-State: APjAAAVZk/gmKFHeDuka9uIXaIcfEsHhFxKwOjHjN43phcUlqAkhVetT hJShjyenbHM0rdaaK4AxVKW6BF8aIblaXw== X-Google-Smtp-Source: APXvYqxH+4Fl2E4r0Ui/u+sEBiyCOfEnuHWOOhBzBuSYNk0Fb9sqpYh64Re/fnD1FawttHKf+R8KKw== X-Received: by 2002:a5d:6ac4:: with SMTP id u4mr5299408wrw.318.1581166701812; Sat, 08 Feb 2020 04:58:21 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 04/20] target/arm: Move LOR regdefs to file scope Date: Sat, 8 Feb 2020 12:58:00 +0000 Message-Id: <20200208125816.14954-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200208125816.14954-1-richard.henderson@linaro.org> References: <20200208125816.14954-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) For static const regdefs, file scope is preferred. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- target/arm/helper.c | 57 +++++++++++++++++++++++---------------------- 1 file changed, 29 insertions(+), 28 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index bfd6c0d04b..e4f17c7e83 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6334,6 +6334,35 @@ static CPAccessResult access_lor_other(CPUARMState *= env, return access_lor_ns(env); } =20 +/* + * A trivial implementation of ARMv8.1-LOR leaves all of these + * registers fixed at 0, which indicates that there are zero + * supported Limited Ordering regions. + */ +static const ARMCPRegInfo lor_reginfo[] =3D { + { .name =3D "LORSA_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D 0, + .access =3D PL1_RW, .accessfn =3D access_lor_other, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "LOREA_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D 1, + .access =3D PL1_RW, .accessfn =3D access_lor_other, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "LORN_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D 2, + .access =3D PL1_RW, .accessfn =3D access_lor_other, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "LORC_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D 3, + .access =3D PL1_RW, .accessfn =3D access_lor_other, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "LORID_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D 7, + .access =3D PL1_R, .accessfn =3D access_lorid, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + REGINFO_SENTINEL +}; + #ifdef TARGET_AARCH64 static CPAccessResult access_pauth(CPUARMState *env, const ARMCPRegInfo *r= i, bool isread) @@ -7568,34 +7597,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) } =20 if (cpu_isar_feature(aa64_lor, cpu)) { - /* - * A trivial implementation of ARMv8.1-LOR leaves all of these - * registers fixed at 0, which indicates that there are zero - * supported Limited Ordering regions. - */ - static const ARMCPRegInfo lor_reginfo[] =3D { - { .name =3D "LORSA_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D= 0, - .access =3D PL1_RW, .accessfn =3D access_lor_other, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "LOREA_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D= 1, - .access =3D PL1_RW, .accessfn =3D access_lor_other, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "LORN_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D= 2, - .access =3D PL1_RW, .accessfn =3D access_lor_other, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "LORC_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D= 3, - .access =3D PL1_RW, .accessfn =3D access_lor_other, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "LORID_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D= 7, - .access =3D PL1_R, .accessfn =3D access_lorid, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - REGINFO_SENTINEL - }; define_arm_cp_regs(cpu, lor_reginfo); } =20 --=20 2.20.1