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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id w1sm3796430wro.72.2020.02.07.06.33.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Feb 2020 06:33:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Y+KiwaqP4h5aFTrX/BwPPQnHy8uVGnBT/5tjq3JwMVI=; b=cqAEpcOzTLBo7+3+0LKDz5E+NQFNTTf6iBu8Na2s3pCqqFV9AhIOb92ypDoUKAVsJA uXDP+qDEDWWxAtUtFx5+uXX/Nc86U94JZRP7sn1apzOETkXO/dlKgZDDu09aMW0WXrp4 AZn3aP0ICVt8yv/SykC37bCAnIU7dtQIXcYQBk/3KIkKtCxmdl03cKk4bc1YJbwNqBmh YBKhMubG0cQhEZcFyObCJG8p4wihA5AV4EnOjULoDg2mEImlGp0C0dpe8U/1dN6A5kro snbaXSpZJnMK/L3DgxUsyNfD9DpPo+6llfPo+Tbbhs8HY0Jq9IpNcHsIWccz/hmjI6aA UC6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Y+KiwaqP4h5aFTrX/BwPPQnHy8uVGnBT/5tjq3JwMVI=; b=MyYPsTMCzeRkXiFdFiBSS7pBra76o3BHEyB+WI0MJlmHEnJEZSA5t8gC+yqu2vbjok lkrJq84i5Osrz+hrg5IRcpAyEDNPjIqo0+S5HPcYp1PfRJVcrHXuZvaSfMWe9F82qcJ+ 97YtRU/KTxkeNy7A68S3lFaFWxz73RWEoVW9kNYsyXxH146Awi/BZpUdFMF1Z2Uf7Op9 /K+wfBQvcwCQn5cTo9RkEN4gALdHO5qtF4OblIQx9vSEHzxjGfbs6kuaEGKiDRtnw3GO 2JmVx4PzjGYHY/cz6hRKpYBd5IcaOsSpPUAlQwh7Df1UO56CLgqWLzRiIm4q0rMcgxKc DVyg== X-Gm-Message-State: APjAAAUfcU0cDupnm2jtmkRyvVoSkH+u1hGvSQ4ViyoEEJ2TuWiEDobg nQXhRXVV4dV49Lz3KjHbUHoSXGSdxJk= X-Google-Smtp-Source: APXvYqy6h/iaNDF4IthDH1xj2GRQhvrPyesE7rkxHciahr2asQznEek5LswoTF9zbtV7bmhXqlcw/A== X-Received: by 2002:a1c:9c87:: with SMTP id f129mr4911110wme.26.1581086033923; Fri, 07 Feb 2020 06:33:53 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/48] target/arm: Split out alle1_tlbmask Date: Fri, 7 Feb 2020 14:33:03 +0000 Message-Id: <20200207143343.30322-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200207143343.30322-1-peter.maydell@linaro.org> References: <20200207143343.30322-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32a X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Richard Henderson No functional change, but unify code sequences. Tested-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Message-id: 20200206105448.4726-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 86 +++++++++++++-------------------------------- 1 file changed, 24 insertions(+), 62 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 8b3bb51dee2..49da685b296 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3972,34 +3972,31 @@ static void tlbi_aa64_vmalle1_write(CPUARMState *en= v, const ARMCPRegInfo *ri, tlb_flush_by_mmuidx(cs, mask); } =20 -static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) +static int alle1_tlbmask(CPUARMState *env) { - /* Note that the 'ALL' scope must invalidate both stage 1 and + /* + * Note that the 'ALL' scope must invalidate both stage 1 and * stage 2 translations, whereas most other scopes only invalidate * stage 1 translations. */ - ARMCPU *cpu =3D env_archcpu(env); - CPUState *cs =3D CPU(cpu); - if (arm_is_secure_below_el3(env)) { - tlb_flush_by_mmuidx(cs, - ARMMMUIdxBit_S1SE1 | - ARMMMUIdxBit_S1SE0); + return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0; + } else if (arm_feature(env, ARM_FEATURE_EL2)) { + return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0 | ARMMMUIdxBit_= S2NS; } else { - if (arm_feature(env, ARM_FEATURE_EL2)) { - tlb_flush_by_mmuidx(cs, - ARMMMUIdxBit_S12NSE1 | - ARMMMUIdxBit_S12NSE0 | - ARMMMUIdxBit_S2NS); - } else { - tlb_flush_by_mmuidx(cs, - ARMMMUIdxBit_S12NSE1 | - ARMMMUIdxBit_S12NSE0); - } + return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0; } } =20 +static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + CPUState *cs =3D env_cpu(env); + int mask =3D alle1_tlbmask(env); + + tlb_flush_by_mmuidx(cs, mask); +} + static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -4021,28 +4018,10 @@ static void tlbi_aa64_alle3_write(CPUARMState *env,= const ARMCPRegInfo *ri, static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *= ri, uint64_t value) { - /* Note that the 'ALL' scope must invalidate both stage 1 and - * stage 2 translations, whereas most other scopes only invalidate - * stage 1 translations. - */ CPUState *cs =3D env_cpu(env); - bool sec =3D arm_is_secure_below_el3(env); - bool has_el2 =3D arm_feature(env, ARM_FEATURE_EL2); + int mask =3D alle1_tlbmask(env); =20 - if (sec) { - tlb_flush_by_mmuidx_all_cpus_synced(cs, - ARMMMUIdxBit_S1SE1 | - ARMMMUIdxBit_S1SE0); - } else if (has_el2) { - tlb_flush_by_mmuidx_all_cpus_synced(cs, - ARMMMUIdxBit_S12NSE1 | - ARMMMUIdxBit_S12NSE0 | - ARMMMUIdxBit_S2NS); - } else { - tlb_flush_by_mmuidx_all_cpus_synced(cs, - ARMMMUIdxBit_S12NSE1 | - ARMMMUIdxBit_S12NSE0); - } + tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); } =20 static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *= ri, @@ -4092,20 +4071,11 @@ static void tlbi_aa64_vae3_write(CPUARMState *env, = const ARMCPRegInfo *ri, static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *r= i, uint64_t value) { - ARMCPU *cpu =3D env_archcpu(env); - CPUState *cs =3D CPU(cpu); - bool sec =3D arm_is_secure_below_el3(env); + CPUState *cs =3D env_cpu(env); + int mask =3D vae1_tlbmask(env); uint64_t pageaddr =3D sextract64(value << 12, 0, 56); =20 - if (sec) { - tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, - ARMMMUIdxBit_S1SE1 | - ARMMMUIdxBit_S1SE0); - } else { - tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, - ARMMMUIdxBit_S12NSE1 | - ARMMMUIdxBit_S12NSE0); - } + tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, mask); } =20 static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -4116,8 +4086,8 @@ static void tlbi_aa64_vae1_write(CPUARMState *env, co= nst ARMCPRegInfo *ri, * since we don't support flush-for-specific-ASID-only or * flush-last-level-only. */ - ARMCPU *cpu =3D env_archcpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); + int mask =3D vae1_tlbmask(env); uint64_t pageaddr =3D sextract64(value << 12, 0, 56); =20 if (tlb_force_broadcast(env)) { @@ -4125,15 +4095,7 @@ static void tlbi_aa64_vae1_write(CPUARMState *env, c= onst ARMCPRegInfo *ri, return; } =20 - if (arm_is_secure_below_el3(env)) { - tlb_flush_page_by_mmuidx(cs, pageaddr, - ARMMMUIdxBit_S1SE1 | - ARMMMUIdxBit_S1SE0); - } else { - tlb_flush_page_by_mmuidx(cs, pageaddr, - ARMMMUIdxBit_S12NSE1 | - ARMMMUIdxBit_S12NSE0); - } + tlb_flush_page_by_mmuidx(cs, pageaddr, mask); } =20 static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *r= i, --=20 2.20.1