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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id w1sm3796430wro.72.2020.02.07.06.34.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Feb 2020 06:34:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=1LTG4U/f+N60k+wJCqnLvXrcq4ScJA4RfGQ/AElRkTQ=; b=JqqrjjgK6O+mbuYyngaA1pKoC9OSKx0bLaZ7oUPUtqn1vJ0pOXLvXDPPuBCpM234le 3lMeUg41xC+wZhq1yF8pefRihJLEn69ZY4CsYCiVVfmfzA+Hxu5353hvB79DKd9F46im 2k3pnhSoWXQbDgW8+jYg9qMC5GgCdydIuIoqJ2MBAgHj0Jnzuhvc5aPicgaHwetcJKF1 78/MxhBexWlL7T65AO3YZxIA9EOzUi8XMPNd/dcWU1Ac2fjMSFZLhkT014W4F5rGLDJN WBEY0ECQZUYehGrbbOp2tpSlQKOttA/2HeJB4Q3Ha2q/lz2VOgF6pHKrguGaZqD7/n+/ zaVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1LTG4U/f+N60k+wJCqnLvXrcq4ScJA4RfGQ/AElRkTQ=; b=M+OlFUXBU9tjLRcyP06Ygkf8qbBY7FCd/UDFsACXpYG8ce08EpxzmtxGK/30Ojdj7F ALI6ojHBM2+yiKpkRMd3zEncNz2o8nhYczjb14FfCkCdPErz7AEDQigYMt+VGF1Re//K zTRlAFvivWl1rO/zGpRxmcsVpqOaF6g8ahYp2A++D4ZzLxSvGyhltQXoFQ4ee9NwWiXC Nai0+bYuIDfsr9rVOmWbeg77go45V+kMnV2Q2UlLLyHUeuffvHSpRBAa3iGDVHqDt/T4 LrV6rVe9p0/ZSasXjTlUtEp7S44AZycPb+OWD/L07BTP8gJitGaTdZjWz5oPFR4i2t4z Ab2A== X-Gm-Message-State: APjAAAVAwzBY+i+7ouLar6sL+d5sDhqGrSPbpJvbnslE0XSlCObKC0Dq QMcj/V9QFG41tJKoGuUewCsUbgGdleA= X-Google-Smtp-Source: APXvYqxcL7W2DokFq6yhc2FgHLLQEokgfg1neXm3g1DPKuYtbz6kgWHsUpJsH4cF7N7CIY4OBVW8Tw== X-Received: by 2002:a1c:67c3:: with SMTP id b186mr4648893wmc.36.1581086068624; Fri, 07 Feb 2020 06:34:28 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 40/48] target/arm: Pass more cpu state to arm_excp_unmasked Date: Fri, 7 Feb 2020 14:33:35 +0000 Message-Id: <20200207143343.30322-41-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200207143343.30322-1-peter.maydell@linaro.org> References: <20200207143343.30322-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Richard Henderson Avoid redundant computation of cpu state by passing it in from the caller, which has already computed it for itself. Tested-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Message-id: 20200206105448.4726-40-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index b81ed44bd2b..fcee0a2dd45 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -411,14 +411,13 @@ static void arm_cpu_reset(CPUState *s) } =20 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, - unsigned int target_el) + unsigned int target_el, + unsigned int cur_el, bool secure, + uint64_t hcr_el2) { CPUARMState *env =3D cs->env_ptr; - unsigned int cur_el =3D arm_current_el(env); - bool secure =3D arm_is_secure(env); bool pstate_unmasked; int8_t unmasked =3D 0; - uint64_t hcr_el2; =20 /* * Don't take exceptions if they target a lower EL. @@ -429,8 +428,6 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsi= gned int excp_idx, return false; } =20 - hcr_el2 =3D arm_hcr_el2_eff(env); - switch (excp_idx) { case EXCP_FIQ: pstate_unmasked =3D !(env->daif & PSTATE_F); @@ -535,6 +532,7 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt= _request) CPUARMState *env =3D cs->env_ptr; uint32_t cur_el =3D arm_current_el(env); bool secure =3D arm_is_secure(env); + uint64_t hcr_el2 =3D arm_hcr_el2_eff(env); uint32_t target_el; uint32_t excp_idx; bool ret =3D false; @@ -542,7 +540,8 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt= _request) if (interrupt_request & CPU_INTERRUPT_FIQ) { excp_idx =3D EXCP_FIQ; target_el =3D arm_phys_excp_target_el(cs, excp_idx, cur_el, secure= ); - if (arm_excp_unmasked(cs, excp_idx, target_el)) { + if (arm_excp_unmasked(cs, excp_idx, target_el, + cur_el, secure, hcr_el2)) { cs->exception_index =3D excp_idx; env->exception.target_el =3D target_el; cc->do_interrupt(cs); @@ -552,7 +551,8 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt= _request) if (interrupt_request & CPU_INTERRUPT_HARD) { excp_idx =3D EXCP_IRQ; target_el =3D arm_phys_excp_target_el(cs, excp_idx, cur_el, secure= ); - if (arm_excp_unmasked(cs, excp_idx, target_el)) { + if (arm_excp_unmasked(cs, excp_idx, target_el, + cur_el, secure, hcr_el2)) { cs->exception_index =3D excp_idx; env->exception.target_el =3D target_el; cc->do_interrupt(cs); @@ -562,7 +562,8 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt= _request) if (interrupt_request & CPU_INTERRUPT_VIRQ) { excp_idx =3D EXCP_VIRQ; target_el =3D 1; - if (arm_excp_unmasked(cs, excp_idx, target_el)) { + if (arm_excp_unmasked(cs, excp_idx, target_el, + cur_el, secure, hcr_el2)) { cs->exception_index =3D excp_idx; env->exception.target_el =3D target_el; cc->do_interrupt(cs); @@ -572,7 +573,8 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt= _request) if (interrupt_request & CPU_INTERRUPT_VFIQ) { excp_idx =3D EXCP_VFIQ; target_el =3D 1; - if (arm_excp_unmasked(cs, excp_idx, target_el)) { + if (arm_excp_unmasked(cs, excp_idx, target_el, + cur_el, secure, hcr_el2)) { cs->exception_index =3D excp_idx; env->exception.target_el =3D target_el; cc->do_interrupt(cs); --=20 2.20.1