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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id w1sm3796430wro.72.2020.02.07.06.34.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Feb 2020 06:34:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=JjYyP7RWWnHPNkNaWrncpCUhNmdtAYWQtIovOWWFnzk=; b=vE0L+7KXg1lgbQwTwVlLANSjTU/jfHWp6QlKWTrZztPDlZbJ84yEpp7Y32o7v6RD75 xyMdqmoDTq8nO9dmqboVV9mViQ2VrMJbFKFJxuXGiQFvR4d2q4dCRIeLu2+FrVEY+tTq oCVSrWYQ1JXC2aYr4rGNSBM2vvxfnzr2qFNOgyRkv0XrFbNlrqY5nfR/S5va8iul1CUP f/JziBTqou48CKDld3b2Ea1gT9ugT4IWk3X3Af2b+LXmj4kzWPVgvByEKbNIKZImlNGE fvBLk5QNDJrp6I7om/TX1Pdx3R7CJCYGmyMFZji6ISjOUq61qAKCZ68WVyqOEzZxbmjD hcew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JjYyP7RWWnHPNkNaWrncpCUhNmdtAYWQtIovOWWFnzk=; b=tmaJglFsK8Oh9br2au3cX9Gm00hHfHvK1xUcqzqRWomb0WRoLCjV/uybatZtw6hhX5 IY9tMxtZ5PwuOGGPDPN6Fo9NcRF9JTY65j+ZJ61m3fs4s81elA2dWw6kxWf9ip5Uf0zc qIjATe4uOx+1sGjdDeZmS0RK3I6mqopzo99b1IQ7yDMHUT9plv4EPKOxaOaaKEHcTXc9 8j0CQF+J8NM194xo+YjYGwKjHrUFsO9MpPfmAgE7/HHef7LJOyoLi0W47Q6ajoqB1glC f0O56hyYbCT1G0T+ew+2NbMDk6LaY/xf1VDb9hyQ8VH2hQOa/hG41VsIwILKsjlaB7YN YXQw== X-Gm-Message-State: APjAAAVFmZQDuIVSMCU2Vr9k5YeKG5OIQFS3YD6lomHRMu6KWAqLuqSy yF1QHe+l0nBq53xySRMQSQCnjOb3ieM= X-Google-Smtp-Source: APXvYqzuisfBBFBru0YEDnTAVIkpcRnt+HlsvzekiP1xQMnQpGVh9GVJ4h22w/YP/Lee0PX0+IW9Hg== X-Received: by 2002:a05:600c:2254:: with SMTP id a20mr4526216wmm.97.1581086063982; Fri, 07 Feb 2020 06:34:23 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 36/48] target/arm: Update get_a64_user_mem_index for VHE Date: Fri, 7 Feb 2020 14:33:31 +0000 Message-Id: <20200207143343.30322-37-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200207143343.30322-1-peter.maydell@linaro.org> References: <20200207143343.30322-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Richard Henderson The EL2&0 translation regime is affected by Load Register (unpriv). The code structure used here will facilitate later changes in this area for implementing UAO and NV. Tested-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200206105448.4726-36-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 9 ++++---- target/arm/translate.h | 2 ++ target/arm/helper.c | 22 +++++++++++++++++++ target/arm/translate-a64.c | 44 ++++++++++++++++++++++++-------------- 4 files changed, 57 insertions(+), 20 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d091a7e2e87..2ed2667a170 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3214,10 +3214,10 @@ typedef ARMCPU ArchCPU; * | | | TBFLAG_A32 | | * | | +-----+----------+ TBFLAG_AM32 | * | TBFLAG_ANY | |TBFLAG_M32| | - * | | +-------------------------| - * | | | TBFLAG_A64 | - * +--------------+-----------+-------------------------+ - * 31 20 14 0 + * | | +-+----------+--------------| + * | | | TBFLAG_A64 | + * +--------------+---------+---------------------------+ + * 31 20 15 0 * * Unless otherwise noted, these bits are cached in env->hflags. */ @@ -3283,6 +3283,7 @@ FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) FIELD(TBFLAG_A64, BT, 9, 1) FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ FIELD(TBFLAG_A64, TBID, 12, 2) +FIELD(TBFLAG_A64, UNPRIV, 14, 1) =20 static inline bool bswap_code(bool sctlr_b) { diff --git a/target/arm/translate.h b/target/arm/translate.h index a32b6b1b3a9..5b167c416a2 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -73,6 +73,8 @@ typedef struct DisasContext { * ie A64 LDX*, LDAX*, A32/T32 LDREX*, LDAEX*. */ bool is_ldex; + /* True if AccType_UNPRIV should be used for LDTR et al */ + bool unpriv; /* True if v8.3-PAuth is active. */ bool pauth_active; /* True with v8.5-BTI and SCTLR_ELx.BT* set. */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 9627b4aab15..ff2d957b7c6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12011,6 +12011,28 @@ static uint32_t rebuild_hflags_a64(CPUARMState *en= v, int el, int fp_el, } } =20 + /* Compute the condition for using AccType_UNPRIV for LDTR et al. */ + /* TODO: ARMv8.2-UAO */ + switch (mmu_idx) { + case ARMMMUIdx_E10_1: + case ARMMMUIdx_SE10_1: + /* TODO: ARMv8.3-NV */ + flags =3D FIELD_DP32(flags, TBFLAG_A64, UNPRIV, 1); + break; + case ARMMMUIdx_E20_2: + /* TODO: ARMv8.4-SecEL2 */ + /* + * Note that E20_2 is gated by HCR_EL2.E2H =3D=3D 1, but E20_0 is + * gated by HCR_EL2. =3D=3D '11', and so is LDTR. + */ + if (env->cp15.hcr_el2 & HCR_TGE) { + flags =3D FIELD_DP32(flags, TBFLAG_A64, UNPRIV, 1); + } + break; + default: + break; + } + return rebuild_hflags_common(env, fp_el, mmu_idx, flags); } =20 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 3982e1988dc..6e82486884b 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -105,25 +105,36 @@ void a64_translate_init(void) offsetof(CPUARMState, exclusive_high), "exclusive_high"); } =20 -static inline int get_a64_user_mem_index(DisasContext *s) +/* + * Return the core mmu_idx to use for A64 "unprivileged load/store" insns + */ +static int get_a64_user_mem_index(DisasContext *s) { - /* Return the core mmu_idx to use for A64 "unprivileged load/store" in= sns: - * if EL1, access as if EL0; otherwise access at current EL + /* + * If AccType_UNPRIV is not used, the insn uses AccType_NORMAL, + * which is the usual mmu_idx for this cpu state. */ - ARMMMUIdx useridx; + ARMMMUIdx useridx =3D s->mmu_idx; =20 - switch (s->mmu_idx) { - case ARMMMUIdx_E10_1: - useridx =3D ARMMMUIdx_E10_0; - break; - case ARMMMUIdx_SE10_1: - useridx =3D ARMMMUIdx_SE10_0; - break; - case ARMMMUIdx_Stage2: - g_assert_not_reached(); - default: - useridx =3D s->mmu_idx; - break; + if (s->unpriv) { + /* + * We have pre-computed the condition for AccType_UNPRIV. + * Therefore we should never get here with a mmu_idx for + * which we do not know the corresponding user mmu_idx. + */ + switch (useridx) { + case ARMMMUIdx_E10_1: + useridx =3D ARMMMUIdx_E10_0; + break; + case ARMMMUIdx_E20_2: + useridx =3D ARMMMUIdx_E20_0; + break; + case ARMMMUIdx_SE10_1: + useridx =3D ARMMMUIdx_SE10_0; + break; + default: + g_assert_not_reached(); + } } return arm_to_core_mmu_idx(useridx); } @@ -14171,6 +14182,7 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, dc->pauth_active =3D FIELD_EX32(tb_flags, TBFLAG_A64, PAUTH_ACTIVE); dc->bt =3D FIELD_EX32(tb_flags, TBFLAG_A64, BT); dc->btype =3D FIELD_EX32(tb_flags, TBFLAG_A64, BTYPE); + dc->unpriv =3D FIELD_EX32(tb_flags, TBFLAG_A64, UNPRIV); dc->vec_len =3D 0; dc->vec_stride =3D 0; dc->cp_regs =3D arm_cpu->cp_regs; --=20 2.20.1