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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id w1sm3796430wro.72.2020.02.07.06.34.21 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Feb 2020 06:34:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=uvVs7AbJlQzoOOjIZQudyT2Qfx8L7K31YrCEz2YjTWE=; b=fRc0qw3Mluk1edQfA543Uri3Q96sXB19Q8GY4ZaGZvUy7ZYWNC+Iw+XHKnuT+mydfA Shd4RzsbjtC5+bYatX2uHn9SaFuTNYu719K4AVD1JzfCcbiYL24NXaXf5nE6xqIlP7p+ aTa7V6SG2yL67oW9vDMbAghzOqD1vxYpC2b8kSb3figRohrGDWUhtfkPI5XCaVp3lznD We1cqs/ar06vdgIcKi8GUxlYcgfIQwnKY4L+eUrcJh+wvjYVv7eM9kLli9SN75GKghf6 kQtZDlZrv8eSTnu1tNa6HZNjQn/YYM073EdXOv6vqJwQhO9n6n0X77e88vyHu/sIa0nw nTaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uvVs7AbJlQzoOOjIZQudyT2Qfx8L7K31YrCEz2YjTWE=; b=qyQgBn3eR1Q9Ue3mDiecyLnAlnJA+7IWg5wqX1/yAm1oKSjwdRYJ3uH6Jti059Ctvb TVToWL2emTc8dC7IqayvhL32qvpHM70tibhOU3mlEVzUj35yH5qsu/DNJJO10VaLI+yk ycBgSIoHA1AvNBNoldIYjFvyauDk9eMp9L0zDewTVxcbDd1cMT6kSDVQdA3gOqyo/Vbh Yh+EEhSr1vzHuno5odBl+1TIQCsik0wnAv5Z4owc3inru4WxmjKqfGOUaLQ25WGNFSR/ IcW/gPjmAu3S/i/LhDQbHisiyxq4QM/BChLurQ+YpvpLfDc/NKAiPsFh6D82RaE1XQFs wCug== X-Gm-Message-State: APjAAAWFCf23Xv1w8W0XJRCp9s/isfcKIA289YiFyuTms2n47q+uD+9m CcF1pMt0VyRQQFSi9oJq07OBc/tOfYg= X-Google-Smtp-Source: APXvYqxl5rEAzv8X+ZE7pcZ26a0LuPebCQEd7u1N2Z4MBECmWarLvhzB4qOv/kgJ6eef5tbd591O9g== X-Received: by 2002:a5d:484f:: with SMTP id n15mr4992000wrs.365.1581086062113; Fri, 07 Feb 2020 06:34:22 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 34/48] target/arm: Update {fp,sve}_exception_el for VHE Date: Fri, 7 Feb 2020 14:33:29 +0000 Message-Id: <20200207143343.30322-35-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200207143343.30322-1-peter.maydell@linaro.org> References: <20200207143343.30322-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Richard Henderson When TGE+E2H are both set, CPACR_EL1 is ignored. Tested-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200206105448.4726-34-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 53 ++++++++++++++++++++++++--------------------- 1 file changed, 28 insertions(+), 25 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 56a62b11d09..9627b4aab15 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5791,7 +5791,9 @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] =3D= { int sve_exception_el(CPUARMState *env, int el) { #ifndef CONFIG_USER_ONLY - if (el <=3D 1) { + uint64_t hcr_el2 =3D arm_hcr_el2_eff(env); + + if (el <=3D 1 && (hcr_el2 & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HCR_T= GE)) { bool disabled =3D false; =20 /* The CPACR.ZEN controls traps to EL1: @@ -5806,8 +5808,7 @@ int sve_exception_el(CPUARMState *env, int el) } if (disabled) { /* route_to_el2 */ - return (arm_feature(env, ARM_FEATURE_EL2) - && (arm_hcr_el2_eff(env) & HCR_TGE) ? 2 : 1); + return hcr_el2 & HCR_TGE ? 2 : 1; } =20 /* Check CPACR.FPEN. */ @@ -11691,8 +11692,6 @@ uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val,= uint32_t bytes) int fp_exception_el(CPUARMState *env, int cur_el) { #ifndef CONFIG_USER_ONLY - int fpen; - /* CPACR and the CPTR registers don't exist before v6, so FP is * always accessible */ @@ -11720,30 +11719,34 @@ int fp_exception_el(CPUARMState *env, int cur_el) * 0, 2 : trap EL0 and EL1/PL1 accesses * 1 : trap only EL0 accesses * 3 : trap no accesses + * This register is ignored if E2H+TGE are both set. */ - fpen =3D extract32(env->cp15.cpacr_el1, 20, 2); - switch (fpen) { - case 0: - case 2: - if (cur_el =3D=3D 0 || cur_el =3D=3D 1) { - /* Trap to PL1, which might be EL1 or EL3 */ - if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { + if ((arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HCR_T= GE)) { + int fpen =3D extract32(env->cp15.cpacr_el1, 20, 2); + + switch (fpen) { + case 0: + case 2: + if (cur_el =3D=3D 0 || cur_el =3D=3D 1) { + /* Trap to PL1, which might be EL1 or EL3 */ + if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { + return 3; + } + return 1; + } + if (cur_el =3D=3D 3 && !is_a64(env)) { + /* Secure PL1 running at EL3 */ return 3; } - return 1; + break; + case 1: + if (cur_el =3D=3D 0) { + return 1; + } + break; + case 3: + break; } - if (cur_el =3D=3D 3 && !is_a64(env)) { - /* Secure PL1 running at EL3 */ - return 3; - } - break; - case 1: - if (cur_el =3D=3D 0) { - return 1; - } - break; - case 3: - break; } =20 /* --=20 2.20.1