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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id w1sm3796430wro.72.2020.02.07.06.34.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Feb 2020 06:34:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=JMPFk0I8G2lk98QhY9xW2fm5UIcVqoFjQ1BM8KPf/ic=; b=rjG7KeRoWjtvIsqJO1AHpjQBk2qcL+oiwqjEIS6S/lxr5oJm1Dvl2P1eTw00B2G4vK I1OYDU4BtofCUYGxO1N5nzrS7sSjOSSQnbfNkOsqGy0w0N4T25hNLagdRzhJAErbKYlJ zEtnhERRDk2c/SNjKKAM+LK4Qlob8IzXruO/Dpa5JSAoogVbmVVaRcbAvTzQ0q7LRmeX IoY0T+VhCcVC581C3bFzX62MJJGvEOWFDzjAM+WLvjIcGIs2guTEiQABX6OTj4oNZDST eY85Sw2own4qjPpUu1tpEFp+z5hWR3iJ0btJS05I3eJgSaY+DEMhAR2KnoZFNmG8/8pd u+LQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JMPFk0I8G2lk98QhY9xW2fm5UIcVqoFjQ1BM8KPf/ic=; b=k09tUufNCIFNETn4TaQyHZUDyL05QiFPR1ADBItBtTjoJA4xERL6jKTwggFFeojPFt IwP/5oEyuUexDdCGzOqDTnPf/qtsIKGxru70npSWSSl0DjIJCRHf06LRf6WXiXmzz+iL +VRQ/SUVIzlT/9ZkgWFbS9lnmd0ewGrNPpwES9eHg+D58ISbagAiuSU3Ni51udBQA3Vv NOSGQdN4wpJocNzcNf84FA41oSlHB0JiSUH3JTGpwKRmF9K7Bpas4XYiWW9thXEEAVN1 kp9Vg/jSBRzQynUA/ivKZF0g6TC+U58jI871SjJ1zOm0rnrzKmmsB8sOboVRiqpZiwER 2/2Q== X-Gm-Message-State: APjAAAWhTxFcMtUGApWSb2J+lU4ctR7SW8IWRq2hHrr82uktw7DO6ue4 SnQi43lYn3eNlKafYJN8qJpW5xOpnZA= X-Google-Smtp-Source: APXvYqxFo5AkpVuIpqsqAb0MAOzvZfHisZqDe3zPbQVZLE9OmUWs14ZkVdVAU6LUfW2eF92lLLSkrw== X-Received: by 2002:a7b:c0da:: with SMTP id s26mr4651088wmh.52.1581086059078; Fri, 07 Feb 2020 06:34:19 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 31/48] target/arm: Flush tlb for ASID changes in EL2&0 translation regime Date: Fri, 7 Feb 2020 14:33:26 +0000 Message-Id: <20200207143343.30322-32-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200207143343.30322-1-peter.maydell@linaro.org> References: <20200207143343.30322-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Richard Henderson Since we only support a single ASID, flush the tlb when it changes. Note that TCR_EL2, like TCR_EL1, has the A1 bit that chooses between the two TTBR* registers for the location of the ASID. Tested-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200206105448.4726-31-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index cfa6ce59dc8..f9be6b052f0 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3763,7 +3763,7 @@ static void vmsa_ttbcr_reset(CPUARMState *env, const = ARMCPRegInfo *ri) tcr->base_mask =3D 0xffffc000u; } =20 -static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, +static void vmsa_tcr_el12_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { ARMCPU *cpu =3D env_archcpu(env); @@ -3789,7 +3789,17 @@ static void vmsa_ttbr_write(CPUARMState *env, const = ARMCPRegInfo *ri, static void vmsa_tcr_ttbr_el2_write(CPUARMState *env, const ARMCPRegInfo *= ri, uint64_t value) { - /* TODO: There are ASID fields in here with HCR_EL2.E2H */ + /* + * If we are running with E2&0 regime, then an ASID is active. + * Flush if that might be changing. Note we're not checking + * TCR_EL2.A1 to know if this is really the TTBRx_EL2 that + * holds the active ASID, only checking the field that might. + */ + if (extract64(raw_read(env, ri) ^ value, 48, 16) && + (arm_hcr_el2_eff(env) & HCR_E2H)) { + tlb_flush_by_mmuidx(env_cpu(env), + ARMMMUIdxBit_E20_2 | ARMMMUIdxBit_E20_0); + } raw_write(env, ri, value); } =20 @@ -3849,7 +3859,7 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] =3D { offsetof(CPUARMState, cp15.ttbr1_ns) } }, { .name =3D "TCR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .crn =3D 2, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 2, - .access =3D PL1_RW, .writefn =3D vmsa_tcr_el1_write, + .access =3D PL1_RW, .writefn =3D vmsa_tcr_el12_write, .resetfn =3D vmsa_ttbcr_reset, .raw_writefn =3D raw_write, .fieldoffset =3D offsetof(CPUARMState, cp15.tcr_el[1]) }, { .name =3D "TTBCR", .cp =3D 15, .crn =3D 2, .crm =3D 0, .opc1 =3D 0, = .opc2 =3D 2, @@ -5175,10 +5185,8 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { .resetvalue =3D 0 }, { .name =3D "TCR_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 2, - .access =3D PL2_RW, - /* no .writefn needed as this can't cause an ASID change; - * no .raw_writefn or .resetfn needed as we never use mask/base_mask - */ + .access =3D PL2_RW, .writefn =3D vmsa_tcr_el12_write, + /* no .raw_writefn or .resetfn needed as we never use mask/base_mask= */ .fieldoffset =3D offsetof(CPUARMState, cp15.tcr_el[2]) }, { .name =3D "VTCR", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 4, .crn =3D 2, .crm =3D 1, .opc2 =3D 2, --=20 2.20.1