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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id w1sm3796430wro.72.2020.02.07.06.34.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Feb 2020 06:34:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=+7+Ixs7QmaR6uOEHjOzoEs2YwYAR1dd5H/bLNl8eCSk=; b=eOM3OIX+2bDB14hbGycd7e19LhWEAv/vtAOkh8m52imwV7P9sCglkaJ9T0IYjoE/Vi 1hydJkTh04HRNFlv72fAkCYjEag97F0ezDVTfIGsPFY4HOc3l+uSy25xmbhm1ESyoFoi 7xv+fCN9r+k6wlj1XKz9JcB2vT4qzrTgYpLsDyrKqpbjomD5Eg90xhL/endcdgJ+FYqj Bff+kEPQ32dqb1h43PNURIrWYsMDmJXBHxRmGjNFIXFoGsfIlE6aDohgCKMN3ucC/VBY Xtzf5IKfmfrbCbTLZwe3iV4NkwOX0woAY3Nbej9PNdaWCaMyv/DjYaA3aQjIf4l48zOI C+Ug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+7+Ixs7QmaR6uOEHjOzoEs2YwYAR1dd5H/bLNl8eCSk=; b=VRsfEfwBQkDKKOwXGvumSK9LXRX2CQh1Bm/wu2r+KKPC6aPAr4lPrOL0jYkxaluLOg tpXgOHPxGsq88qwoYzIpN4VeIHRvr1EntLcCidVt12B1UPxIPYHN5lFpKvGmxhnza56i HImC1wqwdIOKZXnhjxnOKgeHTg3a7xoi126OVAzWxdFmrxTQmNlHk69UZHTNALhWXWVW edvH1j+6oernlfp1hBU18WPaOeFgY2JiR1gCaRjbzzmly+XxDRaJ3uRjRxSMGs+ceX7j i7nPaHxstJ/EOIp/KxH95+KQM7gMNQ7H9RFqTJdlJW6KtSyogd4rJ2bjkul+IzgKoFDE jXfw== X-Gm-Message-State: APjAAAUWvr6qK7fkAG2lqDKpLgTCIks/1ywM6ZUEruPdzYovYecz/701 x5SrdvGFckzBEa0h7SmAo904dkG500U= X-Google-Smtp-Source: APXvYqy9xiNd31d7M8XxvtriiJO1j+ekFlZQPciQZu+R9bcC9fnnsjlW4b5gmHr7hlbEPTgqU5s9FQ== X-Received: by 2002:adf:e542:: with SMTP id z2mr5040847wrm.346.1581086044825; Fri, 07 Feb 2020 06:34:04 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/48] target/arm: Rearrange ARMMMUIdxBit Date: Fri, 7 Feb 2020 14:33:13 +0000 Message-Id: <20200207143343.30322-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200207143343.30322-1-peter.maydell@linaro.org> References: <20200207143343.30322-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Richard Henderson Define via macro expansion, so that renumbering of the base ARMMMUIdx symbols is automatically reflected in the bit definitions. Tested-by: Alex Benn=C3=A9e Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Message-id: 20200206105448.4726-18-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 39 +++++++++++++++++++++++---------------- 1 file changed, 23 insertions(+), 16 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index aa9728cff62..aa121cd9d0a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2927,27 +2927,34 @@ typedef enum ARMMMUIdx { ARMMMUIdx_Stage1_E1 =3D 1 | ARM_MMU_IDX_NOTLB, } ARMMMUIdx; =20 -/* Bit macros for the core-mmu-index values for each index, +/* + * Bit macros for the core-mmu-index values for each index, * for use when calling tlb_flush_by_mmuidx() and friends. */ +#define TO_CORE_BIT(NAME) \ + ARMMMUIdxBit_##NAME =3D 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_M= ASK) + typedef enum ARMMMUIdxBit { - ARMMMUIdxBit_E10_0 =3D 1 << 0, - ARMMMUIdxBit_E10_1 =3D 1 << 1, - ARMMMUIdxBit_E2 =3D 1 << 2, - ARMMMUIdxBit_SE3 =3D 1 << 3, - ARMMMUIdxBit_SE10_0 =3D 1 << 4, - ARMMMUIdxBit_SE10_1 =3D 1 << 5, - ARMMMUIdxBit_Stage2 =3D 1 << 6, - ARMMMUIdxBit_MUser =3D 1 << 0, - ARMMMUIdxBit_MPriv =3D 1 << 1, - ARMMMUIdxBit_MUserNegPri =3D 1 << 2, - ARMMMUIdxBit_MPrivNegPri =3D 1 << 3, - ARMMMUIdxBit_MSUser =3D 1 << 4, - ARMMMUIdxBit_MSPriv =3D 1 << 5, - ARMMMUIdxBit_MSUserNegPri =3D 1 << 6, - ARMMMUIdxBit_MSPrivNegPri =3D 1 << 7, + TO_CORE_BIT(E10_0), + TO_CORE_BIT(E10_1), + TO_CORE_BIT(E2), + TO_CORE_BIT(SE10_0), + TO_CORE_BIT(SE10_1), + TO_CORE_BIT(SE3), + TO_CORE_BIT(Stage2), + + TO_CORE_BIT(MUser), + TO_CORE_BIT(MPriv), + TO_CORE_BIT(MUserNegPri), + TO_CORE_BIT(MPrivNegPri), + TO_CORE_BIT(MSUser), + TO_CORE_BIT(MSPriv), + TO_CORE_BIT(MSUserNegPri), + TO_CORE_BIT(MSPrivNegPri), } ARMMMUIdxBit; =20 +#undef TO_CORE_BIT + #define MMU_USER_IDX 0 =20 static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx) --=20 2.20.1