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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id w1sm3796430wro.72.2020.02.07.06.34.03 for <qemu-devel@nongnu.org> (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Feb 2020 06:34:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=yxq4YxHd2MI+/+Xjtj2NcaZECHeURog87fN3pYPdVps=; b=LZjbkFE7uVmk/lfce4cMTzCHKdwhw9nYAys8p6AdQfNkDB3uw7my6IUyFE2k/FhL4t Z/Z1Hrn4Vt3pZmzEuFNpCaev0H1DGxp/Qv+avjWHnjlvKMECasbY/XdcG6Pr4MNW5+Da VcXeQNaeZGKC79IPw5/AqL2h6ykdjHYYOr46QCktp//v1mVXC43NwhgahCDz/Pg0f9nE KJUOiBR/PCOV0J/+ttiPgkGC8Wm749gi2PP9PvJszcZ2sBd7GvqX4qmGnVHt04brT/6A 1knjlyrh3xI5BAj0i2Z1PVWLNlsahif68D4fI9Wkc0NP1YK/g6wjgvfOcXjsLh0hph8W i+kg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yxq4YxHd2MI+/+Xjtj2NcaZECHeURog87fN3pYPdVps=; b=F6cOHx3aISkiopnzT4kqLiOPM7GUzkUa3kUOqg0ckKM+W9mHLCqqUpnE6ggUKyNwkU wW+UXHETF7DRDRx+y/Rdqg7OCdQRwQWGbHUvSgyn8EouZop6N1ukv/bJEXNHv+G+5x+t 2rhZFzl4zmzY+z9ljfGleVoFnTC7HCVVrNtam11f3IfqNPJC9ifrE1ETisEjKrytxYzP PtX1GGWRoQlSF7mOdLoK2W3UmcbWr+CxrtizTpFyxS6PIWyBHDKRbJZucL7eUedCnOip IN/+/W6WTc79JQ89MRn8z6ogpbEVnR7vQmW1KwNsgRXISBTmTUarQLGiqRq4t7Nhbocf +Z6w== X-Gm-Message-State: APjAAAWkq+odSj9iMYsUqibEu+gzIPfG8AURN5bHuBC0Nmbz8TZ/u1t+ gEru+tVuDm4uR/vQFC5aRmKSKzZDwNc= X-Google-Smtp-Source: APXvYqx1/h2NF/L4KAF9241u/Qzxfsq+2DpWePXCgiS23QsOsEtcw5M4Zm7gMy7PSrCYxwRBtf6p9g== X-Received: by 2002:a5d:6708:: with SMTP id o8mr5288263wru.296.1581086043994; Fri, 07 Feb 2020 06:34:03 -0800 (PST) From: Peter Maydell <peter.maydell@linaro.org> To: qemu-devel@nongnu.org Subject: [PULL 17/48] target/arm: Expand TBFLAG_ANY.MMUIDX to 4 bits Date: Fri, 7 Feb 2020 14:33:12 +0000 Message-Id: <20200207143343.30322-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200207143343.30322-1-peter.maydell@linaro.org> References: <20200207143343.30322-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: <qemu-devel.nongnu.org> List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe> List-Archive: <https://lists.nongnu.org/archive/html/qemu-devel> List-Post: <mailto:qemu-devel@nongnu.org> List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help> List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=subscribe> Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+importer=patchew.org@nongnu.org> X-ZohoMail-DKIM: pass (identity @linaro.org) From: Richard Henderson <richard.henderson@linaro.org> We are about to expand the number of mmuidx to 10, and so need 4 bits. For the benefit of reading the number out of -d exec, align it to the penultimate nibble. Tested-by: Alex Benn=C3=A9e <alex.bennee@linaro.org> Reviewed-by: Alex Benn=C3=A9e <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200206105448.4726-17-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/cpu.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index fce6a426c88..aa9728cff62 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3214,7 +3214,7 @@ typedef ARMCPU ArchCPU; * We put flags which are shared between 32 and 64 bit mode at the top * of the word, and flags which apply to only one mode at the bottom. * - * 31 21 18 14 9 0 + * 31 20 18 14 9 0 * +--------------+-----+-----+----------+--------------+ * | | | TBFLAG_A32 | | * | | +-----+----------+ TBFLAG_AM32 | @@ -3222,19 +3222,19 @@ typedef ARMCPU ArchCPU; * | | +-------------------------| * | | | TBFLAG_A64 | * +--------------+-----------+-------------------------+ - * 31 21 14 0 + * 31 20 14 0 * * Unless otherwise noted, these bits are cached in env->hflags. */ FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1) -FIELD(TBFLAG_ANY, MMUIDX, 28, 3) -FIELD(TBFLAG_ANY, SS_ACTIVE, 27, 1) -FIELD(TBFLAG_ANY, PSTATE_SS, 26, 1) /* Not cached. */ +FIELD(TBFLAG_ANY, SS_ACTIVE, 30, 1) +FIELD(TBFLAG_ANY, PSTATE_SS, 29, 1) /* Not cached. */ +FIELD(TBFLAG_ANY, BE_DATA, 28, 1) +FIELD(TBFLAG_ANY, MMUIDX, 24, 4) /* Target EL if we take a floating-point-disabled exception */ -FIELD(TBFLAG_ANY, FPEXC_EL, 24, 2) -FIELD(TBFLAG_ANY, BE_DATA, 23, 1) +FIELD(TBFLAG_ANY, FPEXC_EL, 22, 2) /* For A-profile only, target EL for debug exceptions. */ -FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 21, 2) +FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 20, 2) =20 /* * Bit usage when in AArch32 state, both A- and M-profile. --=20 2.20.1