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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id w1sm3796430wro.72.2020.02.07.06.34.00 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Feb 2020 06:34:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=TQPPrtjdwVz41m/9N7UotbrI/z67Nsmq49aMZwnBiso=; b=c3Uvx0+NGaZh+EE8H9FXU/5DChd2WqJC0q/0fZYhUeeUroSUHlgH44uO1cu1XMin8/ vWijA0KT/+n0sHXFECbOWunH2OxrEJBa5cxg7BYPf6kWI9jWm5mz1zVWOLXLM1LLZSAN ory2MWqpt4UzzKXKhT6O3bo/vc1rjRK2//8hGFhneF7Jd/lSgkZEeHdXG59T4SYMYIAA YYzApejpUd6uyqvqMzPOGqiLo+Ymz3cEVnyBr5dzOxZvG953IoeQn+EBylynzTWRC5Oo 4ck29Y5boghmdgJA7VfjXg/oht5T/x+96ZFw9BUlvE6p5ueNrk96Ru6cWE1idPrGfWZd 41Lw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TQPPrtjdwVz41m/9N7UotbrI/z67Nsmq49aMZwnBiso=; b=eZFIpF1Vj5jSllg17IS4ww26Z/SmGvw7RxPDT5a+Sq1A8dUS9LA1BEbSuz7cY4e5S5 AAmAJjtIZ3wvjYJi7sdb2Ko15Z9CrIr00c9zPtaaWKhpLVbysQTWqZC2Dqr0OQ/wpk/W wmmr9ep0/YdsbOtqLQggX1efWl3wWkxomJfCsXPftIcsUI8lOa2pvIzrInbUtl1CPRtk P/wK491U3WwXPzejRaMhbhLpbV1N1E9u18OjNbNiqESml7jEUp85sQwY2gurIUoXlZgH 1s/9h+uf2M0ciWUeusnarH+2hDc5Wc8iwxNdEKY7Tm45jYjDoVxyF4SFSm7xM1lXmKlP c+HQ== X-Gm-Message-State: APjAAAWNeXnjjPiLDJo54FgH0MirOyGMgFFEYsyGY7gXS7A8PmRDhs+9 uJxyrjDfiGqMtPqKfHDyxFy6o0nMYTA= X-Google-Smtp-Source: APXvYqxncHL4VYxNNb9l1QNKg0uV+T7ZaNCEg8CWXxlp7IFZdPq4zBV+ziM+2sxoG7ZgocR0jofccQ== X-Received: by 2002:a1c:a754:: with SMTP id q81mr4776965wme.139.1581086041888; Fri, 07 Feb 2020 06:34:01 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/48] target/arm: Rename ARMMMUIdx_S1E2 to ARMMMUIdx_E2 Date: Fri, 7 Feb 2020 14:33:10 +0000 Message-Id: <20200207143343.30322-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200207143343.30322-1-peter.maydell@linaro.org> References: <20200207143343.30322-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32b X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Richard Henderson This is part of a reorganization to the set of mmu_idx. The non-secure EL2 regime only has a single stage translation; there is no point in pointing out that the idx is for stage1. Tested-by: Alex Benn=C3=A9e Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Message-id: 20200206105448.4726-15-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 4 ++-- target/arm/internals.h | 2 +- target/arm/helper.c | 22 +++++++++++----------- target/arm/translate.c | 2 +- 4 files changed, 15 insertions(+), 15 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 9f01ec8dd24..a188398b03e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2907,7 +2907,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, un= signed int excp_idx, typedef enum ARMMMUIdx { ARMMMUIdx_E10_0 =3D 0 | ARM_MMU_IDX_A, ARMMMUIdx_E10_1 =3D 1 | ARM_MMU_IDX_A, - ARMMMUIdx_S1E2 =3D 2 | ARM_MMU_IDX_A, + ARMMMUIdx_E2 =3D 2 | ARM_MMU_IDX_A, ARMMMUIdx_SE3 =3D 3 | ARM_MMU_IDX_A, ARMMMUIdx_SE10_0 =3D 4 | ARM_MMU_IDX_A, ARMMMUIdx_SE10_1 =3D 5 | ARM_MMU_IDX_A, @@ -2933,7 +2933,7 @@ typedef enum ARMMMUIdx { typedef enum ARMMMUIdxBit { ARMMMUIdxBit_E10_0 =3D 1 << 0, ARMMMUIdxBit_E10_1 =3D 1 << 1, - ARMMMUIdxBit_S1E2 =3D 1 << 2, + ARMMMUIdxBit_E2 =3D 1 << 2, ARMMMUIdxBit_SE3 =3D 1 << 3, ARMMMUIdxBit_SE10_0 =3D 1 << 4, ARMMMUIdxBit_SE10_1 =3D 1 << 5, diff --git a/target/arm/internals.h b/target/arm/internals.h index d8730fbbad3..5b8b9c233fe 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -812,7 +812,7 @@ static inline bool regime_is_secure(CPUARMState *env, A= RMMMUIdx mmu_idx) case ARMMMUIdx_E10_1: case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_Stage1_E1: - case ARMMMUIdx_S1E2: + case ARMMMUIdx_E2: case ARMMMUIdx_Stage2: case ARMMMUIdx_MPrivNegPri: case ARMMMUIdx_MUserNegPri: diff --git a/target/arm/helper.c b/target/arm/helper.c index f5d97da1c48..7ee41974566 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -728,7 +728,7 @@ static void tlbiall_hyp_write(CPUARMState *env, const A= RMCPRegInfo *ri, { CPUState *cs =3D env_cpu(env); =20 - tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E2); + tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E2); } =20 static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -736,7 +736,7 @@ static void tlbiall_hyp_is_write(CPUARMState *env, cons= t ARMCPRegInfo *ri, { CPUState *cs =3D env_cpu(env); =20 - tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E2); + tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E2); } =20 static void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -745,7 +745,7 @@ static void tlbimva_hyp_write(CPUARMState *env, const A= RMCPRegInfo *ri, CPUState *cs =3D env_cpu(env); uint64_t pageaddr =3D value & ~MAKE_64BIT_MASK(0, 12); =20 - tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E2); + tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E2); } =20 static void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -755,7 +755,7 @@ static void tlbimva_hyp_is_write(CPUARMState *env, cons= t ARMCPRegInfo *ri, uint64_t pageaddr =3D value & ~MAKE_64BIT_MASK(0, 12); =20 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, - ARMMMUIdxBit_S1E2); + ARMMMUIdxBit_E2); } =20 static const ARMCPRegInfo cp_reginfo[] =3D { @@ -3238,7 +3238,7 @@ static void ats1h_write(CPUARMState *env, const ARMCP= RegInfo *ri, MMUAccessType access_type =3D ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA= _LOAD; uint64_t par64; =20 - par64 =3D do_ats_write(env, value, access_type, ARMMMUIdx_S1E2); + par64 =3D do_ats_write(env, value, access_type, ARMMMUIdx_E2); =20 A32_BANKED_CURRENT_REG_SET(env, par, par64); } @@ -3266,7 +3266,7 @@ static void ats_write64(CPUARMState *env, const ARMCP= RegInfo *ri, mmu_idx =3D secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_Stage1_E1; break; case 4: /* AT S1E2R, AT S1E2W */ - mmu_idx =3D ARMMMUIdx_S1E2; + mmu_idx =3D ARMMMUIdx_E2; break; case 6: /* AT S1E3R, AT S1E3W */ mmu_idx =3D ARMMMUIdx_SE3; @@ -4004,7 +4004,7 @@ static void tlbi_aa64_alle2_write(CPUARMState *env, c= onst ARMCPRegInfo *ri, ARMCPU *cpu =3D env_archcpu(env); CPUState *cs =3D CPU(cpu); =20 - tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E2); + tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E2); } =20 static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -4030,7 +4030,7 @@ static void tlbi_aa64_alle2is_write(CPUARMState *env,= const ARMCPRegInfo *ri, { CPUState *cs =3D env_cpu(env); =20 - tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E2); + tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E2); } =20 static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *= ri, @@ -4052,7 +4052,7 @@ static void tlbi_aa64_vae2_write(CPUARMState *env, co= nst ARMCPRegInfo *ri, CPUState *cs =3D CPU(cpu); uint64_t pageaddr =3D sextract64(value << 12, 0, 56); =20 - tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E2); + tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E2); } =20 static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -4105,7 +4105,7 @@ static void tlbi_aa64_vae2is_write(CPUARMState *env, = const ARMCPRegInfo *ri, uint64_t pageaddr =3D sextract64(value << 12, 0, 56); =20 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, - ARMMMUIdxBit_S1E2); + ARMMMUIdxBit_E2); } =20 static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *r= i, @@ -8711,7 +8711,7 @@ static inline uint32_t regime_el(CPUARMState *env, AR= MMMUIdx mmu_idx) { switch (mmu_idx) { case ARMMMUIdx_Stage2: - case ARMMMUIdx_S1E2: + case ARMMMUIdx_E2: return 2; case ARMMMUIdx_SE3: return 3; diff --git a/target/arm/translate.c b/target/arm/translate.c index 75afcb03fb4..91e2ca55154 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -152,7 +152,7 @@ static inline int get_a32_user_mem_index(DisasContext *= s) * otherwise, access as if at PL0. */ switch (s->mmu_idx) { - case ARMMMUIdx_S1E2: /* this one is UNPREDICTABLE */ + case ARMMMUIdx_E2: /* this one is UNPREDICTABLE */ case ARMMMUIdx_E10_0: case ARMMMUIdx_E10_1: return arm_to_core_mmu_idx(ARMMMUIdx_E10_0); --=20 2.20.1