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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id w1sm3796430wro.72.2020.02.07.06.33.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Feb 2020 06:33:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=d60he3qLJJvwlViODDZ4moMZIY8jMtrYyHcJABkXqeA=; b=tBZl/Gmh2hBI2tQLMvrHVWgc+NJh8WR9XWallr09mYuSE+CbGuga72TgzVRaSPqsbt h/7cj0yxDRBsoyYLTlZtcEvJ9U6rm4D6G0/5dnlqeR9jB/Px//Vtd+STNo57zLk2Nkyh vXxcKA1G3DTrkmuYLexpd9/K+iMpUS6SZgNZm8NMH43+n17ICk/NhlCzp6weWHybBVE0 FI2RZiTdt0j9JwqvUX9BYH7f6dRksZFwnvnIBVej2tUm34WfB+4MCyc3FSSQ4iARxmwY /bvyuaclRo788qTo6TKzyReb+54DyczVgOSwpy6Sl3nrivFfMDgDXcczR6n5Ns9qqqV9 FKTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=d60he3qLJJvwlViODDZ4moMZIY8jMtrYyHcJABkXqeA=; b=eBMhrB64ncUtIGgGEFHUevf7qEt3mOE7vH6V9+QWRkpyCovewQQj/0TsHuncTJdFLQ uX34OkxU1zW6m26i1rG4BqH8rHYdqIZ1ZAuZ0mRJKjc9NoWu5pf2adCys6UOpxE1oepg pwPG606XLFKel7Zs75io1TxvMZQx43MpCw3+FfkjCYr53VoTmYOvmNzm81P/JYmXG85G gKJcMtCqnfrxM6EZ9Gn9eOG6xT7OP9qtbDXPFQAqq1FHBiNK+11yyB8VR5tjFNHAY81a T0e6SvQCA9/jXUHRKaYeQwVSLHNHniUGNZrfMaQe94TT9zFMjk+V8UFGsOVu+/1doMWs 12yA== X-Gm-Message-State: APjAAAWW4+3VnvrZ4k/bthJHzomtz2sqgVDp2PgLT3IkqP9mqJAbm0td DuZENJbUGBgrqRJ0J9Kqdq3C53RXKYA= X-Google-Smtp-Source: APXvYqxuuQvyVoPQLlvsJzCJ5x/2c9EhLEYeSl+tJglXqUeeATjJO1HFZEJWkHRtP/f+YuFq8zmQnw== X-Received: by 2002:a7b:c119:: with SMTP id w25mr4789605wmi.116.1581086039593; Fri, 07 Feb 2020 06:33:59 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/48] target/arm: Rename ARMMMUIdx_S1SE[01] to ARMMMUIdx_SE10_[01] Date: Fri, 7 Feb 2020 14:33:08 +0000 Message-Id: <20200207143343.30322-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200207143343.30322-1-peter.maydell@linaro.org> References: <20200207143343.30322-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Richard Henderson This is part of a reorganization to the set of mmu_idx. This emphasizes that they apply to the Secure EL1&0 regime. Tested-by: Alex Benn=C3=A9e Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Message-id: 20200206105448.4726-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 8 ++++---- target/arm/internals.h | 4 ++-- target/arm/translate.h | 2 +- target/arm/helper.c | 26 +++++++++++++------------- target/arm/translate-a64.c | 4 ++-- target/arm/translate.c | 6 +++--- 6 files changed, 25 insertions(+), 25 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index afc3e76ce50..6cf2b3d6fd7 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2909,8 +2909,8 @@ typedef enum ARMMMUIdx { ARMMMUIdx_E10_1 =3D 1 | ARM_MMU_IDX_A, ARMMMUIdx_S1E2 =3D 2 | ARM_MMU_IDX_A, ARMMMUIdx_S1E3 =3D 3 | ARM_MMU_IDX_A, - ARMMMUIdx_S1SE0 =3D 4 | ARM_MMU_IDX_A, - ARMMMUIdx_S1SE1 =3D 5 | ARM_MMU_IDX_A, + ARMMMUIdx_SE10_0 =3D 4 | ARM_MMU_IDX_A, + ARMMMUIdx_SE10_1 =3D 5 | ARM_MMU_IDX_A, ARMMMUIdx_Stage2 =3D 6 | ARM_MMU_IDX_A, ARMMMUIdx_MUser =3D 0 | ARM_MMU_IDX_M, ARMMMUIdx_MPriv =3D 1 | ARM_MMU_IDX_M, @@ -2935,8 +2935,8 @@ typedef enum ARMMMUIdxBit { ARMMMUIdxBit_E10_1 =3D 1 << 1, ARMMMUIdxBit_S1E2 =3D 1 << 2, ARMMMUIdxBit_S1E3 =3D 1 << 3, - ARMMMUIdxBit_S1SE0 =3D 1 << 4, - ARMMMUIdxBit_S1SE1 =3D 1 << 5, + ARMMMUIdxBit_SE10_0 =3D 1 << 4, + ARMMMUIdxBit_SE10_1 =3D 1 << 5, ARMMMUIdxBit_Stage2 =3D 1 << 6, ARMMMUIdxBit_MUser =3D 1 << 0, ARMMMUIdxBit_MPriv =3D 1 << 1, diff --git a/target/arm/internals.h b/target/arm/internals.h index 280b5b0c822..eafcd326e11 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -820,8 +820,8 @@ static inline bool regime_is_secure(CPUARMState *env, A= RMMMUIdx mmu_idx) case ARMMMUIdx_MUser: return false; case ARMMMUIdx_S1E3: - case ARMMMUIdx_S1SE0: - case ARMMMUIdx_S1SE1: + case ARMMMUIdx_SE10_0: + case ARMMMUIdx_SE10_1: case ARMMMUIdx_MSPrivNegPri: case ARMMMUIdx_MSUserNegPri: case ARMMMUIdx_MSPriv: diff --git a/target/arm/translate.h b/target/arm/translate.h index b837b7fcbf1..a32b6b1b3a9 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -126,7 +126,7 @@ static inline int default_exception_el(DisasContext *s) * exceptions can only be routed to ELs above 1, so we target the high= er of * 1 or the current EL. */ - return (s->mmu_idx =3D=3D ARMMMUIdx_S1SE0 && s->secure_routed_to_el3) + return (s->mmu_idx =3D=3D ARMMMUIdx_SE10_0 && s->secure_routed_to_el3) ? 3 : MAX(1, s->current_el); } =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index 2d87c3a2e59..bbceb7a38ed 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3193,7 +3193,7 @@ static void ats_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) mmu_idx =3D ARMMMUIdx_Stage1_E1; break; case 1: - mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_Stage1_E1; + mmu_idx =3D secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_Stage1_E1; break; default: g_assert_not_reached(); @@ -3203,13 +3203,13 @@ static void ats_write(CPUARMState *env, const ARMCP= RegInfo *ri, uint64_t value) /* stage 1 current state PL0: ATS1CUR, ATS1CUW */ switch (el) { case 3: - mmu_idx =3D ARMMMUIdx_S1SE0; + mmu_idx =3D ARMMMUIdx_SE10_0; break; case 2: mmu_idx =3D ARMMMUIdx_Stage1_E0; break; case 1: - mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_Stage1_E0; + mmu_idx =3D secure ? ARMMMUIdx_SE10_0 : ARMMMUIdx_Stage1_E0; break; default: g_assert_not_reached(); @@ -3263,7 +3263,7 @@ static void ats_write64(CPUARMState *env, const ARMCP= RegInfo *ri, case 0: switch (ri->opc1) { case 0: /* AT S1E1R, AT S1E1W */ - mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_Stage1_E1; + mmu_idx =3D secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_Stage1_E1; break; case 4: /* AT S1E2R, AT S1E2W */ mmu_idx =3D ARMMMUIdx_S1E2; @@ -3276,13 +3276,13 @@ static void ats_write64(CPUARMState *env, const ARM= CPRegInfo *ri, } break; case 2: /* AT S1E0R, AT S1E0W */ - mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_Stage1_E0; + mmu_idx =3D secure ? ARMMMUIdx_SE10_0 : ARMMMUIdx_Stage1_E0; break; case 4: /* AT S12E1R, AT S12E1W */ - mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_E10_1; + mmu_idx =3D secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_E10_1; break; case 6: /* AT S12E0R, AT S12E0W */ - mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_E10_0; + mmu_idx =3D secure ? ARMMMUIdx_SE10_0 : ARMMMUIdx_E10_0; break; default: g_assert_not_reached(); @@ -3945,7 +3945,7 @@ static CPAccessResult aa64_cacheop_access(CPUARMState= *env, static int vae1_tlbmask(CPUARMState *env) { if (arm_is_secure_below_el3(env)) { - return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0; + return ARMMMUIdxBit_SE10_1 | ARMMMUIdxBit_SE10_0; } else { return ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_0; } @@ -3981,7 +3981,7 @@ static int alle1_tlbmask(CPUARMState *env) * stage 1 translations. */ if (arm_is_secure_below_el3(env)) { - return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0; + return ARMMMUIdxBit_SE10_1 | ARMMMUIdxBit_SE10_0; } else if (arm_feature(env, ARM_FEATURE_EL2)) { return ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_0 | ARMMMUIdxBit_Stag= e2; } else { @@ -8715,9 +8715,9 @@ static inline uint32_t regime_el(CPUARMState *env, AR= MMMUIdx mmu_idx) return 2; case ARMMMUIdx_S1E3: return 3; - case ARMMMUIdx_S1SE0: + case ARMMMUIdx_SE10_0: return arm_el_is_aa64(env, 3) ? 1 : 3; - case ARMMMUIdx_S1SE1: + case ARMMMUIdx_SE10_1: case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_MPrivNegPri: @@ -8856,7 +8856,7 @@ bool arm_s1_regime_using_lpae_format(CPUARMState *env= , ARMMMUIdx mmu_idx) static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) { switch (mmu_idx) { - case ARMMMUIdx_S1SE0: + case ARMMMUIdx_SE10_0: case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_MUser: case ARMMMUIdx_MSUser: @@ -11296,7 +11296,7 @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el) } =20 if (el < 2 && arm_is_secure_below_el3(env)) { - return ARMMMUIdx_S1SE0 + el; + return ARMMMUIdx_SE10_0 + el; } else { return ARMMMUIdx_E10_0 + el; } diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index d0d13e21754..fcfb96ce1fb 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -116,8 +116,8 @@ static inline int get_a64_user_mem_index(DisasContext *= s) case ARMMMUIdx_E10_1: useridx =3D ARMMMUIdx_E10_0; break; - case ARMMMUIdx_S1SE1: - useridx =3D ARMMMUIdx_S1SE0; + case ARMMMUIdx_SE10_1: + useridx =3D ARMMMUIdx_SE10_0; break; case ARMMMUIdx_Stage2: g_assert_not_reached(); diff --git a/target/arm/translate.c b/target/arm/translate.c index 70b1fd3fe2a..a2019a9b2a9 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -157,9 +157,9 @@ static inline int get_a32_user_mem_index(DisasContext *= s) case ARMMMUIdx_E10_1: return arm_to_core_mmu_idx(ARMMMUIdx_E10_0); case ARMMMUIdx_S1E3: - case ARMMMUIdx_S1SE0: - case ARMMMUIdx_S1SE1: - return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0); + case ARMMMUIdx_SE10_0: + case ARMMMUIdx_SE10_1: + return arm_to_core_mmu_idx(ARMMMUIdx_SE10_0); case ARMMMUIdx_MUser: case ARMMMUIdx_MPriv: return arm_to_core_mmu_idx(ARMMMUIdx_MUser); --=20 2.20.1