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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id w1sm3796430wro.72.2020.02.07.06.33.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Feb 2020 06:33:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=t2XXbAjw3+imLyFMwFKsGx9WTEwn7dvujeV3QiuK/hQ=; b=pEQgOKtKdQsOlcSBsiMGHJYeyHjquzf56GlaCDJwOcIZi7mNzcOOPnDTKS+RpMc/sa iiNKhIRNgtUycqBT4wSoqhJpElwIsF62GPvzNfRKCPDiEmspkVFAiqMByyqWNhf5/Mm+ llAgrP3MqA3p3p/Ja1F9NkcUPcirvKdjRU4OL3CV63wu0MMleGfn9Ne7GOV6vJzy9YgV WpRpI8Wm7RZyKvtSZlRVjIor/5mLIlktfYnH0M/Y5lLg7aHx242KED7xA562CpKjvLZd IaryhOPypkziF4CqeufOUIkygd/3Al/f+tNEb4TXqsiJdm13paqCkw5PFT8ZJeL/E5Zy U6Vg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=t2XXbAjw3+imLyFMwFKsGx9WTEwn7dvujeV3QiuK/hQ=; b=fOaNb+rO3KlPM4NIN3XD5eBcwigd9tvXxe6tGudyEYx0A4B/eJDKzfYy9DKn4pybxK Zs/fVLGTZNpOE0iBl2s04j5mzD5L1zHRpAwU3dDMeslLV1aGzjrHnYrOMJwL7adhvsTT CTs+iZd6S4BDRHZ/rxAVWGwCtDqtKhi9sUWnWmWviHPuxDF/VhmLWjf/ds76XWrT9hbz 21f44T5fpud0L9480Em93Imx6xU+veiAvFtE1sn1MC4v8nW5Igsgu1MF2q3+R64Lt5Vh Agl/x9DFJfjnx7DlvRU5gfq5Xpyccet3uqZqHqcCMElLPTQptarAm/rp7eBbqqLjLByj Mh6A== X-Gm-Message-State: APjAAAWZ1xsNjs0tnM3UcUfsaZTn33De5VuWILx1cElO0S4a/TNv+D2O iHiKuRg4A29R5qMC+5YNdjvMilHMF20= X-Google-Smtp-Source: APXvYqxazx1NkQ+pAPGIJlnwqMDz/8fFmwbG0GLyfQdQUOl8qVUDgb9RoZKDUIlXoyyd6DrX6759Gg== X-Received: by 2002:adf:a453:: with SMTP id e19mr4845211wra.48.1581086038577; Fri, 07 Feb 2020 06:33:58 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/48] target/arm: Rename ARMMMUIdx_S1NSE* to ARMMMUIdx_Stage1_E* Date: Fri, 7 Feb 2020 14:33:07 +0000 Message-Id: <20200207143343.30322-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200207143343.30322-1-peter.maydell@linaro.org> References: <20200207143343.30322-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42a X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Richard Henderson This is part of a reorganization to the set of mmu_idx. The EL1&0 regime is the only one that uses 2-stage translation. Spelling out Stage avoids confusion with Secure. Tested-by: Alex Benn=C3=A9e Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Message-id: 20200206105448.4726-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 4 ++-- target/arm/internals.h | 6 +++--- target/arm/helper.c | 27 ++++++++++++++------------- 3 files changed, 19 insertions(+), 18 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c6da3d3043a..afc3e76ce50 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2923,8 +2923,8 @@ typedef enum ARMMMUIdx { /* Indexes below here don't have TLBs and are used only for AT system * instructions or for the first stage of an S12 page table walk. */ - ARMMMUIdx_S1NSE0 =3D 0 | ARM_MMU_IDX_NOTLB, - ARMMMUIdx_S1NSE1 =3D 1 | ARM_MMU_IDX_NOTLB, + ARMMMUIdx_Stage1_E0 =3D 0 | ARM_MMU_IDX_NOTLB, + ARMMMUIdx_Stage1_E1 =3D 1 | ARM_MMU_IDX_NOTLB, } ARMMMUIdx; =20 /* Bit macros for the core-mmu-index values for each index, diff --git a/target/arm/internals.h b/target/arm/internals.h index 1509e45e98a..280b5b0c822 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -810,8 +810,8 @@ static inline bool regime_is_secure(CPUARMState *env, A= RMMMUIdx mmu_idx) switch (mmu_idx) { case ARMMMUIdx_E10_0: case ARMMMUIdx_E10_1: - case ARMMMUIdx_S1NSE0: - case ARMMMUIdx_S1NSE1: + case ARMMMUIdx_Stage1_E0: + case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_S1E2: case ARMMMUIdx_Stage2: case ARMMMUIdx_MPrivNegPri: @@ -975,7 +975,7 @@ ARMMMUIdx arm_mmu_idx(CPUARMState *env); #ifdef CONFIG_USER_ONLY static inline ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) { - return ARMMMUIdx_S1NSE0; + return ARMMMUIdx_Stage1_E0; } #else ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env); diff --git a/target/arm/helper.c b/target/arm/helper.c index a6d4f449cc7..2d87c3a2e59 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3041,7 +3041,8 @@ static uint64_t do_ats_write(CPUARMState *env, uint64= _t value, bool take_exc =3D false; =20 if (fi.s1ptw && current_el =3D=3D 1 && !arm_is_secure(env) - && (mmu_idx =3D=3D ARMMMUIdx_S1NSE1 || mmu_idx =3D=3D ARMMMUId= x_S1NSE0)) { + && (mmu_idx =3D=3D ARMMMUIdx_Stage1_E1 || + mmu_idx =3D=3D ARMMMUIdx_Stage1_E0)) { /* * Synchronous stage 2 fault on an access made as part of the * translation table walk for AT S1E0* or AT S1E1* insn @@ -3189,10 +3190,10 @@ static void ats_write(CPUARMState *env, const ARMCP= RegInfo *ri, uint64_t value) mmu_idx =3D ARMMMUIdx_S1E3; break; case 2: - mmu_idx =3D ARMMMUIdx_S1NSE1; + mmu_idx =3D ARMMMUIdx_Stage1_E1; break; case 1: - mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1; + mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_Stage1_E1; break; default: g_assert_not_reached(); @@ -3205,10 +3206,10 @@ static void ats_write(CPUARMState *env, const ARMCP= RegInfo *ri, uint64_t value) mmu_idx =3D ARMMMUIdx_S1SE0; break; case 2: - mmu_idx =3D ARMMMUIdx_S1NSE0; + mmu_idx =3D ARMMMUIdx_Stage1_E0; break; case 1: - mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0; + mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_Stage1_E0; break; default: g_assert_not_reached(); @@ -3262,7 +3263,7 @@ static void ats_write64(CPUARMState *env, const ARMCP= RegInfo *ri, case 0: switch (ri->opc1) { case 0: /* AT S1E1R, AT S1E1W */ - mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1; + mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_Stage1_E1; break; case 4: /* AT S1E2R, AT S1E2W */ mmu_idx =3D ARMMMUIdx_S1E2; @@ -3275,7 +3276,7 @@ static void ats_write64(CPUARMState *env, const ARMCP= RegInfo *ri, } break; case 2: /* AT S1E0R, AT S1E0W */ - mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0; + mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_Stage1_E0; break; case 4: /* AT S12E1R, AT S12E1W */ mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_E10_1; @@ -8717,8 +8718,8 @@ static inline uint32_t regime_el(CPUARMState *env, AR= MMMUIdx mmu_idx) case ARMMMUIdx_S1SE0: return arm_el_is_aa64(env, 3) ? 1 : 3; case ARMMMUIdx_S1SE1: - case ARMMMUIdx_S1NSE0: - case ARMMMUIdx_S1NSE1: + case ARMMMUIdx_Stage1_E0: + case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_MPrivNegPri: case ARMMMUIdx_MUserNegPri: case ARMMMUIdx_MPriv: @@ -8776,7 +8777,7 @@ static inline bool regime_translation_disabled(CPUARM= State *env, } =20 if ((env->cp15.hcr_el2 & HCR_DC) && - (mmu_idx =3D=3D ARMMMUIdx_S1NSE0 || mmu_idx =3D=3D ARMMMUIdx_S1NSE= 1)) { + (mmu_idx =3D=3D ARMMMUIdx_Stage1_E0 || mmu_idx =3D=3D ARMMMUIdx_St= age1_E1)) { /* HCR.DC means SCTLR_EL1.M behaves as 0 */ return true; } @@ -8821,7 +8822,7 @@ static inline TCR *regime_tcr(CPUARMState *env, ARMMM= UIdx mmu_idx) static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) { if (mmu_idx =3D=3D ARMMMUIdx_E10_0 || mmu_idx =3D=3D ARMMMUIdx_E10_1) { - mmu_idx +=3D (ARMMMUIdx_S1NSE0 - ARMMMUIdx_E10_0); + mmu_idx +=3D (ARMMMUIdx_Stage1_E0 - ARMMMUIdx_E10_0); } return mmu_idx; } @@ -8856,7 +8857,7 @@ static inline bool regime_is_user(CPUARMState *env, A= RMMMUIdx mmu_idx) { switch (mmu_idx) { case ARMMMUIdx_S1SE0: - case ARMMMUIdx_S1NSE0: + case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_MUser: case ARMMMUIdx_MSUser: case ARMMMUIdx_MUserNegPri: @@ -9087,7 +9088,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMM= MUIdx mmu_idx, hwaddr addr, MemTxAttrs txattrs, ARMMMUFaultInfo *fi) { - if ((mmu_idx =3D=3D ARMMMUIdx_S1NSE0 || mmu_idx =3D=3D ARMMMUIdx_S1NSE= 1) && + if ((mmu_idx =3D=3D ARMMMUIdx_Stage1_E0 || mmu_idx =3D=3D ARMMMUIdx_St= age1_E1) && !regime_translation_disabled(env, ARMMMUIdx_Stage2)) { target_ulong s2size; hwaddr s2pa; --=20 2.20.1