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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id w1sm3796430wro.72.2020.02.07.06.33.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Feb 2020 06:33:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=K/U+IIcELqA/8+RNhiPHTX2soklHMEv4FEE0tCKxqow=; b=GnlbV/FsFVsWFeLtJ9pRyZUL61gIURXtuCtqlyNNHwi4bWJm9DslWxdtLqirP/mWGN OenTg+uhy4Fba39G4KiTVUmmX7pQJwNDqKp9akAs3aPKUslkGcSqzR8E1O9qJTmFar0W XOPAE6YZnyDTU8Dmdb3izZzbpNYfsCdnpvbe/1JRaxVCDRu/at0VZF+pWh03EbBa8uby RSeyCApaZb4ta8SZfRcr230P4OPwKfzdB08m1WUSE1FjzhH1cWvl8BTE5CfSBqcS9CNj 4GariruQKOclBHABpPqmnSSF1taYaaOJ41YmyJ5q+dB8lZek/Hrfgjesg/xsOkp+bHTu +Hdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=K/U+IIcELqA/8+RNhiPHTX2soklHMEv4FEE0tCKxqow=; b=I+qYyUvb2uGoUPBF+NUeua6iaZ/a3AxIDsGd4n6/Nf7YwnJbJmaCX99KhroUp7eXWb iq43KZkRoS6wh41RHkjyRH2Zmj6b+99aFk6cBvG+3903qzYEAXMsVchrtKwH9VJMDRkH 5BsDFW4Qrq9SVgsv6x39XZoSJ35AdB8ixMbLRzF6jvWjk3iotBfEvu74N93bTLWAd0sx yAnCESZxXX7UYTY6l67xGDahPssuApklkixlpPn6ckNGoXvGeOpCaKfgFzElRFI5aqwq SkwLGIiIaI6aTesGNKr/0JMJVrxfKry+g/FaZtPnywsTuL3An4cw705BtEufdcej8E+u 9s3Q== X-Gm-Message-State: APjAAAVvGYcyzKeBhj4+vkhIFsMYv0BnLfzAeAG4Njw+lAy3yaIDirWN AK2FrmkcLP4ULPlJczhJd6y7FMNGyrM= X-Google-Smtp-Source: APXvYqzEjfEBbngQ5VbyWGry5U/LEhMMfDaXqyPqUbKo67MmeMiiC/WCE1lBLVoGWzfYMS3F0i1D1w== X-Received: by 2002:a7b:c0da:: with SMTP id s26mr4649661wmh.52.1581086034907; Fri, 07 Feb 2020 06:33:54 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/48] target/arm: Simplify tlb_force_broadcast alternatives Date: Fri, 7 Feb 2020 14:33:04 +0000 Message-Id: <20200207143343.30322-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200207143343.30322-1-peter.maydell@linaro.org> References: <20200207143343.30322-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Richard Henderson Rather than call to a separate function and re-compute any parameters for the flush, simply use the correct flush function directly. Tested-by: Alex Benn=C3=A9e Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Message-id: 20200206105448.4726-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 52 +++++++++++++++++++++------------------------ 1 file changed, 24 insertions(+), 28 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 49da685b296..bf69935550f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -614,56 +614,54 @@ static void tlbiall_write(CPUARMState *env, const ARM= CPRegInfo *ri, uint64_t value) { /* Invalidate all (TLBIALL) */ - ARMCPU *cpu =3D env_archcpu(env); + CPUState *cs =3D env_cpu(env); =20 if (tlb_force_broadcast(env)) { - tlbiall_is_write(env, NULL, value); - return; + tlb_flush_all_cpus_synced(cs); + } else { + tlb_flush(cs); } - - tlb_flush(CPU(cpu)); } =20 static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */ - ARMCPU *cpu =3D env_archcpu(env); + CPUState *cs =3D env_cpu(env); =20 + value &=3D TARGET_PAGE_MASK; if (tlb_force_broadcast(env)) { - tlbimva_is_write(env, NULL, value); - return; + tlb_flush_page_all_cpus_synced(cs, value); + } else { + tlb_flush_page(cs, value); } - - tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK); } =20 static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { /* Invalidate by ASID (TLBIASID) */ - ARMCPU *cpu =3D env_archcpu(env); + CPUState *cs =3D env_cpu(env); =20 if (tlb_force_broadcast(env)) { - tlbiasid_is_write(env, NULL, value); - return; + tlb_flush_all_cpus_synced(cs); + } else { + tlb_flush(cs); } - - tlb_flush(CPU(cpu)); } =20 static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */ - ARMCPU *cpu =3D env_archcpu(env); + CPUState *cs =3D env_cpu(env); =20 + value &=3D TARGET_PAGE_MASK; if (tlb_force_broadcast(env)) { - tlbimvaa_is_write(env, NULL, value); - return; + tlb_flush_page_all_cpus_synced(cs, value); + } else { + tlb_flush_page(cs, value); } - - tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK); } =20 static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -3965,11 +3963,10 @@ static void tlbi_aa64_vmalle1_write(CPUARMState *en= v, const ARMCPRegInfo *ri, int mask =3D vae1_tlbmask(env); =20 if (tlb_force_broadcast(env)) { - tlbi_aa64_vmalle1is_write(env, NULL, value); - return; + tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); + } else { + tlb_flush_by_mmuidx(cs, mask); } - - tlb_flush_by_mmuidx(cs, mask); } =20 static int alle1_tlbmask(CPUARMState *env) @@ -4091,11 +4088,10 @@ static void tlbi_aa64_vae1_write(CPUARMState *env, = const ARMCPRegInfo *ri, uint64_t pageaddr =3D sextract64(value << 12, 0, 56); =20 if (tlb_force_broadcast(env)) { - tlbi_aa64_vae1is_write(env, NULL, value); - return; + tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, mask); + } else { + tlb_flush_page_by_mmuidx(cs, pageaddr, mask); } - - tlb_flush_page_by_mmuidx(cs, pageaddr, mask); } =20 static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *r= i, --=20 2.20.1