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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 01/48] target/arm/monitor: query-cpu-model-expansion crashed
qemu when using machine type none
Date: Fri, 7 Feb 2020 14:32:56 +0000
Message-Id: <20200207143343.30322-2-peter.maydell@linaro.org>
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From: Liang Yan <lyan@suse.com>
Commit e19afd566781 mentioned that target-arm only supports queryable
cpu models 'max', 'host', and the current type when KVM is in use.
The logic works well until using machine type none.
For machine type none, cpu_type will be null if cpu option is not
set by command line, strlen(cpu_type) will terminate process.
So We add a check above it.
This won't affect i386 and s390x since they do not use current_cpu.
Signed-off-by: Liang Yan <lyan@suse.com>
Message-id: 20200203134251.12986-1-lyan@suse.com
Reviewed-by: Andrew Jones <drjones@redhat.com>
Tested-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/monitor.c | 15 +++++++++------
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/target/arm/monitor.c b/target/arm/monitor.c
index 9725dfff16d..c2dc7908de7 100644
--- a/target/arm/monitor.c
+++ b/target/arm/monitor.c
@@ -137,17 +137,20 @@ CpuModelExpansionInfo *qmp_query_cpu_model_expansion(=
CpuModelExpansionType type,
}
=20
if (kvm_enabled()) {
- const char *cpu_type =3D current_machine->cpu_type;
- int len =3D strlen(cpu_type) - strlen(ARM_CPU_TYPE_SUFFIX);
bool supported =3D false;
=20
if (!strcmp(model->name, "host") || !strcmp(model->name, "max")) {
/* These are kvmarm's recommended cpu types */
supported =3D true;
- } else if (strlen(model->name) =3D=3D len &&
- !strncmp(model->name, cpu_type, len)) {
- /* KVM is enabled and we're using this type, so it works. */
- supported =3D true;
+ } else if (current_machine->cpu_type) {
+ const char *cpu_type =3D current_machine->cpu_type;
+ int len =3D strlen(cpu_type) - strlen(ARM_CPU_TYPE_SUFFIX);
+
+ if (strlen(model->name) =3D=3D len &&
+ !strncmp(model->name, cpu_type, len)) {
+ /* KVM is enabled and we're using this type, so it works. =
*/
+ supported =3D true;
+ }
}
if (!supported) {
error_setg(errp, "We cannot guarantee the CPU type '%s' works "
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 02/48] target/arm: Define isar_feature_aa64_vh
Date: Fri, 7 Feb 2020 14:32:57 +0000
Message-Id: <20200207143343.30322-3-peter.maydell@linaro.org>
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From: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Reviewed-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200206105448.4726-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 608fcbd0b75..2a53f5d09be 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3685,6 +3685,11 @@ static inline bool isar_feature_aa64_sve(const ARMIS=
ARegisters *id)
return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) !=3D 0;
}
=20
+static inline bool isar_feature_aa64_vh(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) !=3D 0;
+}
+
static inline bool isar_feature_aa64_lor(const ARMISARegisters *id)
{
return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) !=3D 0;
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 03/48] target/arm: Enable HCR_E2H for VHE
Date: Fri, 7 Feb 2020 14:32:58 +0000
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Tested-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 7 -------
target/arm/helper.c | 6 +++++-
2 files changed, 5 insertions(+), 8 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 2a53f5d09be..0e68704a908 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1424,13 +1424,6 @@ static inline void xpsr_write(CPUARMState *env, uint=
32_t val, uint32_t mask)
#define HCR_ATA (1ULL << 56)
#define HCR_DCT (1ULL << 57)
=20
-/*
- * When we actually implement ARMv8.1-VHE we should add HCR_E2H to
- * HCR_MASK and then clear it again if the feature bit is not set in
- * hcr_write().
- */
-#define HCR_MASK ((1ULL << 34) - 1)
-
#define SCR_NS (1U << 0)
#define SCR_IRQ (1U << 1)
#define SCR_FIQ (1U << 2)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 19a57a17da5..f5ce05fdf33 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -4721,7 +4721,8 @@ static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] =
=3D {
static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v=
alue)
{
ARMCPU *cpu =3D env_archcpu(env);
- uint64_t valid_mask =3D HCR_MASK;
+ /* Begin with bits defined in base ARMv8.0. */
+ uint64_t valid_mask =3D MAKE_64BIT_MASK(0, 34);
=20
if (arm_feature(env, ARM_FEATURE_EL3)) {
valid_mask &=3D ~HCR_HCD;
@@ -4735,6 +4736,9 @@ static void hcr_write(CPUARMState *env, const ARMCPRe=
gInfo *ri, uint64_t value)
*/
valid_mask &=3D ~HCR_TSC;
}
+ if (cpu_isar_feature(aa64_vh, cpu)) {
+ valid_mask |=3D HCR_E2H;
+ }
if (cpu_isar_feature(aa64_lor, cpu)) {
valid_mask |=3D HCR_TLOR;
}
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 04/48] target/arm: Add CONTEXTIDR_EL2
Date: Fri, 7 Feb 2020 14:32:59 +0000
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From: Richard Henderson <richard.henderson@linaro.org>
Not all of the breakpoint types are supported, but those that
only examine contextidr are extended to support the new register.
Tested-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Reviewed-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200206105448.4726-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/debug_helper.c | 50 +++++++++++++++++++++++++++++----------
target/arm/helper.c | 12 ++++++++++
2 files changed, 50 insertions(+), 12 deletions(-)
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
index dde80273ff1..2e3e90c6a57 100644
--- a/target/arm/debug_helper.c
+++ b/target/arm/debug_helper.c
@@ -20,6 +20,7 @@ static bool linked_bp_matches(ARMCPU *cpu, int lbn)
int ctx_cmps =3D extract32(cpu->dbgdidr, 20, 4);
int bt;
uint32_t contextidr;
+ uint64_t hcr_el2;
=20
/*
* Links to unimplemented or non-context aware breakpoints are
@@ -40,24 +41,44 @@ static bool linked_bp_matches(ARMCPU *cpu, int lbn)
}
=20
bt =3D extract64(bcr, 20, 4);
-
- /*
- * We match the whole register even if this is AArch32 using the
- * short descriptor format (in which case it holds both PROCID and ASI=
D),
- * since we don't implement the optional v7 context ID masking.
- */
- contextidr =3D extract64(env->cp15.contextidr_el[1], 0, 32);
+ hcr_el2 =3D arm_hcr_el2_eff(env);
=20
switch (bt) {
case 3: /* linked context ID match */
- if (arm_current_el(env) > 1) {
- /* Context matches never fire in EL2 or (AArch64) EL3 */
+ switch (arm_current_el(env)) {
+ default:
+ /* Context matches never fire in AArch64 EL3 */
return false;
+ case 2:
+ if (!(hcr_el2 & HCR_E2H)) {
+ /* Context matches never fire in EL2 without E2H enabled. =
*/
+ return false;
+ }
+ contextidr =3D env->cp15.contextidr_el[2];
+ break;
+ case 1:
+ contextidr =3D env->cp15.contextidr_el[1];
+ break;
+ case 0:
+ if ((hcr_el2 & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)=
) {
+ contextidr =3D env->cp15.contextidr_el[2];
+ } else {
+ contextidr =3D env->cp15.contextidr_el[1];
+ }
+ break;
}
- return (contextidr =3D=3D extract64(env->cp15.dbgbvr[lbn], 0, 32));
- case 5: /* linked address mismatch (reserved in AArch64) */
+ break;
+
+ case 7: /* linked contextidr_el1 match */
+ contextidr =3D env->cp15.contextidr_el[1];
+ break;
+ case 13: /* linked contextidr_el2 match */
+ contextidr =3D env->cp15.contextidr_el[2];
+ break;
+
case 9: /* linked VMID match (reserved if no EL2) */
case 11: /* linked context ID and VMID match (reserved if no EL2) */
+ case 15: /* linked full context ID match */
default:
/*
* Links to Unlinked context breakpoints must generate no
@@ -66,7 +87,12 @@ static bool linked_bp_matches(ARMCPU *cpu, int lbn)
return false;
}
=20
- return false;
+ /*
+ * We match the whole register even if this is AArch32 using the
+ * short descriptor format (in which case it holds both PROCID and ASI=
D),
+ * since we don't implement the optional v7 context ID masking.
+ */
+ return contextidr =3D=3D (uint32_t)env->cp15.dbgbvr[lbn];
}
=20
static bool bp_wp_matches(ARMCPU *cpu, int n, bool is_wp)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index f5ce05fdf33..fe7991864a6 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6126,6 +6126,14 @@ static const ARMCPRegInfo jazelle_regs[] =3D {
REGINFO_SENTINEL
};
=20
+static const ARMCPRegInfo vhe_reginfo[] =3D {
+ { .name =3D "CONTEXTIDR_EL2", .state =3D ARM_CP_STATE_AA64,
+ .opc0 =3D 3, .opc1 =3D 4, .crn =3D 13, .crm =3D 0, .opc2 =3D 1,
+ .access =3D PL2_RW,
+ .fieldoffset =3D offsetof(CPUARMState, cp15.contextidr_el[2]) },
+ REGINFO_SENTINEL
+};
+
void register_cp_regs_for_features(ARMCPU *cpu)
{
/* Register all the coprocessor registers based on feature bits */
@@ -7089,6 +7097,10 @@ void register_cp_regs_for_features(ARMCPU *cpu)
define_arm_cp_regs(cpu, lor_reginfo);
}
=20
+ if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu=
)) {
+ define_arm_cp_regs(cpu, vhe_reginfo);
+ }
+
if (cpu_isar_feature(aa64_sve, cpu)) {
define_one_arm_cp_reg(cpu, &zcr_el1_reginfo);
if (arm_feature(env, ARM_FEATURE_EL2)) {
--=20
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 05/48] target/arm: Add TTBR1_EL2
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From: Richard Henderson <richard.henderson@linaro.org>
At the same time, add writefn to TTBR0_EL2 and TCR_EL2.
A later patch will update any ASID therein.
Tested-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Reviewed-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200206105448.4726-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index fe7991864a6..c7ee0d603f4 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -3533,6 +3533,13 @@ static void vmsa_ttbr_write(CPUARMState *env, const =
ARMCPRegInfo *ri,
raw_write(env, ri, value);
}
=20
+static void vmsa_tcr_ttbr_el2_write(CPUARMState *env, const ARMCPRegInfo *=
ri,
+ uint64_t value)
+{
+ /* TODO: There are ASID fields in here with HCR_EL2.E2H */
+ raw_write(env, ri, value);
+}
+
static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
@@ -4979,7 +4986,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D {
.fieldoffset =3D offsetof(CPUARMState, cp15.tpidr_el[2]) },
{ .name =3D "TTBR0_EL2", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 0,
- .access =3D PL2_RW, .resetvalue =3D 0,
+ .access =3D PL2_RW, .resetvalue =3D 0, .writefn =3D vmsa_tcr_ttbr_el=
2_write,
.fieldoffset =3D offsetof(CPUARMState, cp15.ttbr0_el[2]) },
{ .name =3D "HTTBR", .cp =3D 15, .opc1 =3D 4, .crm =3D 2,
.access =3D PL2_RW, .type =3D ARM_CP_64BIT | ARM_CP_ALIAS,
@@ -6131,6 +6138,10 @@ static const ARMCPRegInfo vhe_reginfo[] =3D {
.opc0 =3D 3, .opc1 =3D 4, .crn =3D 13, .crm =3D 0, .opc2 =3D 1,
.access =3D PL2_RW,
.fieldoffset =3D offsetof(CPUARMState, cp15.contextidr_el[2]) },
+ { .name =3D "TTBR1_EL2", .state =3D ARM_CP_STATE_AA64,
+ .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 1,
+ .access =3D PL2_RW, .writefn =3D vmsa_tcr_ttbr_el2_write,
+ .fieldoffset =3D offsetof(CPUARMState, cp15.ttbr1_el[2]) },
REGINFO_SENTINEL
};
=20
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 06/48] target/arm: Update CNTVCT_EL0 for VHE
Date: Fri, 7 Feb 2020 14:33:01 +0000
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From: Richard Henderson <richard.henderson@linaro.org>
The virtual offset may be 0 depending on EL, E2H and TGE.
Tested-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Reviewed-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200206105448.4726-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 40 +++++++++++++++++++++++++++++++++++++---
1 file changed, 37 insertions(+), 3 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index c7ee0d603f4..dbfdf2324b4 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -2515,9 +2515,31 @@ static uint64_t gt_cnt_read(CPUARMState *env, const =
ARMCPRegInfo *ri)
return gt_get_countervalue(env);
}
=20
+static uint64_t gt_virt_cnt_offset(CPUARMState *env)
+{
+ uint64_t hcr;
+
+ switch (arm_current_el(env)) {
+ case 2:
+ hcr =3D arm_hcr_el2_eff(env);
+ if (hcr & HCR_E2H) {
+ return 0;
+ }
+ break;
+ case 0:
+ hcr =3D arm_hcr_el2_eff(env);
+ if ((hcr & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)) {
+ return 0;
+ }
+ break;
+ }
+
+ return env->cp15.cntvoff_el2;
+}
+
static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
- return gt_get_countervalue(env) - env->cp15.cntvoff_el2;
+ return gt_get_countervalue(env) - gt_virt_cnt_offset(env);
}
=20
static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -2532,7 +2554,13 @@ static void gt_cval_write(CPUARMState *env, const AR=
MCPRegInfo *ri,
static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri,
int timeridx)
{
- uint64_t offset =3D timeridx =3D=3D GTIMER_VIRT ? env->cp15.cntvoff_el=
2 : 0;
+ uint64_t offset =3D 0;
+
+ switch (timeridx) {
+ case GTIMER_VIRT:
+ offset =3D gt_virt_cnt_offset(env);
+ break;
+ }
=20
return (uint32_t)(env->cp15.c14_timer[timeridx].cval -
(gt_get_countervalue(env) - offset));
@@ -2542,7 +2570,13 @@ static void gt_tval_write(CPUARMState *env, const AR=
MCPRegInfo *ri,
int timeridx,
uint64_t value)
{
- uint64_t offset =3D timeridx =3D=3D GTIMER_VIRT ? env->cp15.cntvoff_el=
2 : 0;
+ uint64_t offset =3D 0;
+
+ switch (timeridx) {
+ case GTIMER_VIRT:
+ offset =3D gt_virt_cnt_offset(env);
+ break;
+ }
=20
trace_arm_gt_tval_write(timeridx, value);
env->cp15.c14_timer[timeridx].cval =3D gt_get_countervalue(env) - offs=
et +
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 07/48] target/arm: Split out vae1_tlbmask
Date: Fri, 7 Feb 2020 14:33:02 +0000
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From: Richard Henderson <richard.henderson@linaro.org>
No functional change, but unify code sequences.
Tested-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daud=C3=A9 <philmd@redhat.com>
Reviewed-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200206105448.4726-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 32 +++++++++++++-------------------
1 file changed, 13 insertions(+), 19 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index dbfdf2324b4..8b3bb51dee2 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -3940,42 +3940,36 @@ static CPAccessResult aa64_cacheop_access(CPUARMSta=
te *env,
* Page D4-1736 (DDI0487A.b)
*/
=20
+static int vae1_tlbmask(CPUARMState *env)
+{
+ if (arm_is_secure_below_el3(env)) {
+ return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0;
+ } else {
+ return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0;
+ }
+}
+
static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo=
*ri,
uint64_t value)
{
CPUState *cs =3D env_cpu(env);
- bool sec =3D arm_is_secure_below_el3(env);
+ int mask =3D vae1_tlbmask(env);
=20
- if (sec) {
- tlb_flush_by_mmuidx_all_cpus_synced(cs,
- ARMMMUIdxBit_S1SE1 |
- ARMMMUIdxBit_S1SE0);
- } else {
- tlb_flush_by_mmuidx_all_cpus_synced(cs,
- ARMMMUIdxBit_S12NSE1 |
- ARMMMUIdxBit_S12NSE0);
- }
+ tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);
}
=20
static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *=
ri,
uint64_t value)
{
CPUState *cs =3D env_cpu(env);
+ int mask =3D vae1_tlbmask(env);
=20
if (tlb_force_broadcast(env)) {
tlbi_aa64_vmalle1is_write(env, NULL, value);
return;
}
=20
- if (arm_is_secure_below_el3(env)) {
- tlb_flush_by_mmuidx(cs,
- ARMMMUIdxBit_S1SE1 |
- ARMMMUIdxBit_S1SE0);
- } else {
- tlb_flush_by_mmuidx(cs,
- ARMMMUIdxBit_S12NSE1 |
- ARMMMUIdxBit_S12NSE0);
- }
+ tlb_flush_by_mmuidx(cs, mask);
}
=20
static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 08/48] target/arm: Split out alle1_tlbmask
Date: Fri, 7 Feb 2020 14:33:03 +0000
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From: Richard Henderson <richard.henderson@linaro.org>
No functional change, but unify code sequences.
Tested-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daud=C3=A9 <philmd@redhat.com>
Reviewed-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200206105448.4726-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 86 +++++++++++++--------------------------------
1 file changed, 24 insertions(+), 62 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 8b3bb51dee2..49da685b296 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -3972,34 +3972,31 @@ static void tlbi_aa64_vmalle1_write(CPUARMState *en=
v, const ARMCPRegInfo *ri,
tlb_flush_by_mmuidx(cs, mask);
}
=20
-static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
- uint64_t value)
+static int alle1_tlbmask(CPUARMState *env)
{
- /* Note that the 'ALL' scope must invalidate both stage 1 and
+ /*
+ * Note that the 'ALL' scope must invalidate both stage 1 and
* stage 2 translations, whereas most other scopes only invalidate
* stage 1 translations.
*/
- ARMCPU *cpu =3D env_archcpu(env);
- CPUState *cs =3D CPU(cpu);
-
if (arm_is_secure_below_el3(env)) {
- tlb_flush_by_mmuidx(cs,
- ARMMMUIdxBit_S1SE1 |
- ARMMMUIdxBit_S1SE0);
+ return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0;
+ } else if (arm_feature(env, ARM_FEATURE_EL2)) {
+ return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0 | ARMMMUIdxBit_=
S2NS;
} else {
- if (arm_feature(env, ARM_FEATURE_EL2)) {
- tlb_flush_by_mmuidx(cs,
- ARMMMUIdxBit_S12NSE1 |
- ARMMMUIdxBit_S12NSE0 |
- ARMMMUIdxBit_S2NS);
- } else {
- tlb_flush_by_mmuidx(cs,
- ARMMMUIdxBit_S12NSE1 |
- ARMMMUIdxBit_S12NSE0);
- }
+ return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0;
}
}
=20
+static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+ CPUState *cs =3D env_cpu(env);
+ int mask =3D alle1_tlbmask(env);
+
+ tlb_flush_by_mmuidx(cs, mask);
+}
+
static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
@@ -4021,28 +4018,10 @@ static void tlbi_aa64_alle3_write(CPUARMState *env,=
const ARMCPRegInfo *ri,
static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *=
ri,
uint64_t value)
{
- /* Note that the 'ALL' scope must invalidate both stage 1 and
- * stage 2 translations, whereas most other scopes only invalidate
- * stage 1 translations.
- */
CPUState *cs =3D env_cpu(env);
- bool sec =3D arm_is_secure_below_el3(env);
- bool has_el2 =3D arm_feature(env, ARM_FEATURE_EL2);
+ int mask =3D alle1_tlbmask(env);
=20
- if (sec) {
- tlb_flush_by_mmuidx_all_cpus_synced(cs,
- ARMMMUIdxBit_S1SE1 |
- ARMMMUIdxBit_S1SE0);
- } else if (has_el2) {
- tlb_flush_by_mmuidx_all_cpus_synced(cs,
- ARMMMUIdxBit_S12NSE1 |
- ARMMMUIdxBit_S12NSE0 |
- ARMMMUIdxBit_S2NS);
- } else {
- tlb_flush_by_mmuidx_all_cpus_synced(cs,
- ARMMMUIdxBit_S12NSE1 |
- ARMMMUIdxBit_S12NSE0);
- }
+ tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);
}
=20
static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *=
ri,
@@ -4092,20 +4071,11 @@ static void tlbi_aa64_vae3_write(CPUARMState *env, =
const ARMCPRegInfo *ri,
static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *r=
i,
uint64_t value)
{
- ARMCPU *cpu =3D env_archcpu(env);
- CPUState *cs =3D CPU(cpu);
- bool sec =3D arm_is_secure_below_el3(env);
+ CPUState *cs =3D env_cpu(env);
+ int mask =3D vae1_tlbmask(env);
uint64_t pageaddr =3D sextract64(value << 12, 0, 56);
=20
- if (sec) {
- tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
- ARMMMUIdxBit_S1SE1 |
- ARMMMUIdxBit_S1SE0);
- } else {
- tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
- ARMMMUIdxBit_S12NSE1 |
- ARMMMUIdxBit_S12NSE0);
- }
+ tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, mask);
}
=20
static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -4116,8 +4086,8 @@ static void tlbi_aa64_vae1_write(CPUARMState *env, co=
nst ARMCPRegInfo *ri,
* since we don't support flush-for-specific-ASID-only or
* flush-last-level-only.
*/
- ARMCPU *cpu =3D env_archcpu(env);
- CPUState *cs =3D CPU(cpu);
+ CPUState *cs =3D env_cpu(env);
+ int mask =3D vae1_tlbmask(env);
uint64_t pageaddr =3D sextract64(value << 12, 0, 56);
=20
if (tlb_force_broadcast(env)) {
@@ -4125,15 +4095,7 @@ static void tlbi_aa64_vae1_write(CPUARMState *env, c=
onst ARMCPRegInfo *ri,
return;
}
=20
- if (arm_is_secure_below_el3(env)) {
- tlb_flush_page_by_mmuidx(cs, pageaddr,
- ARMMMUIdxBit_S1SE1 |
- ARMMMUIdxBit_S1SE0);
- } else {
- tlb_flush_page_by_mmuidx(cs, pageaddr,
- ARMMMUIdxBit_S12NSE1 |
- ARMMMUIdxBit_S12NSE0);
- }
+ tlb_flush_page_by_mmuidx(cs, pageaddr, mask);
}
=20
static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *r=
i,
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 09/48] target/arm: Simplify tlb_force_broadcast alternatives
Date: Fri, 7 Feb 2020 14:33:04 +0000
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From: Richard Henderson <richard.henderson@linaro.org>
Rather than call to a separate function and re-compute any
parameters for the flush, simply use the correct flush
function directly.
Tested-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Reviewed-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200206105448.4726-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 52 +++++++++++++++++++++------------------------
1 file changed, 24 insertions(+), 28 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 49da685b296..bf69935550f 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -614,56 +614,54 @@ static void tlbiall_write(CPUARMState *env, const ARM=
CPRegInfo *ri,
uint64_t value)
{
/* Invalidate all (TLBIALL) */
- ARMCPU *cpu =3D env_archcpu(env);
+ CPUState *cs =3D env_cpu(env);
=20
if (tlb_force_broadcast(env)) {
- tlbiall_is_write(env, NULL, value);
- return;
+ tlb_flush_all_cpus_synced(cs);
+ } else {
+ tlb_flush(cs);
}
-
- tlb_flush(CPU(cpu));
}
=20
static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
/* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
- ARMCPU *cpu =3D env_archcpu(env);
+ CPUState *cs =3D env_cpu(env);
=20
+ value &=3D TARGET_PAGE_MASK;
if (tlb_force_broadcast(env)) {
- tlbimva_is_write(env, NULL, value);
- return;
+ tlb_flush_page_all_cpus_synced(cs, value);
+ } else {
+ tlb_flush_page(cs, value);
}
-
- tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
}
=20
static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
/* Invalidate by ASID (TLBIASID) */
- ARMCPU *cpu =3D env_archcpu(env);
+ CPUState *cs =3D env_cpu(env);
=20
if (tlb_force_broadcast(env)) {
- tlbiasid_is_write(env, NULL, value);
- return;
+ tlb_flush_all_cpus_synced(cs);
+ } else {
+ tlb_flush(cs);
}
-
- tlb_flush(CPU(cpu));
}
=20
static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
/* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
- ARMCPU *cpu =3D env_archcpu(env);
+ CPUState *cs =3D env_cpu(env);
=20
+ value &=3D TARGET_PAGE_MASK;
if (tlb_force_broadcast(env)) {
- tlbimvaa_is_write(env, NULL, value);
- return;
+ tlb_flush_page_all_cpus_synced(cs, value);
+ } else {
+ tlb_flush_page(cs, value);
}
-
- tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
}
=20
static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -3965,11 +3963,10 @@ static void tlbi_aa64_vmalle1_write(CPUARMState *en=
v, const ARMCPRegInfo *ri,
int mask =3D vae1_tlbmask(env);
=20
if (tlb_force_broadcast(env)) {
- tlbi_aa64_vmalle1is_write(env, NULL, value);
- return;
+ tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);
+ } else {
+ tlb_flush_by_mmuidx(cs, mask);
}
-
- tlb_flush_by_mmuidx(cs, mask);
}
=20
static int alle1_tlbmask(CPUARMState *env)
@@ -4091,11 +4088,10 @@ static void tlbi_aa64_vae1_write(CPUARMState *env, =
const ARMCPRegInfo *ri,
uint64_t pageaddr =3D sextract64(value << 12, 0, 56);
=20
if (tlb_force_broadcast(env)) {
- tlbi_aa64_vae1is_write(env, NULL, value);
- return;
+ tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, mask);
+ } else {
+ tlb_flush_page_by_mmuidx(cs, pageaddr, mask);
}
-
- tlb_flush_page_by_mmuidx(cs, pageaddr, mask);
}
=20
static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *r=
i,
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 10/48] target/arm: Rename ARMMMUIdx*_S12NSE* to
ARMMMUIdx*_E10_*
Date: Fri, 7 Feb 2020 14:33:05 +0000
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From: Richard Henderson <richard.henderson@linaro.org>
This is part of a reorganization to the set of mmu_idx.
This emphasizes that they apply to the EL1&0 regime.
The ultimate goal is
-- Non-secure regimes:
ARMMMUIdx_E10_0,
ARMMMUIdx_E20_0,
ARMMMUIdx_E10_1,
ARMMMUIdx_E2,
ARMMMUIdx_E20_2,
-- Secure regimes:
ARMMMUIdx_SE10_0,
ARMMMUIdx_SE10_1,
ARMMMUIdx_SE3,
-- Helper mmu_idx for non-secure EL1&0 stage1 and stage2
ARMMMUIdx_Stage2,
ARMMMUIdx_Stage1_E0,
ARMMMUIdx_Stage1_E1,
The 'S' prefix is reserved for "Secure". Unless otherwise specified,
each mmu_idx represents all stages of translation.
Tested-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Reviewed-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200206105448.4726-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 8 ++++----
target/arm/internals.h | 4 ++--
target/arm/helper.c | 40 +++++++++++++++++++-------------------
target/arm/translate-a64.c | 4 ++--
target/arm/translate.c | 6 +++---
5 files changed, 31 insertions(+), 31 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 0e68704a908..272104afbb9 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -2905,8 +2905,8 @@ static inline bool arm_excp_unmasked(CPUState *cs, un=
signed int excp_idx,
#define ARM_MMU_IDX_COREIDX_MASK 0x7
=20
typedef enum ARMMMUIdx {
- ARMMMUIdx_S12NSE0 =3D 0 | ARM_MMU_IDX_A,
- ARMMMUIdx_S12NSE1 =3D 1 | ARM_MMU_IDX_A,
+ ARMMMUIdx_E10_0 =3D 0 | ARM_MMU_IDX_A,
+ ARMMMUIdx_E10_1 =3D 1 | ARM_MMU_IDX_A,
ARMMMUIdx_S1E2 =3D 2 | ARM_MMU_IDX_A,
ARMMMUIdx_S1E3 =3D 3 | ARM_MMU_IDX_A,
ARMMMUIdx_S1SE0 =3D 4 | ARM_MMU_IDX_A,
@@ -2931,8 +2931,8 @@ typedef enum ARMMMUIdx {
* for use when calling tlb_flush_by_mmuidx() and friends.
*/
typedef enum ARMMMUIdxBit {
- ARMMMUIdxBit_S12NSE0 =3D 1 << 0,
- ARMMMUIdxBit_S12NSE1 =3D 1 << 1,
+ ARMMMUIdxBit_E10_0 =3D 1 << 0,
+ ARMMMUIdxBit_E10_1 =3D 1 << 1,
ARMMMUIdxBit_S1E2 =3D 1 << 2,
ARMMMUIdxBit_S1E3 =3D 1 << 3,
ARMMMUIdxBit_S1SE0 =3D 1 << 4,
diff --git a/target/arm/internals.h b/target/arm/internals.h
index f5313dd3d42..d4ea6cfe9d1 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -808,8 +808,8 @@ static inline void arm_call_el_change_hook(ARMCPU *cpu)
static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx)
{
switch (mmu_idx) {
- case ARMMMUIdx_S12NSE0:
- case ARMMMUIdx_S12NSE1:
+ case ARMMMUIdx_E10_0:
+ case ARMMMUIdx_E10_1:
case ARMMMUIdx_S1NSE0:
case ARMMMUIdx_S1NSE1:
case ARMMMUIdx_S1E2:
diff --git a/target/arm/helper.c b/target/arm/helper.c
index bf69935550f..95b67ba6c5f 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -670,8 +670,8 @@ static void tlbiall_nsnh_write(CPUARMState *env, const =
ARMCPRegInfo *ri,
CPUState *cs =3D env_cpu(env);
=20
tlb_flush_by_mmuidx(cs,
- ARMMMUIdxBit_S12NSE1 |
- ARMMMUIdxBit_S12NSE0 |
+ ARMMMUIdxBit_E10_1 |
+ ARMMMUIdxBit_E10_0 |
ARMMMUIdxBit_S2NS);
}
=20
@@ -681,8 +681,8 @@ static void tlbiall_nsnh_is_write(CPUARMState *env, con=
st ARMCPRegInfo *ri,
CPUState *cs =3D env_cpu(env);
=20
tlb_flush_by_mmuidx_all_cpus_synced(cs,
- ARMMMUIdxBit_S12NSE1 |
- ARMMMUIdxBit_S12NSE0 |
+ ARMMMUIdxBit_E10_1 |
+ ARMMMUIdxBit_E10_0 |
ARMMMUIdxBit_S2NS);
}
=20
@@ -3117,7 +3117,7 @@ static uint64_t do_ats_write(CPUARMState *env, uint64=
_t value,
format64 =3D arm_s1_regime_using_lpae_format(env, mmu_idx);
=20
if (arm_feature(env, ARM_FEATURE_EL2)) {
- if (mmu_idx =3D=3D ARMMMUIdx_S12NSE0 || mmu_idx =3D=3D ARMMMUI=
dx_S12NSE1) {
+ if (mmu_idx =3D=3D ARMMMUIdx_E10_0 || mmu_idx =3D=3D ARMMMUIdx=
_E10_1) {
format64 |=3D env->cp15.hcr_el2 & (HCR_VM | HCR_DC);
} else {
format64 |=3D arm_current_el(env) =3D=3D 2;
@@ -3216,11 +3216,11 @@ static void ats_write(CPUARMState *env, const ARMCP=
RegInfo *ri, uint64_t value)
break;
case 4:
/* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
- mmu_idx =3D ARMMMUIdx_S12NSE1;
+ mmu_idx =3D ARMMMUIdx_E10_1;
break;
case 6:
/* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
- mmu_idx =3D ARMMMUIdx_S12NSE0;
+ mmu_idx =3D ARMMMUIdx_E10_0;
break;
default:
g_assert_not_reached();
@@ -3278,10 +3278,10 @@ static void ats_write64(CPUARMState *env, const ARM=
CPRegInfo *ri,
mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0;
break;
case 4: /* AT S12E1R, AT S12E1W */
- mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S12NSE1;
+ mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_E10_1;
break;
case 6: /* AT S12E0R, AT S12E0W */
- mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S12NSE0;
+ mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_E10_0;
break;
default:
g_assert_not_reached();
@@ -3581,8 +3581,8 @@ static void vttbr_write(CPUARMState *env, const ARMCP=
RegInfo *ri,
/* Accesses to VTTBR may change the VMID so we must flush the TLB. */
if (raw_read(env, ri) !=3D value) {
tlb_flush_by_mmuidx(cs,
- ARMMMUIdxBit_S12NSE1 |
- ARMMMUIdxBit_S12NSE0 |
+ ARMMMUIdxBit_E10_1 |
+ ARMMMUIdxBit_E10_0 |
ARMMMUIdxBit_S2NS);
raw_write(env, ri, value);
}
@@ -3943,7 +3943,7 @@ static int vae1_tlbmask(CPUARMState *env)
if (arm_is_secure_below_el3(env)) {
return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0;
} else {
- return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0;
+ return ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_0;
}
}
=20
@@ -3979,9 +3979,9 @@ static int alle1_tlbmask(CPUARMState *env)
if (arm_is_secure_below_el3(env)) {
return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0;
} else if (arm_feature(env, ARM_FEATURE_EL2)) {
- return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0 | ARMMMUIdxBit_=
S2NS;
+ return ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_0 | ARMMMUIdxBit_S2NS;
} else {
- return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0;
+ return ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_0;
}
}
=20
@@ -8817,8 +8817,8 @@ static inline TCR *regime_tcr(CPUARMState *env, ARMMM=
UIdx mmu_idx)
*/
static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx)
{
- if (mmu_idx =3D=3D ARMMMUIdx_S12NSE0 || mmu_idx =3D=3D ARMMMUIdx_S12NS=
E1) {
- mmu_idx +=3D (ARMMMUIdx_S1NSE0 - ARMMMUIdx_S12NSE0);
+ if (mmu_idx =3D=3D ARMMMUIdx_E10_0 || mmu_idx =3D=3D ARMMMUIdx_E10_1) {
+ mmu_idx +=3D (ARMMMUIdx_S1NSE0 - ARMMMUIdx_E10_0);
}
return mmu_idx;
}
@@ -8861,8 +8861,8 @@ static inline bool regime_is_user(CPUARMState *env, A=
RMMMUIdx mmu_idx)
return true;
default:
return false;
- case ARMMMUIdx_S12NSE0:
- case ARMMMUIdx_S12NSE1:
+ case ARMMMUIdx_E10_0:
+ case ARMMMUIdx_E10_1:
g_assert_not_reached();
}
}
@@ -10766,7 +10766,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong a=
ddress,
target_ulong *page_size,
ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
{
- if (mmu_idx =3D=3D ARMMMUIdx_S12NSE0 || mmu_idx =3D=3D ARMMMUIdx_S12NS=
E1) {
+ if (mmu_idx =3D=3D ARMMMUIdx_E10_0 || mmu_idx =3D=3D ARMMMUIdx_E10_1) {
/* Call ourselves recursively to do the stage 1 and then stage 2
* translations.
*/
@@ -11294,7 +11294,7 @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el)
if (el < 2 && arm_is_secure_below_el3(env)) {
return ARMMMUIdx_S1SE0 + el;
} else {
- return ARMMMUIdx_S12NSE0 + el;
+ return ARMMMUIdx_E10_0 + el;
}
}
=20
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 766a03335bf..cb539b1eff0 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -113,8 +113,8 @@ static inline int get_a64_user_mem_index(DisasContext *=
s)
ARMMMUIdx useridx;
=20
switch (s->mmu_idx) {
- case ARMMMUIdx_S12NSE1:
- useridx =3D ARMMMUIdx_S12NSE0;
+ case ARMMMUIdx_E10_1:
+ useridx =3D ARMMMUIdx_E10_0;
break;
case ARMMMUIdx_S1SE1:
useridx =3D ARMMMUIdx_S1SE0;
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 2f4aea927f1..f90f22ef90d 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -153,9 +153,9 @@ static inline int get_a32_user_mem_index(DisasContext *=
s)
*/
switch (s->mmu_idx) {
case ARMMMUIdx_S1E2: /* this one is UNPREDICTABLE */
- case ARMMMUIdx_S12NSE0:
- case ARMMMUIdx_S12NSE1:
- return arm_to_core_mmu_idx(ARMMMUIdx_S12NSE0);
+ case ARMMMUIdx_E10_0:
+ case ARMMMUIdx_E10_1:
+ return arm_to_core_mmu_idx(ARMMMUIdx_E10_0);
case ARMMMUIdx_S1E3:
case ARMMMUIdx_S1SE0:
case ARMMMUIdx_S1SE1:
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 11/48] target/arm: Rename ARMMMUIdx_S2NS to ARMMMUIdx_Stage2
Date: Fri, 7 Feb 2020 14:33:06 +0000
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From: Richard Henderson <richard.henderson@linaro.org>
The EL1&0 regime is the only one that uses 2-stage translation.
Tested-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Reviewed-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200206105448.4726-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 4 +--
target/arm/internals.h | 2 +-
target/arm/helper.c | 57 ++++++++++++++++++++------------------
target/arm/translate-a64.c | 2 +-
target/arm/translate.c | 2 +-
5 files changed, 35 insertions(+), 32 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 272104afbb9..c6da3d3043a 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -2911,7 +2911,7 @@ typedef enum ARMMMUIdx {
ARMMMUIdx_S1E3 =3D 3 | ARM_MMU_IDX_A,
ARMMMUIdx_S1SE0 =3D 4 | ARM_MMU_IDX_A,
ARMMMUIdx_S1SE1 =3D 5 | ARM_MMU_IDX_A,
- ARMMMUIdx_S2NS =3D 6 | ARM_MMU_IDX_A,
+ ARMMMUIdx_Stage2 =3D 6 | ARM_MMU_IDX_A,
ARMMMUIdx_MUser =3D 0 | ARM_MMU_IDX_M,
ARMMMUIdx_MPriv =3D 1 | ARM_MMU_IDX_M,
ARMMMUIdx_MUserNegPri =3D 2 | ARM_MMU_IDX_M,
@@ -2937,7 +2937,7 @@ typedef enum ARMMMUIdxBit {
ARMMMUIdxBit_S1E3 =3D 1 << 3,
ARMMMUIdxBit_S1SE0 =3D 1 << 4,
ARMMMUIdxBit_S1SE1 =3D 1 << 5,
- ARMMMUIdxBit_S2NS =3D 1 << 6,
+ ARMMMUIdxBit_Stage2 =3D 1 << 6,
ARMMMUIdxBit_MUser =3D 1 << 0,
ARMMMUIdxBit_MPriv =3D 1 << 1,
ARMMMUIdxBit_MUserNegPri =3D 1 << 2,
diff --git a/target/arm/internals.h b/target/arm/internals.h
index d4ea6cfe9d1..1509e45e98a 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -813,7 +813,7 @@ static inline bool regime_is_secure(CPUARMState *env, A=
RMMMUIdx mmu_idx)
case ARMMMUIdx_S1NSE0:
case ARMMMUIdx_S1NSE1:
case ARMMMUIdx_S1E2:
- case ARMMMUIdx_S2NS:
+ case ARMMMUIdx_Stage2:
case ARMMMUIdx_MPrivNegPri:
case ARMMMUIdx_MUserNegPri:
case ARMMMUIdx_MPriv:
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 95b67ba6c5f..a6d4f449cc7 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -672,7 +672,7 @@ static void tlbiall_nsnh_write(CPUARMState *env, const =
ARMCPRegInfo *ri,
tlb_flush_by_mmuidx(cs,
ARMMMUIdxBit_E10_1 |
ARMMMUIdxBit_E10_0 |
- ARMMMUIdxBit_S2NS);
+ ARMMMUIdxBit_Stage2);
}
=20
static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -683,7 +683,7 @@ static void tlbiall_nsnh_is_write(CPUARMState *env, con=
st ARMCPRegInfo *ri,
tlb_flush_by_mmuidx_all_cpus_synced(cs,
ARMMMUIdxBit_E10_1 |
ARMMMUIdxBit_E10_0 |
- ARMMMUIdxBit_S2NS);
+ ARMMMUIdxBit_Stage2);
}
=20
static void tlbiipas2_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -704,7 +704,7 @@ static void tlbiipas2_write(CPUARMState *env, const ARM=
CPRegInfo *ri,
=20
pageaddr =3D sextract64(value << 12, 0, 40);
=20
- tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S2NS);
+ tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_Stage2);
}
=20
static void tlbiipas2_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -720,7 +720,7 @@ static void tlbiipas2_is_write(CPUARMState *env, const =
ARMCPRegInfo *ri,
pageaddr =3D sextract64(value << 12, 0, 40);
=20
tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
- ARMMMUIdxBit_S2NS);
+ ARMMMUIdxBit_Stage2);
}
=20
static void tlbiall_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -3578,12 +3578,15 @@ static void vttbr_write(CPUARMState *env, const ARM=
CPRegInfo *ri,
ARMCPU *cpu =3D env_archcpu(env);
CPUState *cs =3D CPU(cpu);
=20
- /* Accesses to VTTBR may change the VMID so we must flush the TLB. */
+ /*
+ * A change in VMID to the stage2 page table (Stage2) invalidates
+ * the combined stage 1&2 tlbs (EL10_1 and EL10_0).
+ */
if (raw_read(env, ri) !=3D value) {
tlb_flush_by_mmuidx(cs,
ARMMMUIdxBit_E10_1 |
ARMMMUIdxBit_E10_0 |
- ARMMMUIdxBit_S2NS);
+ ARMMMUIdxBit_Stage2);
raw_write(env, ri, value);
}
}
@@ -3979,7 +3982,7 @@ static int alle1_tlbmask(CPUARMState *env)
if (arm_is_secure_below_el3(env)) {
return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0;
} else if (arm_feature(env, ARM_FEATURE_EL2)) {
- return ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_0 | ARMMMUIdxBit_S2NS;
+ return ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_0 | ARMMMUIdxBit_Stag=
e2;
} else {
return ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_0;
}
@@ -4133,7 +4136,7 @@ static void tlbi_aa64_ipas2e1_write(CPUARMState *env,=
const ARMCPRegInfo *ri,
=20
pageaddr =3D sextract64(value << 12, 0, 48);
=20
- tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S2NS);
+ tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_Stage2);
}
=20
static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo=
*ri,
@@ -4149,7 +4152,7 @@ static void tlbi_aa64_ipas2e1is_write(CPUARMState *en=
v, const ARMCPRegInfo *ri,
pageaddr =3D sextract64(value << 12, 0, 48);
=20
tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
- ARMMMUIdxBit_S2NS);
+ ARMMMUIdxBit_Stage2);
}
=20
static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo=
*ri,
@@ -8706,7 +8709,7 @@ void arm_cpu_do_interrupt(CPUState *cs)
static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx)
{
switch (mmu_idx) {
- case ARMMMUIdx_S2NS:
+ case ARMMMUIdx_Stage2:
case ARMMMUIdx_S1E2:
return 2;
case ARMMMUIdx_S1E3:
@@ -8760,7 +8763,7 @@ static inline bool regime_translation_disabled(CPUARM=
State *env,
}
}
=20
- if (mmu_idx =3D=3D ARMMMUIdx_S2NS) {
+ if (mmu_idx =3D=3D ARMMMUIdx_Stage2) {
/* HCR.DC means HCR.VM behaves as 1 */
return (env->cp15.hcr_el2 & (HCR_DC | HCR_VM)) =3D=3D 0;
}
@@ -8791,7 +8794,7 @@ static inline bool regime_translation_big_endian(CPUA=
RMState *env,
static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx,
int ttbrn)
{
- if (mmu_idx =3D=3D ARMMMUIdx_S2NS) {
+ if (mmu_idx =3D=3D ARMMMUIdx_Stage2) {
return env->cp15.vttbr_el2;
}
if (ttbrn =3D=3D 0) {
@@ -8806,7 +8809,7 @@ static inline uint64_t regime_ttbr(CPUARMState *env, =
ARMMMUIdx mmu_idx,
/* Return the TCR controlling this translation regime */
static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx)
{
- if (mmu_idx =3D=3D ARMMMUIdx_S2NS) {
+ if (mmu_idx =3D=3D ARMMMUIdx_Stage2) {
return &env->cp15.vtcr_el2;
}
return &env->cp15.tcr_el[regime_el(env, mmu_idx)];
@@ -8993,7 +8996,7 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu=
_idx, bool is_aa64,
bool have_wxn;
int wxn =3D 0;
=20
- assert(mmu_idx !=3D ARMMMUIdx_S2NS);
+ assert(mmu_idx !=3D ARMMMUIdx_Stage2);
=20
user_rw =3D simple_ap_to_rw_prot_is_user(ap, true);
if (is_user) {
@@ -9085,7 +9088,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMM=
MUIdx mmu_idx,
ARMMMUFaultInfo *fi)
{
if ((mmu_idx =3D=3D ARMMMUIdx_S1NSE0 || mmu_idx =3D=3D ARMMMUIdx_S1NSE=
1) &&
- !regime_translation_disabled(env, ARMMMUIdx_S2NS)) {
+ !regime_translation_disabled(env, ARMMMUIdx_Stage2)) {
target_ulong s2size;
hwaddr s2pa;
int s2prot;
@@ -9102,7 +9105,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMM=
MUIdx mmu_idx,
pcacheattrs =3D &cacheattrs;
}
=20
- ret =3D get_phys_addr_lpae(env, addr, 0, ARMMMUIdx_S2NS, &s2pa,
+ ret =3D get_phys_addr_lpae(env, addr, 0, ARMMMUIdx_Stage2, &s2pa,
&txattrs, &s2prot, &s2size, fi, pcacheatt=
rs);
if (ret) {
assert(fi->type !=3D ARMFault_None);
@@ -9574,7 +9577,7 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *=
env, uint64_t va,
tsz =3D extract32(tcr, 0, 6);
using64k =3D extract32(tcr, 14, 1);
using16k =3D extract32(tcr, 15, 1);
- if (mmu_idx =3D=3D ARMMMUIdx_S2NS) {
+ if (mmu_idx =3D=3D ARMMMUIdx_Stage2) {
/* VTCR_EL2 */
tbi =3D tbid =3D hpd =3D false;
} else {
@@ -9635,7 +9638,7 @@ static ARMVAParameters aa32_va_parameters(CPUARMState=
*env, uint32_t va,
int select, tsz;
bool epd, hpd;
=20
- if (mmu_idx =3D=3D ARMMMUIdx_S2NS) {
+ if (mmu_idx =3D=3D ARMMMUIdx_Stage2) {
/* VTCR */
bool sext =3D extract32(tcr, 4, 1);
bool sign =3D extract32(tcr, 3, 1);
@@ -9737,7 +9740,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, targ=
et_ulong address,
level =3D 1;
/* There is no TTBR1 for EL2 */
ttbr1_valid =3D (el !=3D 2);
- addrsize =3D (mmu_idx =3D=3D ARMMMUIdx_S2NS ? 40 : 32);
+ addrsize =3D (mmu_idx =3D=3D ARMMMUIdx_Stage2 ? 40 : 32);
inputsize =3D addrsize - param.tsz;
}
=20
@@ -9788,7 +9791,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, targ=
et_ulong address,
goto do_fault;
}
=20
- if (mmu_idx !=3D ARMMMUIdx_S2NS) {
+ if (mmu_idx !=3D ARMMMUIdx_Stage2) {
/* The starting level depends on the virtual address size (which c=
an
* be up to 48 bits) and the translation granule size. It indicates
* the number of strides (stride bits at a time) needed to
@@ -9888,7 +9891,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, targ=
et_ulong address,
attrs =3D extract64(descriptor, 2, 10)
| (extract64(descriptor, 52, 12) << 10);
=20
- if (mmu_idx =3D=3D ARMMMUIdx_S2NS) {
+ if (mmu_idx =3D=3D ARMMMUIdx_Stage2) {
/* Stage 2 table descriptors do not include any attribute fiel=
ds */
break;
}
@@ -9919,7 +9922,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, targ=
et_ulong address,
ap =3D extract32(attrs, 4, 2);
xn =3D extract32(attrs, 12, 1);
=20
- if (mmu_idx =3D=3D ARMMMUIdx_S2NS) {
+ if (mmu_idx =3D=3D ARMMMUIdx_Stage2) {
ns =3D true;
*prot =3D get_S2prot(env, ap, xn);
} else {
@@ -9946,7 +9949,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, targ=
et_ulong address,
}
=20
if (cacheattrs !=3D NULL) {
- if (mmu_idx =3D=3D ARMMMUIdx_S2NS) {
+ if (mmu_idx =3D=3D ARMMMUIdx_Stage2) {
cacheattrs->attrs =3D convert_stage2_attrs(env,
extract32(attrs, 0, 4=
));
} else {
@@ -9967,7 +9970,7 @@ do_fault:
fi->type =3D fault_type;
fi->level =3D level;
/* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */
- fi->stage2 =3D fi->s1ptw || (mmu_idx =3D=3D ARMMMUIdx_S2NS);
+ fi->stage2 =3D fi->s1ptw || (mmu_idx =3D=3D ARMMMUIdx_Stage2);
return true;
}
=20
@@ -10781,13 +10784,13 @@ bool get_phys_addr(CPUARMState *env, target_ulong=
address,
prot, page_size, fi, cacheattrs);
=20
/* If S1 fails or S2 is disabled, return early. */
- if (ret || regime_translation_disabled(env, ARMMMUIdx_S2NS)) {
+ if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2))=
{
*phys_ptr =3D ipa;
return ret;
}
=20
/* S1 is done. Now do S2 translation. */
- ret =3D get_phys_addr_lpae(env, ipa, access_type, ARMMMUIdx_S2=
NS,
+ ret =3D get_phys_addr_lpae(env, ipa, access_type, ARMMMUIdx_St=
age2,
phys_ptr, attrs, &s2_prot,
page_size, fi,
cacheattrs !=3D NULL ? &cacheattrs2 :=
NULL);
@@ -10829,7 +10832,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong a=
ddress,
/* Fast Context Switch Extension. This doesn't exist at all in v8.
* In v7 and earlier it affects all stage 1 translations.
*/
- if (address < 0x02000000 && mmu_idx !=3D ARMMMUIdx_S2NS
+ if (address < 0x02000000 && mmu_idx !=3D ARMMMUIdx_Stage2
&& !arm_feature(env, ARM_FEATURE_V8)) {
if (regime_el(env, mmu_idx) =3D=3D 3) {
address +=3D env->cp15.fcseidr_s;
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index cb539b1eff0..d0d13e21754 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -119,7 +119,7 @@ static inline int get_a64_user_mem_index(DisasContext *=
s)
case ARMMMUIdx_S1SE1:
useridx =3D ARMMMUIdx_S1SE0;
break;
- case ARMMMUIdx_S2NS:
+ case ARMMMUIdx_Stage2:
g_assert_not_reached();
default:
useridx =3D s->mmu_idx;
diff --git a/target/arm/translate.c b/target/arm/translate.c
index f90f22ef90d..70b1fd3fe2a 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -172,7 +172,7 @@ static inline int get_a32_user_mem_index(DisasContext *=
s)
case ARMMMUIdx_MSUserNegPri:
case ARMMMUIdx_MSPrivNegPri:
return arm_to_core_mmu_idx(ARMMMUIdx_MSUserNegPri);
- case ARMMMUIdx_S2NS:
+ case ARMMMUIdx_Stage2:
default:
g_assert_not_reached();
}
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 12/48] target/arm: Rename ARMMMUIdx_S1NSE* to
ARMMMUIdx_Stage1_E*
Date: Fri, 7 Feb 2020 14:33:07 +0000
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From: Richard Henderson <richard.henderson@linaro.org>
This is part of a reorganization to the set of mmu_idx.
The EL1&0 regime is the only one that uses 2-stage translation.
Spelling out Stage avoids confusion with Secure.
Tested-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Reviewed-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200206105448.4726-12-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 4 ++--
target/arm/internals.h | 6 +++---
target/arm/helper.c | 27 ++++++++++++++-------------
3 files changed, 19 insertions(+), 18 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index c6da3d3043a..afc3e76ce50 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -2923,8 +2923,8 @@ typedef enum ARMMMUIdx {
/* Indexes below here don't have TLBs and are used only for AT system
* instructions or for the first stage of an S12 page table walk.
*/
- ARMMMUIdx_S1NSE0 =3D 0 | ARM_MMU_IDX_NOTLB,
- ARMMMUIdx_S1NSE1 =3D 1 | ARM_MMU_IDX_NOTLB,
+ ARMMMUIdx_Stage1_E0 =3D 0 | ARM_MMU_IDX_NOTLB,
+ ARMMMUIdx_Stage1_E1 =3D 1 | ARM_MMU_IDX_NOTLB,
} ARMMMUIdx;
=20
/* Bit macros for the core-mmu-index values for each index,
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 1509e45e98a..280b5b0c822 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -810,8 +810,8 @@ static inline bool regime_is_secure(CPUARMState *env, A=
RMMMUIdx mmu_idx)
switch (mmu_idx) {
case ARMMMUIdx_E10_0:
case ARMMMUIdx_E10_1:
- case ARMMMUIdx_S1NSE0:
- case ARMMMUIdx_S1NSE1:
+ case ARMMMUIdx_Stage1_E0:
+ case ARMMMUIdx_Stage1_E1:
case ARMMMUIdx_S1E2:
case ARMMMUIdx_Stage2:
case ARMMMUIdx_MPrivNegPri:
@@ -975,7 +975,7 @@ ARMMMUIdx arm_mmu_idx(CPUARMState *env);
#ifdef CONFIG_USER_ONLY
static inline ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env)
{
- return ARMMMUIdx_S1NSE0;
+ return ARMMMUIdx_Stage1_E0;
}
#else
ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env);
diff --git a/target/arm/helper.c b/target/arm/helper.c
index a6d4f449cc7..2d87c3a2e59 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -3041,7 +3041,8 @@ static uint64_t do_ats_write(CPUARMState *env, uint64=
_t value,
bool take_exc =3D false;
=20
if (fi.s1ptw && current_el =3D=3D 1 && !arm_is_secure(env)
- && (mmu_idx =3D=3D ARMMMUIdx_S1NSE1 || mmu_idx =3D=3D ARMMMUId=
x_S1NSE0)) {
+ && (mmu_idx =3D=3D ARMMMUIdx_Stage1_E1 ||
+ mmu_idx =3D=3D ARMMMUIdx_Stage1_E0)) {
/*
* Synchronous stage 2 fault on an access made as part of the
* translation table walk for AT S1E0* or AT S1E1* insn
@@ -3189,10 +3190,10 @@ static void ats_write(CPUARMState *env, const ARMCP=
RegInfo *ri, uint64_t value)
mmu_idx =3D ARMMMUIdx_S1E3;
break;
case 2:
- mmu_idx =3D ARMMMUIdx_S1NSE1;
+ mmu_idx =3D ARMMMUIdx_Stage1_E1;
break;
case 1:
- mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1;
+ mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_Stage1_E1;
break;
default:
g_assert_not_reached();
@@ -3205,10 +3206,10 @@ static void ats_write(CPUARMState *env, const ARMCP=
RegInfo *ri, uint64_t value)
mmu_idx =3D ARMMMUIdx_S1SE0;
break;
case 2:
- mmu_idx =3D ARMMMUIdx_S1NSE0;
+ mmu_idx =3D ARMMMUIdx_Stage1_E0;
break;
case 1:
- mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0;
+ mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_Stage1_E0;
break;
default:
g_assert_not_reached();
@@ -3262,7 +3263,7 @@ static void ats_write64(CPUARMState *env, const ARMCP=
RegInfo *ri,
case 0:
switch (ri->opc1) {
case 0: /* AT S1E1R, AT S1E1W */
- mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1;
+ mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_Stage1_E1;
break;
case 4: /* AT S1E2R, AT S1E2W */
mmu_idx =3D ARMMMUIdx_S1E2;
@@ -3275,7 +3276,7 @@ static void ats_write64(CPUARMState *env, const ARMCP=
RegInfo *ri,
}
break;
case 2: /* AT S1E0R, AT S1E0W */
- mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0;
+ mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_Stage1_E0;
break;
case 4: /* AT S12E1R, AT S12E1W */
mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_E10_1;
@@ -8717,8 +8718,8 @@ static inline uint32_t regime_el(CPUARMState *env, AR=
MMMUIdx mmu_idx)
case ARMMMUIdx_S1SE0:
return arm_el_is_aa64(env, 3) ? 1 : 3;
case ARMMMUIdx_S1SE1:
- case ARMMMUIdx_S1NSE0:
- case ARMMMUIdx_S1NSE1:
+ case ARMMMUIdx_Stage1_E0:
+ case ARMMMUIdx_Stage1_E1:
case ARMMMUIdx_MPrivNegPri:
case ARMMMUIdx_MUserNegPri:
case ARMMMUIdx_MPriv:
@@ -8776,7 +8777,7 @@ static inline bool regime_translation_disabled(CPUARM=
State *env,
}
=20
if ((env->cp15.hcr_el2 & HCR_DC) &&
- (mmu_idx =3D=3D ARMMMUIdx_S1NSE0 || mmu_idx =3D=3D ARMMMUIdx_S1NSE=
1)) {
+ (mmu_idx =3D=3D ARMMMUIdx_Stage1_E0 || mmu_idx =3D=3D ARMMMUIdx_St=
age1_E1)) {
/* HCR.DC means SCTLR_EL1.M behaves as 0 */
return true;
}
@@ -8821,7 +8822,7 @@ static inline TCR *regime_tcr(CPUARMState *env, ARMMM=
UIdx mmu_idx)
static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx)
{
if (mmu_idx =3D=3D ARMMMUIdx_E10_0 || mmu_idx =3D=3D ARMMMUIdx_E10_1) {
- mmu_idx +=3D (ARMMMUIdx_S1NSE0 - ARMMMUIdx_E10_0);
+ mmu_idx +=3D (ARMMMUIdx_Stage1_E0 - ARMMMUIdx_E10_0);
}
return mmu_idx;
}
@@ -8856,7 +8857,7 @@ static inline bool regime_is_user(CPUARMState *env, A=
RMMMUIdx mmu_idx)
{
switch (mmu_idx) {
case ARMMMUIdx_S1SE0:
- case ARMMMUIdx_S1NSE0:
+ case ARMMMUIdx_Stage1_E0:
case ARMMMUIdx_MUser:
case ARMMMUIdx_MSUser:
case ARMMMUIdx_MUserNegPri:
@@ -9087,7 +9088,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMM=
MUIdx mmu_idx,
hwaddr addr, MemTxAttrs txattrs,
ARMMMUFaultInfo *fi)
{
- if ((mmu_idx =3D=3D ARMMMUIdx_S1NSE0 || mmu_idx =3D=3D ARMMMUIdx_S1NSE=
1) &&
+ if ((mmu_idx =3D=3D ARMMMUIdx_Stage1_E0 || mmu_idx =3D=3D ARMMMUIdx_St=
age1_E1) &&
!regime_translation_disabled(env, ARMMMUIdx_Stage2)) {
target_ulong s2size;
hwaddr s2pa;
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 13/48] target/arm: Rename ARMMMUIdx_S1SE[01] to
ARMMMUIdx_SE10_[01]
Date: Fri, 7 Feb 2020 14:33:08 +0000
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From: Richard Henderson <richard.henderson@linaro.org>
This is part of a reorganization to the set of mmu_idx.
This emphasizes that they apply to the Secure EL1&0 regime.
Tested-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Reviewed-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200206105448.4726-13-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 8 ++++----
target/arm/internals.h | 4 ++--
target/arm/translate.h | 2 +-
target/arm/helper.c | 26 +++++++++++++-------------
target/arm/translate-a64.c | 4 ++--
target/arm/translate.c | 6 +++---
6 files changed, 25 insertions(+), 25 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index afc3e76ce50..6cf2b3d6fd7 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -2909,8 +2909,8 @@ typedef enum ARMMMUIdx {
ARMMMUIdx_E10_1 =3D 1 | ARM_MMU_IDX_A,
ARMMMUIdx_S1E2 =3D 2 | ARM_MMU_IDX_A,
ARMMMUIdx_S1E3 =3D 3 | ARM_MMU_IDX_A,
- ARMMMUIdx_S1SE0 =3D 4 | ARM_MMU_IDX_A,
- ARMMMUIdx_S1SE1 =3D 5 | ARM_MMU_IDX_A,
+ ARMMMUIdx_SE10_0 =3D 4 | ARM_MMU_IDX_A,
+ ARMMMUIdx_SE10_1 =3D 5 | ARM_MMU_IDX_A,
ARMMMUIdx_Stage2 =3D 6 | ARM_MMU_IDX_A,
ARMMMUIdx_MUser =3D 0 | ARM_MMU_IDX_M,
ARMMMUIdx_MPriv =3D 1 | ARM_MMU_IDX_M,
@@ -2935,8 +2935,8 @@ typedef enum ARMMMUIdxBit {
ARMMMUIdxBit_E10_1 =3D 1 << 1,
ARMMMUIdxBit_S1E2 =3D 1 << 2,
ARMMMUIdxBit_S1E3 =3D 1 << 3,
- ARMMMUIdxBit_S1SE0 =3D 1 << 4,
- ARMMMUIdxBit_S1SE1 =3D 1 << 5,
+ ARMMMUIdxBit_SE10_0 =3D 1 << 4,
+ ARMMMUIdxBit_SE10_1 =3D 1 << 5,
ARMMMUIdxBit_Stage2 =3D 1 << 6,
ARMMMUIdxBit_MUser =3D 1 << 0,
ARMMMUIdxBit_MPriv =3D 1 << 1,
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 280b5b0c822..eafcd326e11 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -820,8 +820,8 @@ static inline bool regime_is_secure(CPUARMState *env, A=
RMMMUIdx mmu_idx)
case ARMMMUIdx_MUser:
return false;
case ARMMMUIdx_S1E3:
- case ARMMMUIdx_S1SE0:
- case ARMMMUIdx_S1SE1:
+ case ARMMMUIdx_SE10_0:
+ case ARMMMUIdx_SE10_1:
case ARMMMUIdx_MSPrivNegPri:
case ARMMMUIdx_MSUserNegPri:
case ARMMMUIdx_MSPriv:
diff --git a/target/arm/translate.h b/target/arm/translate.h
index b837b7fcbf1..a32b6b1b3a9 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -126,7 +126,7 @@ static inline int default_exception_el(DisasContext *s)
* exceptions can only be routed to ELs above 1, so we target the high=
er of
* 1 or the current EL.
*/
- return (s->mmu_idx =3D=3D ARMMMUIdx_S1SE0 && s->secure_routed_to_el3)
+ return (s->mmu_idx =3D=3D ARMMMUIdx_SE10_0 && s->secure_routed_to_el3)
? 3 : MAX(1, s->current_el);
}
=20
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 2d87c3a2e59..bbceb7a38ed 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -3193,7 +3193,7 @@ static void ats_write(CPUARMState *env, const ARMCPRe=
gInfo *ri, uint64_t value)
mmu_idx =3D ARMMMUIdx_Stage1_E1;
break;
case 1:
- mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_Stage1_E1;
+ mmu_idx =3D secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_Stage1_E1;
break;
default:
g_assert_not_reached();
@@ -3203,13 +3203,13 @@ static void ats_write(CPUARMState *env, const ARMCP=
RegInfo *ri, uint64_t value)
/* stage 1 current state PL0: ATS1CUR, ATS1CUW */
switch (el) {
case 3:
- mmu_idx =3D ARMMMUIdx_S1SE0;
+ mmu_idx =3D ARMMMUIdx_SE10_0;
break;
case 2:
mmu_idx =3D ARMMMUIdx_Stage1_E0;
break;
case 1:
- mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_Stage1_E0;
+ mmu_idx =3D secure ? ARMMMUIdx_SE10_0 : ARMMMUIdx_Stage1_E0;
break;
default:
g_assert_not_reached();
@@ -3263,7 +3263,7 @@ static void ats_write64(CPUARMState *env, const ARMCP=
RegInfo *ri,
case 0:
switch (ri->opc1) {
case 0: /* AT S1E1R, AT S1E1W */
- mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_Stage1_E1;
+ mmu_idx =3D secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_Stage1_E1;
break;
case 4: /* AT S1E2R, AT S1E2W */
mmu_idx =3D ARMMMUIdx_S1E2;
@@ -3276,13 +3276,13 @@ static void ats_write64(CPUARMState *env, const ARM=
CPRegInfo *ri,
}
break;
case 2: /* AT S1E0R, AT S1E0W */
- mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_Stage1_E0;
+ mmu_idx =3D secure ? ARMMMUIdx_SE10_0 : ARMMMUIdx_Stage1_E0;
break;
case 4: /* AT S12E1R, AT S12E1W */
- mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_E10_1;
+ mmu_idx =3D secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_E10_1;
break;
case 6: /* AT S12E0R, AT S12E0W */
- mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_E10_0;
+ mmu_idx =3D secure ? ARMMMUIdx_SE10_0 : ARMMMUIdx_E10_0;
break;
default:
g_assert_not_reached();
@@ -3945,7 +3945,7 @@ static CPAccessResult aa64_cacheop_access(CPUARMState=
*env,
static int vae1_tlbmask(CPUARMState *env)
{
if (arm_is_secure_below_el3(env)) {
- return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0;
+ return ARMMMUIdxBit_SE10_1 | ARMMMUIdxBit_SE10_0;
} else {
return ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_0;
}
@@ -3981,7 +3981,7 @@ static int alle1_tlbmask(CPUARMState *env)
* stage 1 translations.
*/
if (arm_is_secure_below_el3(env)) {
- return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0;
+ return ARMMMUIdxBit_SE10_1 | ARMMMUIdxBit_SE10_0;
} else if (arm_feature(env, ARM_FEATURE_EL2)) {
return ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_0 | ARMMMUIdxBit_Stag=
e2;
} else {
@@ -8715,9 +8715,9 @@ static inline uint32_t regime_el(CPUARMState *env, AR=
MMMUIdx mmu_idx)
return 2;
case ARMMMUIdx_S1E3:
return 3;
- case ARMMMUIdx_S1SE0:
+ case ARMMMUIdx_SE10_0:
return arm_el_is_aa64(env, 3) ? 1 : 3;
- case ARMMMUIdx_S1SE1:
+ case ARMMMUIdx_SE10_1:
case ARMMMUIdx_Stage1_E0:
case ARMMMUIdx_Stage1_E1:
case ARMMMUIdx_MPrivNegPri:
@@ -8856,7 +8856,7 @@ bool arm_s1_regime_using_lpae_format(CPUARMState *env=
, ARMMMUIdx mmu_idx)
static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx)
{
switch (mmu_idx) {
- case ARMMMUIdx_S1SE0:
+ case ARMMMUIdx_SE10_0:
case ARMMMUIdx_Stage1_E0:
case ARMMMUIdx_MUser:
case ARMMMUIdx_MSUser:
@@ -11296,7 +11296,7 @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el)
}
=20
if (el < 2 && arm_is_secure_below_el3(env)) {
- return ARMMMUIdx_S1SE0 + el;
+ return ARMMMUIdx_SE10_0 + el;
} else {
return ARMMMUIdx_E10_0 + el;
}
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index d0d13e21754..fcfb96ce1fb 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -116,8 +116,8 @@ static inline int get_a64_user_mem_index(DisasContext *=
s)
case ARMMMUIdx_E10_1:
useridx =3D ARMMMUIdx_E10_0;
break;
- case ARMMMUIdx_S1SE1:
- useridx =3D ARMMMUIdx_S1SE0;
+ case ARMMMUIdx_SE10_1:
+ useridx =3D ARMMMUIdx_SE10_0;
break;
case ARMMMUIdx_Stage2:
g_assert_not_reached();
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 70b1fd3fe2a..a2019a9b2a9 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -157,9 +157,9 @@ static inline int get_a32_user_mem_index(DisasContext *=
s)
case ARMMMUIdx_E10_1:
return arm_to_core_mmu_idx(ARMMMUIdx_E10_0);
case ARMMMUIdx_S1E3:
- case ARMMMUIdx_S1SE0:
- case ARMMMUIdx_S1SE1:
- return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0);
+ case ARMMMUIdx_SE10_0:
+ case ARMMMUIdx_SE10_1:
+ return arm_to_core_mmu_idx(ARMMMUIdx_SE10_0);
case ARMMMUIdx_MUser:
case ARMMMUIdx_MPriv:
return arm_to_core_mmu_idx(ARMMMUIdx_MUser);
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 14/48] target/arm: Rename ARMMMUIdx*_S1E3 to ARMMMUIdx*_SE3
Date: Fri, 7 Feb 2020 14:33:09 +0000
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From: Richard Henderson <richard.henderson@linaro.org>
This is part of a reorganization to the set of mmu_idx.
The EL3 regime only has a single stage translation, and
is always secure.
Tested-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Reviewed-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200206105448.4726-14-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 4 ++--
target/arm/internals.h | 2 +-
target/arm/helper.c | 14 +++++++-------
target/arm/translate.c | 2 +-
4 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 6cf2b3d6fd7..9f01ec8dd24 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -2908,7 +2908,7 @@ typedef enum ARMMMUIdx {
ARMMMUIdx_E10_0 =3D 0 | ARM_MMU_IDX_A,
ARMMMUIdx_E10_1 =3D 1 | ARM_MMU_IDX_A,
ARMMMUIdx_S1E2 =3D 2 | ARM_MMU_IDX_A,
- ARMMMUIdx_S1E3 =3D 3 | ARM_MMU_IDX_A,
+ ARMMMUIdx_SE3 =3D 3 | ARM_MMU_IDX_A,
ARMMMUIdx_SE10_0 =3D 4 | ARM_MMU_IDX_A,
ARMMMUIdx_SE10_1 =3D 5 | ARM_MMU_IDX_A,
ARMMMUIdx_Stage2 =3D 6 | ARM_MMU_IDX_A,
@@ -2934,7 +2934,7 @@ typedef enum ARMMMUIdxBit {
ARMMMUIdxBit_E10_0 =3D 1 << 0,
ARMMMUIdxBit_E10_1 =3D 1 << 1,
ARMMMUIdxBit_S1E2 =3D 1 << 2,
- ARMMMUIdxBit_S1E3 =3D 1 << 3,
+ ARMMMUIdxBit_SE3 =3D 1 << 3,
ARMMMUIdxBit_SE10_0 =3D 1 << 4,
ARMMMUIdxBit_SE10_1 =3D 1 << 5,
ARMMMUIdxBit_Stage2 =3D 1 << 6,
diff --git a/target/arm/internals.h b/target/arm/internals.h
index eafcd326e11..d8730fbbad3 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -819,7 +819,7 @@ static inline bool regime_is_secure(CPUARMState *env, A=
RMMMUIdx mmu_idx)
case ARMMMUIdx_MPriv:
case ARMMMUIdx_MUser:
return false;
- case ARMMMUIdx_S1E3:
+ case ARMMMUIdx_SE3:
case ARMMMUIdx_SE10_0:
case ARMMMUIdx_SE10_1:
case ARMMMUIdx_MSPrivNegPri:
diff --git a/target/arm/helper.c b/target/arm/helper.c
index bbceb7a38ed..f5d97da1c48 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -3187,7 +3187,7 @@ static void ats_write(CPUARMState *env, const ARMCPRe=
gInfo *ri, uint64_t value)
/* stage 1 current state PL1: ATS1CPR, ATS1CPW */
switch (el) {
case 3:
- mmu_idx =3D ARMMMUIdx_S1E3;
+ mmu_idx =3D ARMMMUIdx_SE3;
break;
case 2:
mmu_idx =3D ARMMMUIdx_Stage1_E1;
@@ -3269,7 +3269,7 @@ static void ats_write64(CPUARMState *env, const ARMCP=
RegInfo *ri,
mmu_idx =3D ARMMMUIdx_S1E2;
break;
case 6: /* AT S1E3R, AT S1E3W */
- mmu_idx =3D ARMMMUIdx_S1E3;
+ mmu_idx =3D ARMMMUIdx_SE3;
break;
default:
g_assert_not_reached();
@@ -4013,7 +4013,7 @@ static void tlbi_aa64_alle3_write(CPUARMState *env, c=
onst ARMCPRegInfo *ri,
ARMCPU *cpu =3D env_archcpu(env);
CPUState *cs =3D CPU(cpu);
=20
- tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E3);
+ tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_SE3);
}
=20
static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *=
ri,
@@ -4038,7 +4038,7 @@ static void tlbi_aa64_alle3is_write(CPUARMState *env,=
const ARMCPRegInfo *ri,
{
CPUState *cs =3D env_cpu(env);
=20
- tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E3);
+ tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_SE3);
}
=20
static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -4066,7 +4066,7 @@ static void tlbi_aa64_vae3_write(CPUARMState *env, co=
nst ARMCPRegInfo *ri,
CPUState *cs =3D CPU(cpu);
uint64_t pageaddr =3D sextract64(value << 12, 0, 56);
=20
- tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E3);
+ tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_SE3);
}
=20
static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *r=
i,
@@ -4115,7 +4115,7 @@ static void tlbi_aa64_vae3is_write(CPUARMState *env, =
const ARMCPRegInfo *ri,
uint64_t pageaddr =3D sextract64(value << 12, 0, 56);
=20
tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
- ARMMMUIdxBit_S1E3);
+ ARMMMUIdxBit_SE3);
}
=20
static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *=
ri,
@@ -8713,7 +8713,7 @@ static inline uint32_t regime_el(CPUARMState *env, AR=
MMMUIdx mmu_idx)
case ARMMMUIdx_Stage2:
case ARMMMUIdx_S1E2:
return 2;
- case ARMMMUIdx_S1E3:
+ case ARMMMUIdx_SE3:
return 3;
case ARMMMUIdx_SE10_0:
return arm_el_is_aa64(env, 3) ? 1 : 3;
diff --git a/target/arm/translate.c b/target/arm/translate.c
index a2019a9b2a9..75afcb03fb4 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -156,7 +156,7 @@ static inline int get_a32_user_mem_index(DisasContext *=
s)
case ARMMMUIdx_E10_0:
case ARMMMUIdx_E10_1:
return arm_to_core_mmu_idx(ARMMMUIdx_E10_0);
- case ARMMMUIdx_S1E3:
+ case ARMMMUIdx_SE3:
case ARMMMUIdx_SE10_0:
case ARMMMUIdx_SE10_1:
return arm_to_core_mmu_idx(ARMMMUIdx_SE10_0);
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 15/48] target/arm: Rename ARMMMUIdx_S1E2 to ARMMMUIdx_E2
Date: Fri, 7 Feb 2020 14:33:10 +0000
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From: Richard Henderson <richard.henderson@linaro.org>
This is part of a reorganization to the set of mmu_idx.
The non-secure EL2 regime only has a single stage translation;
there is no point in pointing out that the idx is for stage1.
Tested-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Reviewed-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200206105448.4726-15-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 4 ++--
target/arm/internals.h | 2 +-
target/arm/helper.c | 22 +++++++++++-----------
target/arm/translate.c | 2 +-
4 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 9f01ec8dd24..a188398b03e 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -2907,7 +2907,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, un=
signed int excp_idx,
typedef enum ARMMMUIdx {
ARMMMUIdx_E10_0 =3D 0 | ARM_MMU_IDX_A,
ARMMMUIdx_E10_1 =3D 1 | ARM_MMU_IDX_A,
- ARMMMUIdx_S1E2 =3D 2 | ARM_MMU_IDX_A,
+ ARMMMUIdx_E2 =3D 2 | ARM_MMU_IDX_A,
ARMMMUIdx_SE3 =3D 3 | ARM_MMU_IDX_A,
ARMMMUIdx_SE10_0 =3D 4 | ARM_MMU_IDX_A,
ARMMMUIdx_SE10_1 =3D 5 | ARM_MMU_IDX_A,
@@ -2933,7 +2933,7 @@ typedef enum ARMMMUIdx {
typedef enum ARMMMUIdxBit {
ARMMMUIdxBit_E10_0 =3D 1 << 0,
ARMMMUIdxBit_E10_1 =3D 1 << 1,
- ARMMMUIdxBit_S1E2 =3D 1 << 2,
+ ARMMMUIdxBit_E2 =3D 1 << 2,
ARMMMUIdxBit_SE3 =3D 1 << 3,
ARMMMUIdxBit_SE10_0 =3D 1 << 4,
ARMMMUIdxBit_SE10_1 =3D 1 << 5,
diff --git a/target/arm/internals.h b/target/arm/internals.h
index d8730fbbad3..5b8b9c233fe 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -812,7 +812,7 @@ static inline bool regime_is_secure(CPUARMState *env, A=
RMMMUIdx mmu_idx)
case ARMMMUIdx_E10_1:
case ARMMMUIdx_Stage1_E0:
case ARMMMUIdx_Stage1_E1:
- case ARMMMUIdx_S1E2:
+ case ARMMMUIdx_E2:
case ARMMMUIdx_Stage2:
case ARMMMUIdx_MPrivNegPri:
case ARMMMUIdx_MUserNegPri:
diff --git a/target/arm/helper.c b/target/arm/helper.c
index f5d97da1c48..7ee41974566 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -728,7 +728,7 @@ static void tlbiall_hyp_write(CPUARMState *env, const A=
RMCPRegInfo *ri,
{
CPUState *cs =3D env_cpu(env);
=20
- tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E2);
+ tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E2);
}
=20
static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -736,7 +736,7 @@ static void tlbiall_hyp_is_write(CPUARMState *env, cons=
t ARMCPRegInfo *ri,
{
CPUState *cs =3D env_cpu(env);
=20
- tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E2);
+ tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E2);
}
=20
static void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -745,7 +745,7 @@ static void tlbimva_hyp_write(CPUARMState *env, const A=
RMCPRegInfo *ri,
CPUState *cs =3D env_cpu(env);
uint64_t pageaddr =3D value & ~MAKE_64BIT_MASK(0, 12);
=20
- tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E2);
+ tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E2);
}
=20
static void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -755,7 +755,7 @@ static void tlbimva_hyp_is_write(CPUARMState *env, cons=
t ARMCPRegInfo *ri,
uint64_t pageaddr =3D value & ~MAKE_64BIT_MASK(0, 12);
=20
tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
- ARMMMUIdxBit_S1E2);
+ ARMMMUIdxBit_E2);
}
=20
static const ARMCPRegInfo cp_reginfo[] =3D {
@@ -3238,7 +3238,7 @@ static void ats1h_write(CPUARMState *env, const ARMCP=
RegInfo *ri,
MMUAccessType access_type =3D ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA=
_LOAD;
uint64_t par64;
=20
- par64 =3D do_ats_write(env, value, access_type, ARMMMUIdx_S1E2);
+ par64 =3D do_ats_write(env, value, access_type, ARMMMUIdx_E2);
=20
A32_BANKED_CURRENT_REG_SET(env, par, par64);
}
@@ -3266,7 +3266,7 @@ static void ats_write64(CPUARMState *env, const ARMCP=
RegInfo *ri,
mmu_idx =3D secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_Stage1_E1;
break;
case 4: /* AT S1E2R, AT S1E2W */
- mmu_idx =3D ARMMMUIdx_S1E2;
+ mmu_idx =3D ARMMMUIdx_E2;
break;
case 6: /* AT S1E3R, AT S1E3W */
mmu_idx =3D ARMMMUIdx_SE3;
@@ -4004,7 +4004,7 @@ static void tlbi_aa64_alle2_write(CPUARMState *env, c=
onst ARMCPRegInfo *ri,
ARMCPU *cpu =3D env_archcpu(env);
CPUState *cs =3D CPU(cpu);
=20
- tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E2);
+ tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E2);
}
=20
static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -4030,7 +4030,7 @@ static void tlbi_aa64_alle2is_write(CPUARMState *env,=
const ARMCPRegInfo *ri,
{
CPUState *cs =3D env_cpu(env);
=20
- tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E2);
+ tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E2);
}
=20
static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *=
ri,
@@ -4052,7 +4052,7 @@ static void tlbi_aa64_vae2_write(CPUARMState *env, co=
nst ARMCPRegInfo *ri,
CPUState *cs =3D CPU(cpu);
uint64_t pageaddr =3D sextract64(value << 12, 0, 56);
=20
- tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E2);
+ tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E2);
}
=20
static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -4105,7 +4105,7 @@ static void tlbi_aa64_vae2is_write(CPUARMState *env, =
const ARMCPRegInfo *ri,
uint64_t pageaddr =3D sextract64(value << 12, 0, 56);
=20
tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
- ARMMMUIdxBit_S1E2);
+ ARMMMUIdxBit_E2);
}
=20
static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *r=
i,
@@ -8711,7 +8711,7 @@ static inline uint32_t regime_el(CPUARMState *env, AR=
MMMUIdx mmu_idx)
{
switch (mmu_idx) {
case ARMMMUIdx_Stage2:
- case ARMMMUIdx_S1E2:
+ case ARMMMUIdx_E2:
return 2;
case ARMMMUIdx_SE3:
return 3;
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 75afcb03fb4..91e2ca55154 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -152,7 +152,7 @@ static inline int get_a32_user_mem_index(DisasContext *=
s)
* otherwise, access as if at PL0.
*/
switch (s->mmu_idx) {
- case ARMMMUIdx_S1E2: /* this one is UNPREDICTABLE */
+ case ARMMMUIdx_E2: /* this one is UNPREDICTABLE */
case ARMMMUIdx_E10_0:
case ARMMMUIdx_E10_1:
return arm_to_core_mmu_idx(ARMMMUIdx_E10_0);
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 16/48] target/arm: Recover 4 bits from TBFLAGs
Date: Fri, 7 Feb 2020 14:33:11 +0000
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From: Richard Henderson <richard.henderson@linaro.org>
We had completely run out of TBFLAG bits.
Split A- and M-profile bits into two overlapping buckets.
This results in 4 free bits.
We used to initialize all of the a32 and m32 fields in DisasContext
by assignment, in arm_tr_init_disas_context. Now we only initialize
either the a32 or m32 by assignment, because the bits overlap in
tbflags. So zero the entire structure in gen_intermediate_code.
Tested-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Reviewed-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200206105448.4726-16-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 68 ++++++++++++++++++++++++++----------------
target/arm/helper.c | 17 +++++------
target/arm/translate.c | 57 +++++++++++++++++++----------------
3 files changed, 82 insertions(+), 60 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index a188398b03e..fce6a426c88 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3214,6 +3214,16 @@ typedef ARMCPU ArchCPU;
* We put flags which are shared between 32 and 64 bit mode at the top
* of the word, and flags which apply to only one mode at the bottom.
*
+ * 31 21 18 14 9 0
+ * +--------------+-----+-----+----------+--------------+
+ * | | | TBFLAG_A32 | |
+ * | | +-----+----------+ TBFLAG_AM32 |
+ * | TBFLAG_ANY | |TBFLAG_M32| |
+ * | | +-------------------------|
+ * | | | TBFLAG_A64 |
+ * +--------------+-----------+-------------------------+
+ * 31 21 14 0
+ *
* Unless otherwise noted, these bits are cached in env->hflags.
*/
FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1)
@@ -3223,46 +3233,54 @@ FIELD(TBFLAG_ANY, PSTATE_SS, 26, 1) /* Not cach=
ed. */
/* Target EL if we take a floating-point-disabled exception */
FIELD(TBFLAG_ANY, FPEXC_EL, 24, 2)
FIELD(TBFLAG_ANY, BE_DATA, 23, 1)
-/*
- * For A-profile only, target EL for debug exceptions.
- * Note that this overlaps with the M-profile-only HANDLER and STACKCHECK =
bits.
- */
+/* For A-profile only, target EL for debug exceptions. */
FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 21, 2)
=20
-/* Bit usage when in AArch32 state: */
-FIELD(TBFLAG_A32, THUMB, 0, 1) /* Not cached. */
-FIELD(TBFLAG_A32, VECLEN, 1, 3) /* Not cached. */
-FIELD(TBFLAG_A32, VECSTRIDE, 4, 2) /* Not cached. */
+/*
+ * Bit usage when in AArch32 state, both A- and M-profile.
+ */
+FIELD(TBFLAG_AM32, CONDEXEC, 0, 8) /* Not cached. */
+FIELD(TBFLAG_AM32, THUMB, 8, 1) /* Not cached. */
+
+/*
+ * Bit usage when in AArch32 state, for A-profile only.
+ */
+FIELD(TBFLAG_A32, VECLEN, 9, 3) /* Not cached. */
+FIELD(TBFLAG_A32, VECSTRIDE, 12, 2) /* Not cached. */
/*
* We store the bottom two bits of the CPAR as TB flags and handle
* checks on the other bits at runtime. This shares the same bits as
* VECSTRIDE, which is OK as no XScale CPU has VFP.
* Not cached, because VECLEN+VECSTRIDE are not cached.
*/
-FIELD(TBFLAG_A32, XSCALE_CPAR, 4, 2)
+FIELD(TBFLAG_A32, XSCALE_CPAR, 12, 2)
+FIELD(TBFLAG_A32, VFPEN, 14, 1) /* Partially cached, minus FPEXC. =
*/
+FIELD(TBFLAG_A32, SCTLR_B, 15, 1)
+FIELD(TBFLAG_A32, HSTR_ACTIVE, 16, 1)
/*
* Indicates whether cp register reads and writes by guest code should acc=
ess
* the secure or nonsecure bank of banked registers; note that this is not
* the same thing as the current security state of the processor!
*/
-FIELD(TBFLAG_A32, NS, 6, 1)
-FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. =
*/
-FIELD(TBFLAG_A32, CONDEXEC, 8, 8) /* Not cached. */
-FIELD(TBFLAG_A32, SCTLR_B, 16, 1)
-FIELD(TBFLAG_A32, HSTR_ACTIVE, 17, 1)
+FIELD(TBFLAG_A32, NS, 17, 1)
=20
-/* For M profile only, set if FPCCR.LSPACT is set */
-FIELD(TBFLAG_A32, LSPACT, 18, 1) /* Not cached. */
-/* For M profile only, set if we must create a new FP context */
-FIELD(TBFLAG_A32, NEW_FP_CTXT_NEEDED, 19, 1) /* Not cached. */
-/* For M profile only, set if FPCCR.S does not match current security stat=
e */
-FIELD(TBFLAG_A32, FPCCR_S_WRONG, 20, 1) /* Not cached. */
-/* For M profile only, Handler (ie not Thread) mode */
-FIELD(TBFLAG_A32, HANDLER, 21, 1)
-/* For M profile only, whether we should generate stack-limit checks */
-FIELD(TBFLAG_A32, STACKCHECK, 22, 1)
+/*
+ * Bit usage when in AArch32 state, for M-profile only.
+ */
+/* Handler (ie not Thread) mode */
+FIELD(TBFLAG_M32, HANDLER, 9, 1)
+/* Whether we should generate stack-limit checks */
+FIELD(TBFLAG_M32, STACKCHECK, 10, 1)
+/* Set if FPCCR.LSPACT is set */
+FIELD(TBFLAG_M32, LSPACT, 11, 1) /* Not cached. */
+/* Set if we must create a new FP context */
+FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 12, 1) /* Not cached. */
+/* Set if FPCCR.S does not match current security state */
+FIELD(TBFLAG_M32, FPCCR_S_WRONG, 13, 1) /* Not cached. */
=20
-/* Bit usage when in AArch64 state */
+/*
+ * Bit usage when in AArch64 state
+ */
FIELD(TBFLAG_A64, TBII, 0, 2)
FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2)
FIELD(TBFLAG_A64, ZCR_LEN, 4, 4)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 7ee41974566..5609bb18e86 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -11353,11 +11353,8 @@ static uint32_t rebuild_hflags_m32(CPUARMState *en=
v, int fp_el,
{
uint32_t flags =3D 0;
=20
- /* v8M always enables the fpu. */
- flags =3D FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1);
-
if (arm_v7m_is_handler_mode(env)) {
- flags =3D FIELD_DP32(flags, TBFLAG_A32, HANDLER, 1);
+ flags =3D FIELD_DP32(flags, TBFLAG_M32, HANDLER, 1);
}
=20
/*
@@ -11368,7 +11365,7 @@ static uint32_t rebuild_hflags_m32(CPUARMState *env=
, int fp_el,
if (arm_feature(env, ARM_FEATURE_V8) &&
!((mmu_idx & ARM_MMU_IDX_M_NEGPRI) &&
(env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_STKOFHFNMIGN_MASK))) {
- flags =3D FIELD_DP32(flags, TBFLAG_A32, STACKCHECK, 1);
+ flags =3D FIELD_DP32(flags, TBFLAG_M32, STACKCHECK, 1);
}
=20
return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags);
@@ -11561,7 +11558,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_=
ulong *pc,
if (arm_feature(env, ARM_FEATURE_M_SECURITY) &&
FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S)
!=3D env->v7m.secure) {
- flags =3D FIELD_DP32(flags, TBFLAG_A32, FPCCR_S_WRONG, 1);
+ flags =3D FIELD_DP32(flags, TBFLAG_M32, FPCCR_S_WRONG, 1);
}
=20
if ((env->v7m.fpccr[env->v7m.secure] & R_V7M_FPCCR_ASPEN_MASK)=
&&
@@ -11573,12 +11570,12 @@ void cpu_get_tb_cpu_state(CPUARMState *env, targe=
t_ulong *pc,
* active FP context; we must create a new FP context befo=
re
* executing any FP insn.
*/
- flags =3D FIELD_DP32(flags, TBFLAG_A32, NEW_FP_CTXT_NEEDED=
, 1);
+ flags =3D FIELD_DP32(flags, TBFLAG_M32, NEW_FP_CTXT_NEEDED=
, 1);
}
=20
bool is_secure =3D env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MAS=
K;
if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) {
- flags =3D FIELD_DP32(flags, TBFLAG_A32, LSPACT, 1);
+ flags =3D FIELD_DP32(flags, TBFLAG_M32, LSPACT, 1);
}
} else {
/*
@@ -11599,8 +11596,8 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_=
ulong *pc,
}
}
=20
- flags =3D FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb);
- flags =3D FIELD_DP32(flags, TBFLAG_A32, CONDEXEC, env->condexec_bi=
ts);
+ flags =3D FIELD_DP32(flags, TBFLAG_AM32, THUMB, env->thumb);
+ flags =3D FIELD_DP32(flags, TBFLAG_AM32, CONDEXEC, env->condexec_b=
its);
pstate_for_ss =3D env->uncached_cpsr;
}
=20
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 91e2ca55154..c169984374a 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -10848,38 +10848,48 @@ static void arm_tr_init_disas_context(DisasContex=
tBase *dcbase, CPUState *cs)
*/
dc->secure_routed_to_el3 =3D arm_feature(env, ARM_FEATURE_EL3) &&
!arm_el_is_aa64(env, 3);
- dc->thumb =3D FIELD_EX32(tb_flags, TBFLAG_A32, THUMB);
- dc->sctlr_b =3D FIELD_EX32(tb_flags, TBFLAG_A32, SCTLR_B);
- dc->hstr_active =3D FIELD_EX32(tb_flags, TBFLAG_A32, HSTR_ACTIVE);
+ dc->thumb =3D FIELD_EX32(tb_flags, TBFLAG_AM32, THUMB);
dc->be_data =3D FIELD_EX32(tb_flags, TBFLAG_ANY, BE_DATA) ? MO_BE : MO=
_LE;
- condexec =3D FIELD_EX32(tb_flags, TBFLAG_A32, CONDEXEC);
+ condexec =3D FIELD_EX32(tb_flags, TBFLAG_AM32, CONDEXEC);
dc->condexec_mask =3D (condexec & 0xf) << 1;
dc->condexec_cond =3D condexec >> 4;
+
core_mmu_idx =3D FIELD_EX32(tb_flags, TBFLAG_ANY, MMUIDX);
dc->mmu_idx =3D core_to_arm_mmu_idx(env, core_mmu_idx);
dc->current_el =3D arm_mmu_idx_to_el(dc->mmu_idx);
#if !defined(CONFIG_USER_ONLY)
dc->user =3D (dc->current_el =3D=3D 0);
#endif
- dc->ns =3D FIELD_EX32(tb_flags, TBFLAG_A32, NS);
dc->fp_excp_el =3D FIELD_EX32(tb_flags, TBFLAG_ANY, FPEXC_EL);
- dc->vfp_enabled =3D FIELD_EX32(tb_flags, TBFLAG_A32, VFPEN);
- dc->vec_len =3D FIELD_EX32(tb_flags, TBFLAG_A32, VECLEN);
- if (arm_feature(env, ARM_FEATURE_XSCALE)) {
- dc->c15_cpar =3D FIELD_EX32(tb_flags, TBFLAG_A32, XSCALE_CPAR);
- dc->vec_stride =3D 0;
+
+ if (arm_feature(env, ARM_FEATURE_M)) {
+ dc->vfp_enabled =3D 1;
+ dc->be_data =3D MO_TE;
+ dc->v7m_handler_mode =3D FIELD_EX32(tb_flags, TBFLAG_M32, HANDLER);
+ dc->v8m_secure =3D arm_feature(env, ARM_FEATURE_M_SECURITY) &&
+ regime_is_secure(env, dc->mmu_idx);
+ dc->v8m_stackcheck =3D FIELD_EX32(tb_flags, TBFLAG_M32, STACKCHECK=
);
+ dc->v8m_fpccr_s_wrong =3D
+ FIELD_EX32(tb_flags, TBFLAG_M32, FPCCR_S_WRONG);
+ dc->v7m_new_fp_ctxt_needed =3D
+ FIELD_EX32(tb_flags, TBFLAG_M32, NEW_FP_CTXT_NEEDED);
+ dc->v7m_lspact =3D FIELD_EX32(tb_flags, TBFLAG_M32, LSPACT);
} else {
- dc->vec_stride =3D FIELD_EX32(tb_flags, TBFLAG_A32, VECSTRIDE);
- dc->c15_cpar =3D 0;
+ dc->be_data =3D
+ FIELD_EX32(tb_flags, TBFLAG_ANY, BE_DATA) ? MO_BE : MO_LE;
+ dc->debug_target_el =3D
+ FIELD_EX32(tb_flags, TBFLAG_ANY, DEBUG_TARGET_EL);
+ dc->sctlr_b =3D FIELD_EX32(tb_flags, TBFLAG_A32, SCTLR_B);
+ dc->hstr_active =3D FIELD_EX32(tb_flags, TBFLAG_A32, HSTR_ACTIVE);
+ dc->ns =3D FIELD_EX32(tb_flags, TBFLAG_A32, NS);
+ dc->vfp_enabled =3D FIELD_EX32(tb_flags, TBFLAG_A32, VFPEN);
+ if (arm_feature(env, ARM_FEATURE_XSCALE)) {
+ dc->c15_cpar =3D FIELD_EX32(tb_flags, TBFLAG_A32, XSCALE_CPAR);
+ } else {
+ dc->vec_len =3D FIELD_EX32(tb_flags, TBFLAG_A32, VECLEN);
+ dc->vec_stride =3D FIELD_EX32(tb_flags, TBFLAG_A32, VECSTRIDE);
+ }
}
- dc->v7m_handler_mode =3D FIELD_EX32(tb_flags, TBFLAG_A32, HANDLER);
- dc->v8m_secure =3D arm_feature(env, ARM_FEATURE_M_SECURITY) &&
- regime_is_secure(env, dc->mmu_idx);
- dc->v8m_stackcheck =3D FIELD_EX32(tb_flags, TBFLAG_A32, STACKCHECK);
- dc->v8m_fpccr_s_wrong =3D FIELD_EX32(tb_flags, TBFLAG_A32, FPCCR_S_WRO=
NG);
- dc->v7m_new_fp_ctxt_needed =3D
- FIELD_EX32(tb_flags, TBFLAG_A32, NEW_FP_CTXT_NEEDED);
- dc->v7m_lspact =3D FIELD_EX32(tb_flags, TBFLAG_A32, LSPACT);
dc->cp_regs =3D cpu->cp_regs;
dc->features =3D env->features;
=20
@@ -10901,9 +10911,6 @@ static void arm_tr_init_disas_context(DisasContextB=
ase *dcbase, CPUState *cs)
dc->ss_active =3D FIELD_EX32(tb_flags, TBFLAG_ANY, SS_ACTIVE);
dc->pstate_ss =3D FIELD_EX32(tb_flags, TBFLAG_ANY, PSTATE_SS);
dc->is_ldex =3D false;
- if (!arm_feature(env, ARM_FEATURE_M)) {
- dc->debug_target_el =3D FIELD_EX32(tb_flags, TBFLAG_ANY, DEBUG_TAR=
GET_EL);
- }
=20
dc->page_start =3D dc->base.pc_first & TARGET_PAGE_MASK;
=20
@@ -11340,10 +11347,10 @@ static const TranslatorOps thumb_translator_ops =
=3D {
/* generate intermediate code for basic block 'tb'. */
void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_in=
sns)
{
- DisasContext dc;
+ DisasContext dc =3D { };
const TranslatorOps *ops =3D &arm_translator_ops;
=20
- if (FIELD_EX32(tb->flags, TBFLAG_A32, THUMB)) {
+ if (FIELD_EX32(tb->flags, TBFLAG_AM32, THUMB)) {
ops =3D &thumb_translator_ops;
}
#ifdef TARGET_AARCH64
--=20
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 17/48] target/arm: Expand TBFLAG_ANY.MMUIDX to 4 bits
Date: Fri, 7 Feb 2020 14:33:12 +0000
Message-Id: <20200207143343.30322-18-peter.maydell@linaro.org>
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From: Richard Henderson <richard.henderson@linaro.org>
We are about to expand the number of mmuidx to 10, and so need 4 bits.
For the benefit of reading the number out of -d exec, align it to the
penultimate nibble.
Tested-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Reviewed-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200206105448.4726-17-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index fce6a426c88..aa9728cff62 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3214,7 +3214,7 @@ typedef ARMCPU ArchCPU;
* We put flags which are shared between 32 and 64 bit mode at the top
* of the word, and flags which apply to only one mode at the bottom.
*
- * 31 21 18 14 9 0
+ * 31 20 18 14 9 0
* +--------------+-----+-----+----------+--------------+
* | | | TBFLAG_A32 | |
* | | +-----+----------+ TBFLAG_AM32 |
@@ -3222,19 +3222,19 @@ typedef ARMCPU ArchCPU;
* | | +-------------------------|
* | | | TBFLAG_A64 |
* +--------------+-----------+-------------------------+
- * 31 21 14 0
+ * 31 20 14 0
*
* Unless otherwise noted, these bits are cached in env->hflags.
*/
FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1)
-FIELD(TBFLAG_ANY, MMUIDX, 28, 3)
-FIELD(TBFLAG_ANY, SS_ACTIVE, 27, 1)
-FIELD(TBFLAG_ANY, PSTATE_SS, 26, 1) /* Not cached. */
+FIELD(TBFLAG_ANY, SS_ACTIVE, 30, 1)
+FIELD(TBFLAG_ANY, PSTATE_SS, 29, 1) /* Not cached. */
+FIELD(TBFLAG_ANY, BE_DATA, 28, 1)
+FIELD(TBFLAG_ANY, MMUIDX, 24, 4)
/* Target EL if we take a floating-point-disabled exception */
-FIELD(TBFLAG_ANY, FPEXC_EL, 24, 2)
-FIELD(TBFLAG_ANY, BE_DATA, 23, 1)
+FIELD(TBFLAG_ANY, FPEXC_EL, 22, 2)
/* For A-profile only, target EL for debug exceptions. */
-FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 21, 2)
+FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 20, 2)
=20
/*
* Bit usage when in AArch32 state, both A- and M-profile.
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 18/48] target/arm: Rearrange ARMMMUIdxBit
Date: Fri, 7 Feb 2020 14:33:13 +0000
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From: Richard Henderson <richard.henderson@linaro.org>
Define via macro expansion, so that renumbering of the base ARMMMUIdx
symbols is automatically reflected in the bit definitions.
Tested-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Reviewed-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daud=C3=A9 <philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200206105448.4726-18-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 39 +++++++++++++++++++++++----------------
1 file changed, 23 insertions(+), 16 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index aa9728cff62..aa121cd9d0a 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -2927,27 +2927,34 @@ typedef enum ARMMMUIdx {
ARMMMUIdx_Stage1_E1 =3D 1 | ARM_MMU_IDX_NOTLB,
} ARMMMUIdx;
=20
-/* Bit macros for the core-mmu-index values for each index,
+/*
+ * Bit macros for the core-mmu-index values for each index,
* for use when calling tlb_flush_by_mmuidx() and friends.
*/
+#define TO_CORE_BIT(NAME) \
+ ARMMMUIdxBit_##NAME =3D 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_M=
ASK)
+
typedef enum ARMMMUIdxBit {
- ARMMMUIdxBit_E10_0 =3D 1 << 0,
- ARMMMUIdxBit_E10_1 =3D 1 << 1,
- ARMMMUIdxBit_E2 =3D 1 << 2,
- ARMMMUIdxBit_SE3 =3D 1 << 3,
- ARMMMUIdxBit_SE10_0 =3D 1 << 4,
- ARMMMUIdxBit_SE10_1 =3D 1 << 5,
- ARMMMUIdxBit_Stage2 =3D 1 << 6,
- ARMMMUIdxBit_MUser =3D 1 << 0,
- ARMMMUIdxBit_MPriv =3D 1 << 1,
- ARMMMUIdxBit_MUserNegPri =3D 1 << 2,
- ARMMMUIdxBit_MPrivNegPri =3D 1 << 3,
- ARMMMUIdxBit_MSUser =3D 1 << 4,
- ARMMMUIdxBit_MSPriv =3D 1 << 5,
- ARMMMUIdxBit_MSUserNegPri =3D 1 << 6,
- ARMMMUIdxBit_MSPrivNegPri =3D 1 << 7,
+ TO_CORE_BIT(E10_0),
+ TO_CORE_BIT(E10_1),
+ TO_CORE_BIT(E2),
+ TO_CORE_BIT(SE10_0),
+ TO_CORE_BIT(SE10_1),
+ TO_CORE_BIT(SE3),
+ TO_CORE_BIT(Stage2),
+
+ TO_CORE_BIT(MUser),
+ TO_CORE_BIT(MPriv),
+ TO_CORE_BIT(MUserNegPri),
+ TO_CORE_BIT(MPrivNegPri),
+ TO_CORE_BIT(MSUser),
+ TO_CORE_BIT(MSPriv),
+ TO_CORE_BIT(MSUserNegPri),
+ TO_CORE_BIT(MSPrivNegPri),
} ARMMMUIdxBit;
=20
+#undef TO_CORE_BIT
+
#define MMU_USER_IDX 0
=20
static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx)
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 19/48] target/arm: Tidy ARMMMUIdx m-profile definitions
Date: Fri, 7 Feb 2020 14:33:14 +0000
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From: Richard Henderson <richard.henderson@linaro.org>
Replace the magic numbers with the relevant ARM_MMU_IDX_M_* constants.
Keep the definitions short by referencing previous symbols.
Tested-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daud=C3=A9 <philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200206105448.4726-19-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index aa121cd9d0a..ad92873943f 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -2912,14 +2912,14 @@ typedef enum ARMMMUIdx {
ARMMMUIdx_SE10_0 =3D 4 | ARM_MMU_IDX_A,
ARMMMUIdx_SE10_1 =3D 5 | ARM_MMU_IDX_A,
ARMMMUIdx_Stage2 =3D 6 | ARM_MMU_IDX_A,
- ARMMMUIdx_MUser =3D 0 | ARM_MMU_IDX_M,
- ARMMMUIdx_MPriv =3D 1 | ARM_MMU_IDX_M,
- ARMMMUIdx_MUserNegPri =3D 2 | ARM_MMU_IDX_M,
- ARMMMUIdx_MPrivNegPri =3D 3 | ARM_MMU_IDX_M,
- ARMMMUIdx_MSUser =3D 4 | ARM_MMU_IDX_M,
- ARMMMUIdx_MSPriv =3D 5 | ARM_MMU_IDX_M,
- ARMMMUIdx_MSUserNegPri =3D 6 | ARM_MMU_IDX_M,
- ARMMMUIdx_MSPrivNegPri =3D 7 | ARM_MMU_IDX_M,
+ ARMMMUIdx_MUser =3D ARM_MMU_IDX_M,
+ ARMMMUIdx_MPriv =3D ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV,
+ ARMMMUIdx_MUserNegPri =3D ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI,
+ ARMMMUIdx_MPrivNegPri =3D ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI,
+ ARMMMUIdx_MSUser =3D ARMMMUIdx_MUser | ARM_MMU_IDX_M_S,
+ ARMMMUIdx_MSPriv =3D ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S,
+ ARMMMUIdx_MSUserNegPri =3D ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S,
+ ARMMMUIdx_MSPrivNegPri =3D ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S,
/* Indexes below here don't have TLBs and are used only for AT system
* instructions or for the first stage of an S12 page table walk.
*/
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 20/48] target/arm: Reorganize ARMMMUIdx
Date: Fri, 7 Feb 2020 14:33:15 +0000
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From: Richard Henderson <richard.henderson@linaro.org>
Prepare for, but do not yet implement, the EL2&0 regime.
This involves adding the new MMUIdx enumerators and adjusting
some of the MMUIdx related predicates to match.
Tested-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Reviewed-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200206105448.4726-20-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu-param.h | 2 +-
target/arm/cpu.h | 134 ++++++++++++++++++-----------------------
target/arm/internals.h | 35 +++++++++++
target/arm/helper.c | 66 +++++++++++++++++---
target/arm/translate.c | 1 -
5 files changed, 152 insertions(+), 86 deletions(-)
diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h
index 6e6948e9602..18ac5623462 100644
--- a/target/arm/cpu-param.h
+++ b/target/arm/cpu-param.h
@@ -29,6 +29,6 @@
# define TARGET_PAGE_BITS_MIN 10
#endif
=20
-#define NB_MMU_MODES 8
+#define NB_MMU_MODES 9
=20
#endif
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index ad92873943f..3fc0e6e7465 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -2819,18 +2819,21 @@ static inline bool arm_excp_unmasked(CPUState *cs, =
unsigned int excp_idx,
* + NonSecure EL1 & 0 stage 1
* + NonSecure EL1 & 0 stage 2
* + NonSecure EL2
- * + Secure EL1 & EL0
+ * + NonSecure EL2 & 0 (ARMv8.1-VHE)
+ * + Secure EL1 & 0
* + Secure EL3
* If EL3 is 32-bit:
* + NonSecure PL1 & 0 stage 1
* + NonSecure PL1 & 0 stage 2
* + NonSecure PL2
- * + Secure PL0 & PL1
+ * + Secure PL0
+ * + Secure PL1
* (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.)
*
* For QEMU, an mmu_idx is not quite the same as a translation regime beca=
use:
- * 1. we need to split the "EL1 & 0" regimes into two mmu_idxes, because =
they
- * may differ in access permissions even if the VA->PA map is the same
+ * 1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_i=
dxes,
+ * because they may differ in access permissions even if the VA->PA ma=
p is
+ * the same
* 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage=
1+2
* translation, which means that we have one mmu_idx that deals with t=
wo
* concatenated translation regimes [this sort of combined s1+2 TLB is
@@ -2842,19 +2845,23 @@ static inline bool arm_excp_unmasked(CPUState *cs, =
unsigned int excp_idx,
* 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3"
* translation regimes, because they map reasonably well to each other
* and they can't both be active at the same time.
- * This gives us the following list of mmu_idx values:
+ * 5. we want to be able to use the TLB for accesses done as part of a
+ * stage1 page table walk, rather than having to walk the stage2 page
+ * table over and over.
*
- * NS EL0 (aka NS PL0) stage 1+2
- * NS EL1 (aka NS PL1) stage 1+2
+ * This gives us the following list of cases:
+ *
+ * NS EL0 EL1&0 stage 1+2 (aka NS PL0)
+ * NS EL1 EL1&0 stage 1+2 (aka NS PL1)
+ * NS EL0 EL2&0
+ * NS EL2 EL2&0
* NS EL2 (aka NS PL2)
+ * S EL0 EL1&0 (aka S PL0)
+ * S EL1 EL1&0 (not used if EL3 is 32 bit)
* S EL3 (aka S PL1)
- * S EL0 (aka S PL0)
- * S EL1 (not used if EL3 is 32 bit)
- * NS EL0+1 stage 2
+ * NS EL1&0 stage 2
*
- * (The last of these is an mmu_idx because we want to be able to use the =
TLB
- * for the accesses done as part of a stage 1 page table walk, rather than
- * having to walk the stage 2 page table over and over.)
+ * for a total of 9 different mmu_idx.
*
* R profile CPUs have an MPU, but can use the same set of MMU indexes
* as A profile. They only need to distinguish NS EL0 and NS EL1 (and
@@ -2892,26 +2899,47 @@ static inline bool arm_excp_unmasked(CPUState *cs, =
unsigned int excp_idx,
* For M profile we arrange them to have a bit for priv, a bit for negpri
* and a bit for secure.
*/
-#define ARM_MMU_IDX_A 0x10 /* A profile */
-#define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */
-#define ARM_MMU_IDX_M 0x40 /* M profile */
+#define ARM_MMU_IDX_A 0x10 /* A profile */
+#define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */
+#define ARM_MMU_IDX_M 0x40 /* M profile */
=20
-/* meanings of the bits for M profile mmu idx values */
-#define ARM_MMU_IDX_M_PRIV 0x1
+/* Meanings of the bits for M profile mmu idx values */
+#define ARM_MMU_IDX_M_PRIV 0x1
#define ARM_MMU_IDX_M_NEGPRI 0x2
-#define ARM_MMU_IDX_M_S 0x4
+#define ARM_MMU_IDX_M_S 0x4 /* Secure */
=20
-#define ARM_MMU_IDX_TYPE_MASK (~0x7)
-#define ARM_MMU_IDX_COREIDX_MASK 0x7
+#define ARM_MMU_IDX_TYPE_MASK \
+ (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB)
+#define ARM_MMU_IDX_COREIDX_MASK 0xf
=20
typedef enum ARMMMUIdx {
- ARMMMUIdx_E10_0 =3D 0 | ARM_MMU_IDX_A,
- ARMMMUIdx_E10_1 =3D 1 | ARM_MMU_IDX_A,
- ARMMMUIdx_E2 =3D 2 | ARM_MMU_IDX_A,
- ARMMMUIdx_SE3 =3D 3 | ARM_MMU_IDX_A,
- ARMMMUIdx_SE10_0 =3D 4 | ARM_MMU_IDX_A,
- ARMMMUIdx_SE10_1 =3D 5 | ARM_MMU_IDX_A,
- ARMMMUIdx_Stage2 =3D 6 | ARM_MMU_IDX_A,
+ /*
+ * A-profile.
+ */
+ ARMMMUIdx_E10_0 =3D 0 | ARM_MMU_IDX_A,
+ ARMMMUIdx_E20_0 =3D 1 | ARM_MMU_IDX_A,
+
+ ARMMMUIdx_E10_1 =3D 2 | ARM_MMU_IDX_A,
+
+ ARMMMUIdx_E2 =3D 3 | ARM_MMU_IDX_A,
+ ARMMMUIdx_E20_2 =3D 4 | ARM_MMU_IDX_A,
+
+ ARMMMUIdx_SE10_0 =3D 5 | ARM_MMU_IDX_A,
+ ARMMMUIdx_SE10_1 =3D 6 | ARM_MMU_IDX_A,
+ ARMMMUIdx_SE3 =3D 7 | ARM_MMU_IDX_A,
+
+ ARMMMUIdx_Stage2 =3D 8 | ARM_MMU_IDX_A,
+
+ /*
+ * These are not allocated TLBs and are used only for AT system
+ * instructions or for the first stage of an S12 page table walk.
+ */
+ ARMMMUIdx_Stage1_E0 =3D 0 | ARM_MMU_IDX_NOTLB,
+ ARMMMUIdx_Stage1_E1 =3D 1 | ARM_MMU_IDX_NOTLB,
+
+ /*
+ * M-profile.
+ */
ARMMMUIdx_MUser =3D ARM_MMU_IDX_M,
ARMMMUIdx_MPriv =3D ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV,
ARMMMUIdx_MUserNegPri =3D ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI,
@@ -2920,11 +2948,6 @@ typedef enum ARMMMUIdx {
ARMMMUIdx_MSPriv =3D ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S,
ARMMMUIdx_MSUserNegPri =3D ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S,
ARMMMUIdx_MSPrivNegPri =3D ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S,
- /* Indexes below here don't have TLBs and are used only for AT system
- * instructions or for the first stage of an S12 page table walk.
- */
- ARMMMUIdx_Stage1_E0 =3D 0 | ARM_MMU_IDX_NOTLB,
- ARMMMUIdx_Stage1_E1 =3D 1 | ARM_MMU_IDX_NOTLB,
} ARMMMUIdx;
=20
/*
@@ -2936,8 +2959,10 @@ typedef enum ARMMMUIdx {
=20
typedef enum ARMMMUIdxBit {
TO_CORE_BIT(E10_0),
+ TO_CORE_BIT(E20_0),
TO_CORE_BIT(E10_1),
TO_CORE_BIT(E2),
+ TO_CORE_BIT(E20_2),
TO_CORE_BIT(SE10_0),
TO_CORE_BIT(SE10_1),
TO_CORE_BIT(SE3),
@@ -2957,49 +2982,6 @@ typedef enum ARMMMUIdxBit {
=20
#define MMU_USER_IDX 0
=20
-static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx)
-{
- return mmu_idx & ARM_MMU_IDX_COREIDX_MASK;
-}
-
-static inline ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx)
-{
- if (arm_feature(env, ARM_FEATURE_M)) {
- return mmu_idx | ARM_MMU_IDX_M;
- } else {
- return mmu_idx | ARM_MMU_IDX_A;
- }
-}
-
-/* Return the exception level we're running at if this is our mmu_idx */
-static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx)
-{
- switch (mmu_idx & ARM_MMU_IDX_TYPE_MASK) {
- case ARM_MMU_IDX_A:
- return mmu_idx & 3;
- case ARM_MMU_IDX_M:
- return mmu_idx & ARM_MMU_IDX_M_PRIV;
- default:
- g_assert_not_reached();
- }
-}
-
-/*
- * Return the MMU index for a v7M CPU with all relevant information
- * manually specified.
- */
-ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env,
- bool secstate, bool priv, bool negpri);
-
-/* Return the MMU index for a v7M CPU in the specified security and
- * privilege state.
- */
-ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
- bool secstate, bool priv);
-
-/* Return the MMU index for a v7M CPU in the specified security state */
-ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate);
-
/**
* cpu_mmu_index:
* @env: The cpu environment
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 5b8b9c233fe..0c4119a3a2e 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -769,6 +769,39 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int=
size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
=20
+static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx)
+{
+ return mmu_idx & ARM_MMU_IDX_COREIDX_MASK;
+}
+
+static inline ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx)
+{
+ if (arm_feature(env, ARM_FEATURE_M)) {
+ return mmu_idx | ARM_MMU_IDX_M;
+ } else {
+ return mmu_idx | ARM_MMU_IDX_A;
+ }
+}
+
+int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx);
+
+/*
+ * Return the MMU index for a v7M CPU with all relevant information
+ * manually specified.
+ */
+ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env,
+ bool secstate, bool priv, bool negpri);
+
+/*
+ * Return the MMU index for a v7M CPU in the specified security and
+ * privilege state.
+ */
+ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
+ bool secstate, bool priv);
+
+/* Return the MMU index for a v7M CPU in the specified security state */
+ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate);
+
/* Return true if the stage 1 translation regime is using LPAE format page
* tables */
bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx);
@@ -810,6 +843,8 @@ static inline bool regime_is_secure(CPUARMState *env, A=
RMMMUIdx mmu_idx)
switch (mmu_idx) {
case ARMMMUIdx_E10_0:
case ARMMMUIdx_E10_1:
+ case ARMMMUIdx_E20_0:
+ case ARMMMUIdx_E20_2:
case ARMMMUIdx_Stage1_E0:
case ARMMMUIdx_Stage1_E1:
case ARMMMUIdx_E2:
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 5609bb18e86..3ce37c2c163 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -8707,9 +8707,11 @@ void arm_cpu_do_interrupt(CPUState *cs)
#endif /* !CONFIG_USER_ONLY */
=20
/* Return the exception level which controls this address translation regi=
me */
-static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx)
+static uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx)
{
switch (mmu_idx) {
+ case ARMMMUIdx_E20_0:
+ case ARMMMUIdx_E20_2:
case ARMMMUIdx_Stage2:
case ARMMMUIdx_E2:
return 2;
@@ -8720,6 +8722,8 @@ static inline uint32_t regime_el(CPUARMState *env, AR=
MMMUIdx mmu_idx)
case ARMMMUIdx_SE10_1:
case ARMMMUIdx_Stage1_E0:
case ARMMMUIdx_Stage1_E1:
+ case ARMMMUIdx_E10_0:
+ case ARMMMUIdx_E10_1:
case ARMMMUIdx_MPrivNegPri:
case ARMMMUIdx_MUserNegPri:
case ARMMMUIdx_MPriv:
@@ -8821,10 +8825,14 @@ static inline TCR *regime_tcr(CPUARMState *env, ARM=
MMUIdx mmu_idx)
*/
static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx)
{
- if (mmu_idx =3D=3D ARMMMUIdx_E10_0 || mmu_idx =3D=3D ARMMMUIdx_E10_1) {
- mmu_idx +=3D (ARMMMUIdx_Stage1_E0 - ARMMMUIdx_E10_0);
+ switch (mmu_idx) {
+ case ARMMMUIdx_E10_0:
+ return ARMMMUIdx_Stage1_E0;
+ case ARMMMUIdx_E10_1:
+ return ARMMMUIdx_Stage1_E1;
+ default:
+ return mmu_idx;
}
- return mmu_idx;
}
=20
/* Return true if the translation regime is using LPAE format page tables =
*/
@@ -8857,6 +8865,7 @@ static inline bool regime_is_user(CPUARMState *env, A=
RMMMUIdx mmu_idx)
{
switch (mmu_idx) {
case ARMMMUIdx_SE10_0:
+ case ARMMMUIdx_E20_0:
case ARMMMUIdx_Stage1_E0:
case ARMMMUIdx_MUser:
case ARMMMUIdx_MSUser:
@@ -11282,6 +11291,31 @@ int fp_exception_el(CPUARMState *env, int cur_el)
return 0;
}
=20
+/* Return the exception level we're running at if this is our mmu_idx */
+int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx)
+{
+ if (mmu_idx & ARM_MMU_IDX_M) {
+ return mmu_idx & ARM_MMU_IDX_M_PRIV;
+ }
+
+ switch (mmu_idx) {
+ case ARMMMUIdx_E10_0:
+ case ARMMMUIdx_E20_0:
+ case ARMMMUIdx_SE10_0:
+ return 0;
+ case ARMMMUIdx_E10_1:
+ case ARMMMUIdx_SE10_1:
+ return 1;
+ case ARMMMUIdx_E2:
+ case ARMMMUIdx_E20_2:
+ return 2;
+ case ARMMMUIdx_SE3:
+ return 3;
+ default:
+ g_assert_not_reached();
+ }
+}
+
#ifndef CONFIG_TCG
ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
{
@@ -11295,10 +11329,26 @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el)
return arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure);
}
=20
- if (el < 2 && arm_is_secure_below_el3(env)) {
- return ARMMMUIdx_SE10_0 + el;
- } else {
- return ARMMMUIdx_E10_0 + el;
+ switch (el) {
+ case 0:
+ /* TODO: ARMv8.1-VHE */
+ if (arm_is_secure_below_el3(env)) {
+ return ARMMMUIdx_SE10_0;
+ }
+ return ARMMMUIdx_E10_0;
+ case 1:
+ if (arm_is_secure_below_el3(env)) {
+ return ARMMMUIdx_SE10_1;
+ }
+ return ARMMMUIdx_E10_1;
+ case 2:
+ /* TODO: ARMv8.1-VHE */
+ /* TODO: ARMv8.4-SecEL2 */
+ return ARMMMUIdx_E2;
+ case 3:
+ return ARMMMUIdx_SE3;
+ default:
+ g_assert_not_reached();
}
}
=20
diff --git a/target/arm/translate.c b/target/arm/translate.c
index c169984374a..e11a5871d02 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -172,7 +172,6 @@ static inline int get_a32_user_mem_index(DisasContext *=
s)
case ARMMMUIdx_MSUserNegPri:
case ARMMMUIdx_MSPrivNegPri:
return arm_to_core_mmu_idx(ARMMMUIdx_MSUserNegPri);
- case ARMMMUIdx_Stage2:
default:
g_assert_not_reached();
}
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 21/48] target/arm: Add regime_has_2_ranges
Date: Fri, 7 Feb 2020 14:33:16 +0000
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From: Richard Henderson <richard.henderson@linaro.org>
Create a predicate to indicate whether the regime has
both positive and negative addresses.
Tested-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Reviewed-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200206105448.4726-21-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/internals.h | 18 ++++++++++++++++++
target/arm/helper.c | 23 ++++++-----------------
target/arm/translate-a64.c | 3 +--
3 files changed, 25 insertions(+), 19 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 0c4119a3a2e..6d4a942bde4 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -837,6 +837,24 @@ static inline void arm_call_el_change_hook(ARMCPU *cpu)
}
}
=20
+/* Return true if this address translation regime has two ranges. */
+static inline bool regime_has_2_ranges(ARMMMUIdx mmu_idx)
+{
+ switch (mmu_idx) {
+ case ARMMMUIdx_Stage1_E0:
+ case ARMMMUIdx_Stage1_E1:
+ case ARMMMUIdx_E10_0:
+ case ARMMMUIdx_E10_1:
+ case ARMMMUIdx_E20_0:
+ case ARMMMUIdx_E20_2:
+ case ARMMMUIdx_SE10_0:
+ case ARMMMUIdx_SE10_1:
+ return true;
+ default:
+ return false;
+ }
+}
+
/* Return true if this address translation regime is secure */
static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx)
{
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 3ce37c2c163..f7bc7f1a8de 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -9031,15 +9031,8 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mm=
u_idx, bool is_aa64,
}
=20
if (is_aa64) {
- switch (regime_el(env, mmu_idx)) {
- case 1:
- if (!is_user) {
- xn =3D pxn || (user_rw & PAGE_WRITE);
- }
- break;
- case 2:
- case 3:
- break;
+ if (regime_has_2_ranges(mmu_idx) && !is_user) {
+ xn =3D pxn || (user_rw & PAGE_WRITE);
}
} else if (arm_feature(env, ARM_FEATURE_V7)) {
switch (regime_el(env, mmu_idx)) {
@@ -9573,7 +9566,6 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *=
env, uint64_t va,
ARMMMUIdx mmu_idx)
{
uint64_t tcr =3D regime_tcr(env, mmu_idx)->raw_tcr;
- uint32_t el =3D regime_el(env, mmu_idx);
bool tbi, tbid, epd, hpd, using16k, using64k;
int select, tsz;
=20
@@ -9583,7 +9575,7 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *=
env, uint64_t va,
*/
select =3D extract64(va, 55, 1);
=20
- if (el > 1) {
+ if (!regime_has_2_ranges(mmu_idx)) {
tsz =3D extract32(tcr, 0, 6);
using64k =3D extract32(tcr, 14, 1);
using16k =3D extract32(tcr, 15, 1);
@@ -9739,10 +9731,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, tar=
get_ulong address,
param =3D aa64_va_parameters(env, address, mmu_idx,
access_type !=3D MMU_INST_FETCH);
level =3D 0;
- /* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mark =
it
- * invalid.
- */
- ttbr1_valid =3D (el < 2);
+ ttbr1_valid =3D regime_has_2_ranges(mmu_idx);
addrsize =3D 64 - 8 * param.tbi;
inputsize =3D 64 - param.tsz;
} else {
@@ -11458,8 +11447,8 @@ static uint32_t rebuild_hflags_a64(CPUARMState *env=
, int el, int fp_el,
=20
flags =3D FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1);
=20
- /* FIXME: ARMv8.1-VHE S2 translation regime. */
- if (regime_el(env, stage1) < 2) {
+ /* Get control bits for tagged addresses. */
+ if (regime_has_2_ranges(mmu_idx)) {
ARMVAParameters p1 =3D aa64_va_parameters_both(env, -1, stage1);
tbid =3D (p1.tbi << 1) | p0.tbi;
tbii =3D tbid & ~((p1.tbid << 1) | p0.tbid);
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index fcfb96ce1fb..3982e1988dc 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -175,8 +175,7 @@ static void gen_top_byte_ignore(DisasContext *s, TCGv_i=
64 dst,
if (tbi =3D=3D 0) {
/* Load unmodified address */
tcg_gen_mov_i64(dst, src);
- } else if (s->current_el >=3D 2) {
- /* FIXME: ARMv8.1-VHE S2 translation regime. */
+ } else if (!regime_has_2_ranges(s->mmu_idx)) {
/* Force tag byte to all zero */
tcg_gen_extract_i64(dst, src, 0, 56);
} else {
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 22/48] target/arm: Update arm_mmu_idx for VHE
Date: Fri, 7 Feb 2020 14:33:17 +0000
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From: Richard Henderson <richard.henderson@linaro.org>
Return the indexes for the EL2&0 regime when the appropriate bits
are set within HCR_EL2.
Tested-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Reviewed-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200206105448.4726-22-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index f7bc7f1a8de..9f8d7ca1f36 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -11318,12 +11318,16 @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el)
return arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure);
}
=20
+ /* See ARM pseudo-function ELIsInHost. */
switch (el) {
case 0:
- /* TODO: ARMv8.1-VHE */
if (arm_is_secure_below_el3(env)) {
return ARMMMUIdx_SE10_0;
}
+ if ((env->cp15.hcr_el2 & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HC=
R_TGE)
+ && arm_el_is_aa64(env, 2)) {
+ return ARMMMUIdx_E20_0;
+ }
return ARMMMUIdx_E10_0;
case 1:
if (arm_is_secure_below_el3(env)) {
@@ -11331,8 +11335,11 @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el)
}
return ARMMMUIdx_E10_1;
case 2:
- /* TODO: ARMv8.1-VHE */
/* TODO: ARMv8.4-SecEL2 */
+ /* Note that TGE does not apply at EL2. */
+ if ((env->cp15.hcr_el2 & HCR_E2H) && arm_el_is_aa64(env, 2)) {
+ return ARMMMUIdx_E20_2;
+ }
return ARMMMUIdx_E2;
case 3:
return ARMMMUIdx_SE3;
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 23/48] target/arm: Update arm_sctlr for VHE
Date: Fri, 7 Feb 2020 14:33:18 +0000
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From: Richard Henderson <richard.henderson@linaro.org>
Use the correct sctlr for EL2&0 regime. Due to header ordering,
and where arm_mmu_idx_el is declared, we need to move the function
out of line. Use the function in many more places in order to
select the correct control.
Tested-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Reviewed-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200206105448.4726-23-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 10 +---------
target/arm/helper-a64.c | 2 +-
target/arm/helper.c | 20 +++++++++++++++-----
target/arm/pauth_helper.c | 9 +--------
4 files changed, 18 insertions(+), 23 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 3fc0e6e7465..68e11f0eda3 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3141,15 +3141,7 @@ static inline bool arm_sctlr_b(CPUARMState *env)
(env->cp15.sctlr_el[1] & SCTLR_B) !=3D 0;
}
=20
-static inline uint64_t arm_sctlr(CPUARMState *env, int el)
-{
- if (el =3D=3D 0) {
- /* FIXME: ARMv8.1-VHE S2 translation regime. */
- return env->cp15.sctlr_el[1];
- } else {
- return env->cp15.sctlr_el[el];
- }
-}
+uint64_t arm_sctlr(CPUARMState *env, int el);
=20
static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env,
bool sctlr_b)
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index 36aa6badfd9..bf45f8a785e 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -70,7 +70,7 @@ static void daif_check(CPUARMState *env, uint32_t op,
uint32_t imm, uintptr_t ra)
{
/* DAIF update to PSTATE. This is OK from EL0 only if UMA is set. */
- if (arm_current_el(env) =3D=3D 0 && !(env->cp15.sctlr_el[1] & SCTLR_UM=
A)) {
+ if (arm_current_el(env) =3D=3D 0 && !(arm_sctlr(env, 0) & SCTLR_UMA)) {
raise_exception_ra(env, EXCP_UDEF,
syn_aa64_sysregtrap(0, extract32(op, 0, 3),
extract32(op, 3, 3), 4,
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 9f8d7ca1f36..e4f368d96b6 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -3913,7 +3913,7 @@ static void aa64_fpsr_write(CPUARMState *env, const A=
RMCPRegInfo *ri,
static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInf=
o *ri,
bool isread)
{
- if (arm_current_el(env) =3D=3D 0 && !(env->cp15.sctlr_el[1] & SCTLR_UM=
A)) {
+ if (arm_current_el(env) =3D=3D 0 && !(arm_sctlr(env, 0) & SCTLR_UMA)) {
return CP_ACCESS_TRAP;
}
return CP_ACCESS_OK;
@@ -3932,7 +3932,7 @@ static CPAccessResult aa64_cacheop_access(CPUARMState=
*env,
/* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
* SCTLR_EL1.UCI is set.
*/
- if (arm_current_el(env) =3D=3D 0 && !(env->cp15.sctlr_el[1] & SCTLR_UC=
I)) {
+ if (arm_current_el(env) =3D=3D 0 && !(arm_sctlr(env, 0) & SCTLR_UCI)) {
return CP_ACCESS_TRAP;
}
return CP_ACCESS_OK;
@@ -8738,14 +8738,24 @@ static uint32_t regime_el(CPUARMState *env, ARMMMUI=
dx mmu_idx)
}
}
=20
-#ifndef CONFIG_USER_ONLY
+uint64_t arm_sctlr(CPUARMState *env, int el)
+{
+ /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */
+ if (el =3D=3D 0) {
+ ARMMMUIdx mmu_idx =3D arm_mmu_idx_el(env, 0);
+ el =3D (mmu_idx =3D=3D ARMMMUIdx_E20_0 ? 2 : 1);
+ }
+ return env->cp15.sctlr_el[el];
+}
=20
/* Return the SCTLR value which controls this address translation regime */
-static inline uint32_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx)
+static inline uint64_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx)
{
return env->cp15.sctlr_el[regime_el(env, mmu_idx)];
}
=20
+#ifndef CONFIG_USER_ONLY
+
/* Return true if the specified stage of address translation is disabled */
static inline bool regime_translation_disabled(CPUARMState *env,
ARMMMUIdx mmu_idx)
@@ -11484,7 +11494,7 @@ static uint32_t rebuild_hflags_a64(CPUARMState *env=
, int el, int fp_el,
flags =3D FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len);
}
=20
- sctlr =3D arm_sctlr(env, el);
+ sctlr =3D regime_sctlr(env, stage1);
=20
if (arm_cpu_data_is_big_endian_a64(el, sctlr)) {
flags =3D FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1);
diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c
index 0a5f41e10c5..e0c401c4a9e 100644
--- a/target/arm/pauth_helper.c
+++ b/target/arm/pauth_helper.c
@@ -386,14 +386,7 @@ static void pauth_check_trap(CPUARMState *env, int el,=
uintptr_t ra)
=20
static bool pauth_key_enabled(CPUARMState *env, int el, uint32_t bit)
{
- uint32_t sctlr;
- if (el =3D=3D 0) {
- /* FIXME: ARMv8.1-VHE S2 translation regime. */
- sctlr =3D env->cp15.sctlr_el[1];
- } else {
- sctlr =3D env->cp15.sctlr_el[el];
- }
- return (sctlr & bit) !=3D 0;
+ return (arm_sctlr(env, el) & bit) !=3D 0;
}
=20
uint64_t HELPER(pacia)(CPUARMState *env, uint64_t x, uint64_t y)
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 24/48] target/arm: Update aa64_zva_access for EL2
Date: Fri, 7 Feb 2020 14:33:19 +0000
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From: Richard Henderson <richard.henderson@linaro.org>
The comment that we don't support EL2 is somewhat out of date.
Update to include checks against HCR_EL2.TDZ.
Tested-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Reviewed-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200206105448.4726-24-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 26 +++++++++++++++++++++-----
1 file changed, 21 insertions(+), 5 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index e4f368d96b6..e41bece6b58 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -4159,11 +4159,27 @@ static void tlbi_aa64_ipas2e1is_write(CPUARMState *=
env, const ARMCPRegInfo *ri,
static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo=
*ri,
bool isread)
{
- /* We don't implement EL2, so the only control on DC ZVA is the
- * bit in the SCTLR which can prohibit access for EL0.
- */
- if (arm_current_el(env) =3D=3D 0 && !(env->cp15.sctlr_el[1] & SCTLR_DZ=
E)) {
- return CP_ACCESS_TRAP;
+ int cur_el =3D arm_current_el(env);
+
+ if (cur_el < 2) {
+ uint64_t hcr =3D arm_hcr_el2_eff(env);
+
+ if (cur_el =3D=3D 0) {
+ if ((hcr & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)) {
+ if (!(env->cp15.sctlr_el[2] & SCTLR_DZE)) {
+ return CP_ACCESS_TRAP_EL2;
+ }
+ } else {
+ if (!(env->cp15.sctlr_el[1] & SCTLR_DZE)) {
+ return CP_ACCESS_TRAP;
+ }
+ if (hcr & HCR_TDZ) {
+ return CP_ACCESS_TRAP_EL2;
+ }
+ }
+ } else if (hcr & HCR_TDZ) {
+ return CP_ACCESS_TRAP_EL2;
+ }
}
return CP_ACCESS_OK;
}
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 25/48] target/arm: Update ctr_el0_access for EL2
Date: Fri, 7 Feb 2020 14:33:20 +0000
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From: Richard Henderson <richard.henderson@linaro.org>
Update to include checks against HCR_EL2.TID2.
Tested-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Reviewed-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200206105448.4726-25-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 26 +++++++++++++++++++++-----
1 file changed, 21 insertions(+), 5 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index e41bece6b58..72b336e3b5d 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -5264,11 +5264,27 @@ static const ARMCPRegInfo el3_cp_reginfo[] =3D {
static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo =
*ri,
bool isread)
{
- /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,
- * but the AArch32 CTR has its own reginfo struct)
- */
- if (arm_current_el(env) =3D=3D 0 && !(env->cp15.sctlr_el[1] & SCTLR_UC=
T)) {
- return CP_ACCESS_TRAP;
+ int cur_el =3D arm_current_el(env);
+
+ if (cur_el < 2) {
+ uint64_t hcr =3D arm_hcr_el2_eff(env);
+
+ if (cur_el =3D=3D 0) {
+ if ((hcr & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)) {
+ if (!(env->cp15.sctlr_el[2] & SCTLR_UCT)) {
+ return CP_ACCESS_TRAP_EL2;
+ }
+ } else {
+ if (!(env->cp15.sctlr_el[1] & SCTLR_UCT)) {
+ return CP_ACCESS_TRAP;
+ }
+ if (hcr & HCR_TID2) {
+ return CP_ACCESS_TRAP_EL2;
+ }
+ }
+ } else if (hcr & HCR_TID2) {
+ return CP_ACCESS_TRAP_EL2;
+ }
}
=20
if (arm_current_el(env) < 2 && arm_hcr_el2_eff(env) & HCR_TID2) {
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 26/48] target/arm: Add the hypervisor virtual counter
Date: Fri, 7 Feb 2020 14:33:21 +0000
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From: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Reviewed-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu-qom.h | 1 +
target/arm/cpu.h | 11 +++++----
target/arm/cpu.c | 3 ++-
target/arm/helper.c | 56 ++++++++++++++++++++++++++++++++++++++++++++
4 files changed, 65 insertions(+), 6 deletions(-)
diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h
index 7f5b244bde3..3a9d31ea9df 100644
--- a/target/arm/cpu-qom.h
+++ b/target/arm/cpu-qom.h
@@ -76,6 +76,7 @@ void arm_gt_ptimer_cb(void *opaque);
void arm_gt_vtimer_cb(void *opaque);
void arm_gt_htimer_cb(void *opaque);
void arm_gt_stimer_cb(void *opaque);
+void arm_gt_hvtimer_cb(void *opaque);
=20
#define ARM_AFF0_SHIFT 0
#define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 68e11f0eda3..ded1e8e0a89 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -144,11 +144,12 @@ typedef struct ARMGenericTimer {
uint64_t ctl; /* Timer Control register */
} ARMGenericTimer;
=20
-#define GTIMER_PHYS 0
-#define GTIMER_VIRT 1
-#define GTIMER_HYP 2
-#define GTIMER_SEC 3
-#define NUM_GTIMERS 4
+#define GTIMER_PHYS 0
+#define GTIMER_VIRT 1
+#define GTIMER_HYP 2
+#define GTIMER_SEC 3
+#define GTIMER_HYPVIRT 4
+#define NUM_GTIMERS 5
=20
typedef struct {
uint64_t raw_tcr;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index f86e71a260d..1ecf2adb6a9 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1272,7 +1272,6 @@ static void arm_cpu_realizefn(DeviceState *dev, Error=
**errp)
}
}
=20
-
{
uint64_t scale;
=20
@@ -1295,6 +1294,8 @@ static void arm_cpu_realizefn(DeviceState *dev, Error=
**errp)
arm_gt_htimer_cb, cpu);
cpu->gt_timer[GTIMER_SEC] =3D timer_new(QEMU_CLOCK_VIRTUAL, scale,
arm_gt_stimer_cb, cpu);
+ cpu->gt_timer[GTIMER_HYPVIRT] =3D timer_new(QEMU_CLOCK_VIRTUAL, sc=
ale,
+ arm_gt_hvtimer_cb, cpu);
}
#endif
=20
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 72b336e3b5d..996865a3a20 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -2556,6 +2556,7 @@ static uint64_t gt_tval_read(CPUARMState *env, const =
ARMCPRegInfo *ri,
=20
switch (timeridx) {
case GTIMER_VIRT:
+ case GTIMER_HYPVIRT:
offset =3D gt_virt_cnt_offset(env);
break;
}
@@ -2572,6 +2573,7 @@ static void gt_tval_write(CPUARMState *env, const ARM=
CPRegInfo *ri,
=20
switch (timeridx) {
case GTIMER_VIRT:
+ case GTIMER_HYPVIRT:
offset =3D gt_virt_cnt_offset(env);
break;
}
@@ -2727,6 +2729,34 @@ static void gt_sec_ctl_write(CPUARMState *env, const=
ARMCPRegInfo *ri,
gt_ctl_write(env, ri, GTIMER_SEC, value);
}
=20
+static void gt_hv_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+ gt_timer_reset(env, ri, GTIMER_HYPVIRT);
+}
+
+static void gt_hv_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+ gt_cval_write(env, ri, GTIMER_HYPVIRT, value);
+}
+
+static uint64_t gt_hv_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+ return gt_tval_read(env, ri, GTIMER_HYPVIRT);
+}
+
+static void gt_hv_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+ gt_tval_write(env, ri, GTIMER_HYPVIRT, value);
+}
+
+static void gt_hv_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+ gt_ctl_write(env, ri, GTIMER_HYPVIRT, value);
+}
+
void arm_gt_ptimer_cb(void *opaque)
{
ARMCPU *cpu =3D opaque;
@@ -2755,6 +2785,13 @@ void arm_gt_stimer_cb(void *opaque)
gt_recalc_timer(cpu, GTIMER_SEC);
}
=20
+void arm_gt_hvtimer_cb(void *opaque)
+{
+ ARMCPU *cpu =3D opaque;
+
+ gt_recalc_timer(cpu, GTIMER_HYPVIRT);
+}
+
static void arm_gt_cntfrq_reset(CPUARMState *env, const ARMCPRegInfo *opaq=
ue)
{
ARMCPU *cpu =3D env_archcpu(env);
@@ -6164,6 +6201,25 @@ static const ARMCPRegInfo vhe_reginfo[] =3D {
.opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 1,
.access =3D PL2_RW, .writefn =3D vmsa_tcr_ttbr_el2_write,
.fieldoffset =3D offsetof(CPUARMState, cp15.ttbr1_el[2]) },
+#ifndef CONFIG_USER_ONLY
+ { .name =3D "CNTHV_CVAL_EL2", .state =3D ARM_CP_STATE_AA64,
+ .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 3, .opc2 =3D 2,
+ .fieldoffset =3D
+ offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYPVIRT].cval),
+ .type =3D ARM_CP_IO, .access =3D PL2_RW,
+ .writefn =3D gt_hv_cval_write, .raw_writefn =3D raw_write },
+ { .name =3D "CNTHV_TVAL_EL2", .state =3D ARM_CP_STATE_BOTH,
+ .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 3, .opc2 =3D 0,
+ .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL2_RW,
+ .resetfn =3D gt_hv_timer_reset,
+ .readfn =3D gt_hv_tval_read, .writefn =3D gt_hv_tval_write },
+ { .name =3D "CNTHV_CTL_EL2", .state =3D ARM_CP_STATE_BOTH,
+ .type =3D ARM_CP_IO,
+ .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 3, .opc2 =3D 1,
+ .access =3D PL2_RW,
+ .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYPVIRT=
].ctl),
+ .writefn =3D gt_hv_ctl_write, .raw_writefn =3D raw_write },
+#endif
REGINFO_SENTINEL
};
=20
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 27/48] target/arm: Update timer access for VHE
Date: Fri, 7 Feb 2020 14:33:22 +0000
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Tested-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 102 +++++++++++++++++++++++++++++++++++---------
1 file changed, 81 insertions(+), 21 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 996865a3a20..992ab2a15f1 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -2324,10 +2324,18 @@ static CPAccessResult gt_cntfrq_access(CPUARMState =
*env, const ARMCPRegInfo *ri,
* Writable only at the highest implemented exception level.
*/
int el =3D arm_current_el(env);
+ uint64_t hcr;
+ uint32_t cntkctl;
=20
switch (el) {
case 0:
- if (!extract32(env->cp15.c14_cntkctl, 0, 2)) {
+ hcr =3D arm_hcr_el2_eff(env);
+ if ((hcr & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)) {
+ cntkctl =3D env->cp15.cnthctl_el2;
+ } else {
+ cntkctl =3D env->cp15.c14_cntkctl;
+ }
+ if (!extract32(cntkctl, 0, 2)) {
return CP_ACCESS_TRAP;
}
break;
@@ -2355,17 +2363,47 @@ static CPAccessResult gt_counter_access(CPUARMState=
*env, int timeridx,
{
unsigned int cur_el =3D arm_current_el(env);
bool secure =3D arm_is_secure(env);
+ uint64_t hcr =3D arm_hcr_el2_eff(env);
=20
- /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
- if (cur_el =3D=3D 0 &&
- !extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
- return CP_ACCESS_TRAP;
- }
+ switch (cur_el) {
+ case 0:
+ /* If HCR_EL2.<E2H,TGE> =3D=3D '11': check CNTHCTL_EL2.EL0[PV]CTEN=
. */
+ if ((hcr & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)) {
+ return (extract32(env->cp15.cnthctl_el2, timeridx, 1)
+ ? CP_ACCESS_OK : CP_ACCESS_TRAP_EL2);
+ }
=20
- if (arm_feature(env, ARM_FEATURE_EL2) &&
- timeridx =3D=3D GTIMER_PHYS && !secure && cur_el < 2 &&
- !extract32(env->cp15.cnthctl_el2, 0, 1)) {
- return CP_ACCESS_TRAP_EL2;
+ /* CNT[PV]CT: not visible from PL0 if EL0[PV]CTEN is zero */
+ if (!extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
+ return CP_ACCESS_TRAP;
+ }
+
+ /* If HCR_EL2.<E2H,TGE> =3D=3D '10': check CNTHCTL_EL2.EL1PCTEN. */
+ if (hcr & HCR_E2H) {
+ if (timeridx =3D=3D GTIMER_PHYS &&
+ !extract32(env->cp15.cnthctl_el2, 10, 1)) {
+ return CP_ACCESS_TRAP_EL2;
+ }
+ } else {
+ /* If HCR_EL2.<E2H> =3D=3D 0: check CNTHCTL_EL2.EL1PCEN. */
+ if (arm_feature(env, ARM_FEATURE_EL2) &&
+ timeridx =3D=3D GTIMER_PHYS && !secure &&
+ !extract32(env->cp15.cnthctl_el2, 1, 1)) {
+ return CP_ACCESS_TRAP_EL2;
+ }
+ }
+ break;
+
+ case 1:
+ /* Check CNTHCTL_EL2.EL1PCTEN, which changes location based on E2H=
. */
+ if (arm_feature(env, ARM_FEATURE_EL2) &&
+ timeridx =3D=3D GTIMER_PHYS && !secure &&
+ (hcr & HCR_E2H
+ ? !extract32(env->cp15.cnthctl_el2, 10, 1)
+ : !extract32(env->cp15.cnthctl_el2, 0, 1))) {
+ return CP_ACCESS_TRAP_EL2;
+ }
+ break;
}
return CP_ACCESS_OK;
}
@@ -2375,19 +2413,41 @@ static CPAccessResult gt_timer_access(CPUARMState *=
env, int timeridx,
{
unsigned int cur_el =3D arm_current_el(env);
bool secure =3D arm_is_secure(env);
+ uint64_t hcr =3D arm_hcr_el2_eff(env);
=20
- /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
- * EL0[PV]TEN is zero.
- */
- if (cur_el =3D=3D 0 &&
- !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
- return CP_ACCESS_TRAP;
- }
+ switch (cur_el) {
+ case 0:
+ if ((hcr & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)) {
+ /* If HCR_EL2.<E2H,TGE> =3D=3D '11': check CNTHCTL_EL2.EL0[PV]=
TEN. */
+ return (extract32(env->cp15.cnthctl_el2, 9 - timeridx, 1)
+ ? CP_ACCESS_OK : CP_ACCESS_TRAP_EL2);
+ }
=20
- if (arm_feature(env, ARM_FEATURE_EL2) &&
- timeridx =3D=3D GTIMER_PHYS && !secure && cur_el < 2 &&
- !extract32(env->cp15.cnthctl_el2, 1, 1)) {
- return CP_ACCESS_TRAP_EL2;
+ /*
+ * CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from
+ * EL0 if EL0[PV]TEN is zero.
+ */
+ if (!extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
+ return CP_ACCESS_TRAP;
+ }
+ /* fall through */
+
+ case 1:
+ if (arm_feature(env, ARM_FEATURE_EL2) &&
+ timeridx =3D=3D GTIMER_PHYS && !secure) {
+ if (hcr & HCR_E2H) {
+ /* If HCR_EL2.<E2H,TGE> =3D=3D '10': check CNTHCTL_EL2.EL1=
PTEN. */
+ if (!extract32(env->cp15.cnthctl_el2, 11, 1)) {
+ return CP_ACCESS_TRAP_EL2;
+ }
+ } else {
+ /* If HCR_EL2.<E2H> =3D=3D 0: check CNTHCTL_EL2.EL1PCEN. */
+ if (!extract32(env->cp15.cnthctl_el2, 1, 1)) {
+ return CP_ACCESS_TRAP_EL2;
+ }
+ }
+ }
+ break;
}
return CP_ACCESS_OK;
}
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 28/48] target/arm: Update define_one_arm_cp_reg_with_opaque for
VHE
Date: Fri, 7 Feb 2020 14:33:23 +0000
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From: Richard Henderson <richard.henderson@linaro.org>
For ARMv8.1, op1 =3D=3D 5 is reserved for EL2 aliases of
EL1 and EL0 registers.
Tested-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200206105448.4726-28-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 992ab2a15f1..2aa04d06131 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7586,13 +7586,10 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
mask =3D PL0_RW;
break;
case 4:
+ case 5:
/* min_EL EL2 */
mask =3D PL2_RW;
break;
- case 5:
- /* unallocated encoding, so not possible */
- assert(false);
- break;
case 6:
/* min_EL EL3 */
mask =3D PL3_RW;
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 29/48] target/arm: Add VHE system register redirection and
aliasing
Date: Fri, 7 Feb 2020 14:33:24 +0000
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From: Richard Henderson <richard.henderson@linaro.org>
Several of the EL1/0 registers are redirected to the EL2 version when in
EL2 and HCR_EL2.E2H is set. Many of these registers have side effects.
Link together the two ARMCPRegInfo structures after they have been
properly instantiated. Install common dispatch routines to all of the
relevant registers.
The same set of registers that are redirected also have additional
EL12/EL02 aliases created to access the original register that was
redirected.
Omit the generic timer registers from redirection here, because we'll
need multiple kinds of redirection from both EL0 and EL2.
Tested-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200206105448.4726-29-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 13 ++++
target/arm/helper.c | 162 ++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 175 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index ded1e8e0a89..d091a7e2e87 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -2576,6 +2576,19 @@ struct ARMCPRegInfo {
* fieldoffset is 0 then no reset will be done.
*/
CPResetFn *resetfn;
+
+ /*
+ * "Original" writefn and readfn.
+ * For ARMv8.1-VHE register aliases, we overwrite the read/write
+ * accessor functions of various EL1/EL0 to perform the runtime
+ * check for which sysreg should actually be modified, and then
+ * forwards the operation. Before overwriting the accessors,
+ * the original function is copied here, so that accesses that
+ * really do go to the EL1/EL0 version proceed normally.
+ * (The corresponding EL2 register is linked via opaque.)
+ */
+ CPReadFn *orig_readfn;
+ CPWriteFn *orig_writefn;
};
=20
/* Macros which are lvalues for the field in CPUARMState for the
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 2aa04d06131..8f7620f2434 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -5358,6 +5358,158 @@ static const ARMCPRegInfo el3_cp_reginfo[] =3D {
REGINFO_SENTINEL
};
=20
+#ifndef CONFIG_USER_ONLY
+/* Test if system register redirection is to occur in the current state. =
*/
+static bool redirect_for_e2h(CPUARMState *env)
+{
+ return arm_current_el(env) =3D=3D 2 && (arm_hcr_el2_eff(env) & HCR_E2H=
);
+}
+
+static uint64_t el2_e2h_read(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+ CPReadFn *readfn;
+
+ if (redirect_for_e2h(env)) {
+ /* Switch to the saved EL2 version of the register. */
+ ri =3D ri->opaque;
+ readfn =3D ri->readfn;
+ } else {
+ readfn =3D ri->orig_readfn;
+ }
+ if (readfn =3D=3D NULL) {
+ readfn =3D raw_read;
+ }
+ return readfn(env, ri);
+}
+
+static void el2_e2h_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+ CPWriteFn *writefn;
+
+ if (redirect_for_e2h(env)) {
+ /* Switch to the saved EL2 version of the register. */
+ ri =3D ri->opaque;
+ writefn =3D ri->writefn;
+ } else {
+ writefn =3D ri->orig_writefn;
+ }
+ if (writefn =3D=3D NULL) {
+ writefn =3D raw_write;
+ }
+ writefn(env, ri, value);
+}
+
+static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu)
+{
+ struct E2HAlias {
+ uint32_t src_key, dst_key, new_key;
+ const char *src_name, *dst_name, *new_name;
+ bool (*feature)(const ARMISARegisters *id);
+ };
+
+#define K(op0, op1, crn, crm, op2) \
+ ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2)
+
+ static const struct E2HAlias aliases[] =3D {
+ { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0),
+ "SCTLR", "SCTLR_EL2", "SCTLR_EL12" },
+ { K(3, 0, 1, 0, 2), K(3, 4, 1, 1, 2), K(3, 5, 1, 0, 2),
+ "CPACR", "CPTR_EL2", "CPACR_EL12" },
+ { K(3, 0, 2, 0, 0), K(3, 4, 2, 0, 0), K(3, 5, 2, 0, 0),
+ "TTBR0_EL1", "TTBR0_EL2", "TTBR0_EL12" },
+ { K(3, 0, 2, 0, 1), K(3, 4, 2, 0, 1), K(3, 5, 2, 0, 1),
+ "TTBR1_EL1", "TTBR1_EL2", "TTBR1_EL12" },
+ { K(3, 0, 2, 0, 2), K(3, 4, 2, 0, 2), K(3, 5, 2, 0, 2),
+ "TCR_EL1", "TCR_EL2", "TCR_EL12" },
+ { K(3, 0, 4, 0, 0), K(3, 4, 4, 0, 0), K(3, 5, 4, 0, 0),
+ "SPSR_EL1", "SPSR_EL2", "SPSR_EL12" },
+ { K(3, 0, 4, 0, 1), K(3, 4, 4, 0, 1), K(3, 5, 4, 0, 1),
+ "ELR_EL1", "ELR_EL2", "ELR_EL12" },
+ { K(3, 0, 5, 1, 0), K(3, 4, 5, 1, 0), K(3, 5, 5, 1, 0),
+ "AFSR0_EL1", "AFSR0_EL2", "AFSR0_EL12" },
+ { K(3, 0, 5, 1, 1), K(3, 4, 5, 1, 1), K(3, 5, 5, 1, 1),
+ "AFSR1_EL1", "AFSR1_EL2", "AFSR1_EL12" },
+ { K(3, 0, 5, 2, 0), K(3, 4, 5, 2, 0), K(3, 5, 5, 2, 0),
+ "ESR_EL1", "ESR_EL2", "ESR_EL12" },
+ { K(3, 0, 6, 0, 0), K(3, 4, 6, 0, 0), K(3, 5, 6, 0, 0),
+ "FAR_EL1", "FAR_EL2", "FAR_EL12" },
+ { K(3, 0, 10, 2, 0), K(3, 4, 10, 2, 0), K(3, 5, 10, 2, 0),
+ "MAIR_EL1", "MAIR_EL2", "MAIR_EL12" },
+ { K(3, 0, 10, 3, 0), K(3, 4, 10, 3, 0), K(3, 5, 10, 3, 0),
+ "AMAIR0", "AMAIR_EL2", "AMAIR_EL12" },
+ { K(3, 0, 12, 0, 0), K(3, 4, 12, 0, 0), K(3, 5, 12, 0, 0),
+ "VBAR", "VBAR_EL2", "VBAR_EL12" },
+ { K(3, 0, 13, 0, 1), K(3, 4, 13, 0, 1), K(3, 5, 13, 0, 1),
+ "CONTEXTIDR_EL1", "CONTEXTIDR_EL2", "CONTEXTIDR_EL12" },
+ { K(3, 0, 14, 1, 0), K(3, 4, 14, 1, 0), K(3, 5, 14, 1, 0),
+ "CNTKCTL", "CNTHCTL_EL2", "CNTKCTL_EL12" },
+
+ /*
+ * Note that redirection of ZCR is mentioned in the description
+ * of ZCR_EL2, and aliasing in the description of ZCR_EL1, but
+ * not in the summary table.
+ */
+ { K(3, 0, 1, 2, 0), K(3, 4, 1, 2, 0), K(3, 5, 1, 2, 0),
+ "ZCR_EL1", "ZCR_EL2", "ZCR_EL12", isar_feature_aa64_sve },
+
+ /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */
+ /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */
+ };
+#undef K
+
+ size_t i;
+
+ for (i =3D 0; i < ARRAY_SIZE(aliases); i++) {
+ const struct E2HAlias *a =3D &aliases[i];
+ ARMCPRegInfo *src_reg, *dst_reg;
+
+ if (a->feature && !a->feature(&cpu->isar)) {
+ continue;
+ }
+
+ src_reg =3D g_hash_table_lookup(cpu->cp_regs, &a->src_key);
+ dst_reg =3D g_hash_table_lookup(cpu->cp_regs, &a->dst_key);
+ g_assert(src_reg !=3D NULL);
+ g_assert(dst_reg !=3D NULL);
+
+ /* Cross-compare names to detect typos in the keys. */
+ g_assert(strcmp(src_reg->name, a->src_name) =3D=3D 0);
+ g_assert(strcmp(dst_reg->name, a->dst_name) =3D=3D 0);
+
+ /* None of the core system registers use opaque; we will. */
+ g_assert(src_reg->opaque =3D=3D NULL);
+
+ /* Create alias before redirection so we dup the right data. */
+ if (a->new_key) {
+ ARMCPRegInfo *new_reg =3D g_memdup(src_reg, sizeof(ARMCPRegInf=
o));
+ uint32_t *new_key =3D g_memdup(&a->new_key, sizeof(uint32_t));
+ bool ok;
+
+ new_reg->name =3D a->new_name;
+ new_reg->type |=3D ARM_CP_ALIAS;
+ /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */
+ new_reg->access &=3D PL2_RW | PL3_RW;
+
+ ok =3D g_hash_table_insert(cpu->cp_regs, new_key, new_reg);
+ g_assert(ok);
+ }
+
+ src_reg->opaque =3D dst_reg;
+ src_reg->orig_readfn =3D src_reg->readfn ?: raw_read;
+ src_reg->orig_writefn =3D src_reg->writefn ?: raw_write;
+ if (!src_reg->raw_readfn) {
+ src_reg->raw_readfn =3D raw_read;
+ }
+ if (!src_reg->raw_writefn) {
+ src_reg->raw_writefn =3D raw_write;
+ }
+ src_reg->readfn =3D el2_e2h_read;
+ src_reg->writefn =3D el2_e2h_write;
+ }
+}
+#endif
+
static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo =
*ri,
bool isread)
{
@@ -7291,6 +7443,16 @@ void register_cp_regs_for_features(ARMCPU *cpu)
: cpu_isar_feature(aa32_predinv, cpu)) {
define_arm_cp_regs(cpu, predinv_reginfo);
}
+
+#ifndef CONFIG_USER_ONLY
+ /*
+ * Register redirections and aliases must be done last,
+ * after the registers from the other extensions have been defined.
+ */
+ if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu=
)) {
+ define_arm_vh_e2h_redirects_aliases(cpu);
+ }
+#endif
}
=20
void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 30/48] target/arm: Add VHE timer register redirection and
aliasing
Date: Fri, 7 Feb 2020 14:33:25 +0000
Message-Id: <20200207143343.30322-31-peter.maydell@linaro.org>
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From: Richard Henderson <richard.henderson@linaro.org>
Apart from the wholesale redirection that HCR_EL2.E2H performs
for EL2, there's a separate redirection specific to the timers
that happens for EL0 when running in the EL2&0 regime.
Tested-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200206105448.4726-30-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 181 +++++++++++++++++++++++++++++++++++++++++---
1 file changed, 169 insertions(+), 12 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 8f7620f2434..cfa6ce59dc8 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -2695,6 +2695,70 @@ static void gt_phys_ctl_write(CPUARMState *env, cons=
t ARMCPRegInfo *ri,
gt_ctl_write(env, ri, GTIMER_PHYS, value);
}
=20
+static int gt_phys_redir_timeridx(CPUARMState *env)
+{
+ switch (arm_mmu_idx(env)) {
+ case ARMMMUIdx_E20_0:
+ case ARMMMUIdx_E20_2:
+ return GTIMER_HYP;
+ default:
+ return GTIMER_PHYS;
+ }
+}
+
+static int gt_virt_redir_timeridx(CPUARMState *env)
+{
+ switch (arm_mmu_idx(env)) {
+ case ARMMMUIdx_E20_0:
+ case ARMMMUIdx_E20_2:
+ return GTIMER_HYPVIRT;
+ default:
+ return GTIMER_VIRT;
+ }
+}
+
+static uint64_t gt_phys_redir_cval_read(CPUARMState *env,
+ const ARMCPRegInfo *ri)
+{
+ int timeridx =3D gt_phys_redir_timeridx(env);
+ return env->cp15.c14_timer[timeridx].cval;
+}
+
+static void gt_phys_redir_cval_write(CPUARMState *env, const ARMCPRegInfo =
*ri,
+ uint64_t value)
+{
+ int timeridx =3D gt_phys_redir_timeridx(env);
+ gt_cval_write(env, ri, timeridx, value);
+}
+
+static uint64_t gt_phys_redir_tval_read(CPUARMState *env,
+ const ARMCPRegInfo *ri)
+{
+ int timeridx =3D gt_phys_redir_timeridx(env);
+ return gt_tval_read(env, ri, timeridx);
+}
+
+static void gt_phys_redir_tval_write(CPUARMState *env, const ARMCPRegInfo =
*ri,
+ uint64_t value)
+{
+ int timeridx =3D gt_phys_redir_timeridx(env);
+ gt_tval_write(env, ri, timeridx, value);
+}
+
+static uint64_t gt_phys_redir_ctl_read(CPUARMState *env,
+ const ARMCPRegInfo *ri)
+{
+ int timeridx =3D gt_phys_redir_timeridx(env);
+ return env->cp15.c14_timer[timeridx].ctl;
+}
+
+static void gt_phys_redir_ctl_write(CPUARMState *env, const ARMCPRegInfo *=
ri,
+ uint64_t value)
+{
+ int timeridx =3D gt_phys_redir_timeridx(env);
+ gt_ctl_write(env, ri, timeridx, value);
+}
+
static void gt_virt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
{
gt_timer_reset(env, ri, GTIMER_VIRT);
@@ -2733,6 +2797,48 @@ static void gt_cntvoff_write(CPUARMState *env, const=
ARMCPRegInfo *ri,
gt_recalc_timer(cpu, GTIMER_VIRT);
}
=20
+static uint64_t gt_virt_redir_cval_read(CPUARMState *env,
+ const ARMCPRegInfo *ri)
+{
+ int timeridx =3D gt_virt_redir_timeridx(env);
+ return env->cp15.c14_timer[timeridx].cval;
+}
+
+static void gt_virt_redir_cval_write(CPUARMState *env, const ARMCPRegInfo =
*ri,
+ uint64_t value)
+{
+ int timeridx =3D gt_virt_redir_timeridx(env);
+ gt_cval_write(env, ri, timeridx, value);
+}
+
+static uint64_t gt_virt_redir_tval_read(CPUARMState *env,
+ const ARMCPRegInfo *ri)
+{
+ int timeridx =3D gt_virt_redir_timeridx(env);
+ return gt_tval_read(env, ri, timeridx);
+}
+
+static void gt_virt_redir_tval_write(CPUARMState *env, const ARMCPRegInfo =
*ri,
+ uint64_t value)
+{
+ int timeridx =3D gt_virt_redir_timeridx(env);
+ gt_tval_write(env, ri, timeridx, value);
+}
+
+static uint64_t gt_virt_redir_ctl_read(CPUARMState *env,
+ const ARMCPRegInfo *ri)
+{
+ int timeridx =3D gt_virt_redir_timeridx(env);
+ return env->cp15.c14_timer[timeridx].ctl;
+}
+
+static void gt_virt_redir_ctl_write(CPUARMState *env, const ARMCPRegInfo *=
ri,
+ uint64_t value)
+{
+ int timeridx =3D gt_virt_redir_timeridx(env);
+ gt_ctl_write(env, ri, timeridx, value);
+}
+
static void gt_hyp_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
{
gt_timer_reset(env, ri, GTIMER_HYP);
@@ -2889,7 +2995,8 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] =
=3D {
.accessfn =3D gt_ptimer_access,
.fieldoffset =3D offsetoflow32(CPUARMState,
cp15.c14_timer[GTIMER_PHYS].ctl),
- .writefn =3D gt_phys_ctl_write, .raw_writefn =3D raw_write,
+ .readfn =3D gt_phys_redir_ctl_read, .raw_readfn =3D raw_read,
+ .writefn =3D gt_phys_redir_ctl_write, .raw_writefn =3D raw_write,
},
{ .name =3D "CNTP_CTL_S",
.cp =3D 15, .crn =3D 14, .crm =3D 2, .opc1 =3D 0, .opc2 =3D 1,
@@ -2906,14 +3013,16 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[=
] =3D {
.accessfn =3D gt_ptimer_access,
.fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].c=
tl),
.resetvalue =3D 0,
- .writefn =3D gt_phys_ctl_write, .raw_writefn =3D raw_write,
+ .readfn =3D gt_phys_redir_ctl_read, .raw_readfn =3D raw_read,
+ .writefn =3D gt_phys_redir_ctl_write, .raw_writefn =3D raw_write,
},
{ .name =3D "CNTV_CTL", .cp =3D 15, .crn =3D 14, .crm =3D 3, .opc1 =3D=
0, .opc2 =3D 1,
.type =3D ARM_CP_IO | ARM_CP_ALIAS, .access =3D PL0_RW,
.accessfn =3D gt_vtimer_access,
.fieldoffset =3D offsetoflow32(CPUARMState,
cp15.c14_timer[GTIMER_VIRT].ctl),
- .writefn =3D gt_virt_ctl_write, .raw_writefn =3D raw_write,
+ .readfn =3D gt_virt_redir_ctl_read, .raw_readfn =3D raw_read,
+ .writefn =3D gt_virt_redir_ctl_write, .raw_writefn =3D raw_write,
},
{ .name =3D "CNTV_CTL_EL0", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 3, .opc2 =3D 1,
@@ -2921,14 +3030,15 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[=
] =3D {
.accessfn =3D gt_vtimer_access,
.fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].c=
tl),
.resetvalue =3D 0,
- .writefn =3D gt_virt_ctl_write, .raw_writefn =3D raw_write,
+ .readfn =3D gt_virt_redir_ctl_read, .raw_readfn =3D raw_read,
+ .writefn =3D gt_virt_redir_ctl_write, .raw_writefn =3D raw_write,
},
/* TimerValue views: a 32 bit downcounting view of the underlying stat=
e */
{ .name =3D "CNTP_TVAL", .cp =3D 15, .crn =3D 14, .crm =3D 2, .opc1 =
=3D 0, .opc2 =3D 0,
.secure =3D ARM_CP_SECSTATE_NS,
.type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL0_RW,
.accessfn =3D gt_ptimer_access,
- .readfn =3D gt_phys_tval_read, .writefn =3D gt_phys_tval_write,
+ .readfn =3D gt_phys_redir_tval_read, .writefn =3D gt_phys_redir_tval=
_write,
},
{ .name =3D "CNTP_TVAL_S",
.cp =3D 15, .crn =3D 14, .crm =3D 2, .opc1 =3D 0, .opc2 =3D 0,
@@ -2941,18 +3051,18 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[=
] =3D {
.opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 2, .opc2 =3D 0,
.type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL0_RW,
.accessfn =3D gt_ptimer_access, .resetfn =3D gt_phys_timer_reset,
- .readfn =3D gt_phys_tval_read, .writefn =3D gt_phys_tval_write,
+ .readfn =3D gt_phys_redir_tval_read, .writefn =3D gt_phys_redir_tval=
_write,
},
{ .name =3D "CNTV_TVAL", .cp =3D 15, .crn =3D 14, .crm =3D 3, .opc1 =
=3D 0, .opc2 =3D 0,
.type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL0_RW,
.accessfn =3D gt_vtimer_access,
- .readfn =3D gt_virt_tval_read, .writefn =3D gt_virt_tval_write,
+ .readfn =3D gt_virt_redir_tval_read, .writefn =3D gt_virt_redir_tval=
_write,
},
{ .name =3D "CNTV_TVAL_EL0", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 3, .opc2 =3D 0,
.type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL0_RW,
.accessfn =3D gt_vtimer_access, .resetfn =3D gt_virt_timer_reset,
- .readfn =3D gt_virt_tval_read, .writefn =3D gt_virt_tval_write,
+ .readfn =3D gt_virt_redir_tval_read, .writefn =3D gt_virt_redir_tval=
_write,
},
/* The counter itself */
{ .name =3D "CNTPCT", .cp =3D 15, .crm =3D 14, .opc1 =3D 0,
@@ -2982,7 +3092,8 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] =
=3D {
.type =3D ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
.fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].c=
val),
.accessfn =3D gt_ptimer_access,
- .writefn =3D gt_phys_cval_write, .raw_writefn =3D raw_write,
+ .readfn =3D gt_phys_redir_cval_read, .raw_readfn =3D raw_read,
+ .writefn =3D gt_phys_redir_cval_write, .raw_writefn =3D raw_write,
},
{ .name =3D "CNTP_CVAL_S", .cp =3D 15, .crm =3D 14, .opc1 =3D 2,
.secure =3D ARM_CP_SECSTATE_S,
@@ -2998,14 +3109,16 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[=
] =3D {
.type =3D ARM_CP_IO,
.fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].c=
val),
.resetvalue =3D 0, .accessfn =3D gt_ptimer_access,
- .writefn =3D gt_phys_cval_write, .raw_writefn =3D raw_write,
+ .readfn =3D gt_phys_redir_cval_read, .raw_readfn =3D raw_read,
+ .writefn =3D gt_phys_redir_cval_write, .raw_writefn =3D raw_write,
},
{ .name =3D "CNTV_CVAL", .cp =3D 15, .crm =3D 14, .opc1 =3D 3,
.access =3D PL0_RW,
.type =3D ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
.fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].c=
val),
.accessfn =3D gt_vtimer_access,
- .writefn =3D gt_virt_cval_write, .raw_writefn =3D raw_write,
+ .readfn =3D gt_virt_redir_cval_read, .raw_readfn =3D raw_read,
+ .writefn =3D gt_virt_redir_cval_write, .raw_writefn =3D raw_write,
},
{ .name =3D "CNTV_CVAL_EL0", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 3, .opc2 =3D 2,
@@ -3013,7 +3126,8 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] =
=3D {
.type =3D ARM_CP_IO,
.fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].c=
val),
.resetvalue =3D 0, .accessfn =3D gt_vtimer_access,
- .writefn =3D gt_virt_cval_write, .raw_writefn =3D raw_write,
+ .readfn =3D gt_virt_redir_cval_read, .raw_readfn =3D raw_read,
+ .writefn =3D gt_virt_redir_cval_write, .raw_writefn =3D raw_write,
},
/* Secure timer -- this is actually restricted to only EL3
* and configurably Secure-EL1 via the accessfn.
@@ -3044,6 +3158,15 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[]=
=3D {
REGINFO_SENTINEL
};
=20
+static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri,
+ bool isread)
+{
+ if (!(arm_hcr_el2_eff(env) & HCR_E2H)) {
+ return CP_ACCESS_TRAP;
+ }
+ return CP_ACCESS_OK;
+}
+
#else
=20
/* In user-mode most of the generic timer registers are inaccessible
@@ -6431,6 +6554,40 @@ static const ARMCPRegInfo vhe_reginfo[] =3D {
.access =3D PL2_RW,
.fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYPVIRT=
].ctl),
.writefn =3D gt_hv_ctl_write, .raw_writefn =3D raw_write },
+ { .name =3D "CNTP_CTL_EL02", .state =3D ARM_CP_STATE_AA64,
+ .opc0 =3D 3, .opc1 =3D 5, .crn =3D 14, .crm =3D 2, .opc2 =3D 1,
+ .type =3D ARM_CP_IO | ARM_CP_ALIAS,
+ .access =3D PL2_RW, .accessfn =3D e2h_access,
+ .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].c=
tl),
+ .writefn =3D gt_phys_ctl_write, .raw_writefn =3D raw_write },
+ { .name =3D "CNTV_CTL_EL02", .state =3D ARM_CP_STATE_AA64,
+ .opc0 =3D 3, .opc1 =3D 5, .crn =3D 14, .crm =3D 3, .opc2 =3D 1,
+ .type =3D ARM_CP_IO | ARM_CP_ALIAS,
+ .access =3D PL2_RW, .accessfn =3D e2h_access,
+ .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].c=
tl),
+ .writefn =3D gt_virt_ctl_write, .raw_writefn =3D raw_write },
+ { .name =3D "CNTP_TVAL_EL02", .state =3D ARM_CP_STATE_AA64,
+ .opc0 =3D 3, .opc1 =3D 5, .crn =3D 14, .crm =3D 2, .opc2 =3D 0,
+ .type =3D ARM_CP_NO_RAW | ARM_CP_IO | ARM_CP_ALIAS,
+ .access =3D PL2_RW, .accessfn =3D e2h_access,
+ .readfn =3D gt_phys_tval_read, .writefn =3D gt_phys_tval_write },
+ { .name =3D "CNTV_TVAL_EL02", .state =3D ARM_CP_STATE_AA64,
+ .opc0 =3D 3, .opc1 =3D 5, .crn =3D 14, .crm =3D 3, .opc2 =3D 0,
+ .type =3D ARM_CP_NO_RAW | ARM_CP_IO | ARM_CP_ALIAS,
+ .access =3D PL2_RW, .accessfn =3D e2h_access,
+ .readfn =3D gt_virt_tval_read, .writefn =3D gt_virt_tval_write },
+ { .name =3D "CNTP_CVAL_EL02", .state =3D ARM_CP_STATE_AA64,
+ .opc0 =3D 3, .opc1 =3D 5, .crn =3D 14, .crm =3D 2, .opc2 =3D 2,
+ .type =3D ARM_CP_IO | ARM_CP_ALIAS,
+ .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].c=
val),
+ .access =3D PL2_RW, .accessfn =3D e2h_access,
+ .writefn =3D gt_phys_cval_write, .raw_writefn =3D raw_write },
+ { .name =3D "CNTV_CVAL_EL02", .state =3D ARM_CP_STATE_AA64,
+ .opc0 =3D 3, .opc1 =3D 5, .crn =3D 14, .crm =3D 3, .opc2 =3D 2,
+ .type =3D ARM_CP_IO | ARM_CP_ALIAS,
+ .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].c=
val),
+ .access =3D PL2_RW, .accessfn =3D e2h_access,
+ .writefn =3D gt_virt_cval_write, .raw_writefn =3D raw_write },
#endif
REGINFO_SENTINEL
};
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 31/48] target/arm: Flush tlb for ASID changes in EL2&0
translation regime
Date: Fri, 7 Feb 2020 14:33:26 +0000
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From: Richard Henderson <richard.henderson@linaro.org>
Since we only support a single ASID, flush the tlb when it changes.
Note that TCR_EL2, like TCR_EL1, has the A1 bit that chooses between
the two TTBR* registers for the location of the ASID.
Tested-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200206105448.4726-31-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 22 +++++++++++++++-------
1 file changed, 15 insertions(+), 7 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index cfa6ce59dc8..f9be6b052f0 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -3763,7 +3763,7 @@ static void vmsa_ttbcr_reset(CPUARMState *env, const =
ARMCPRegInfo *ri)
tcr->base_mask =3D 0xffffc000u;
}
=20
-static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
+static void vmsa_tcr_el12_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
ARMCPU *cpu =3D env_archcpu(env);
@@ -3789,7 +3789,17 @@ static void vmsa_ttbr_write(CPUARMState *env, const =
ARMCPRegInfo *ri,
static void vmsa_tcr_ttbr_el2_write(CPUARMState *env, const ARMCPRegInfo *=
ri,
uint64_t value)
{
- /* TODO: There are ASID fields in here with HCR_EL2.E2H */
+ /*
+ * If we are running with E2&0 regime, then an ASID is active.
+ * Flush if that might be changing. Note we're not checking
+ * TCR_EL2.A1 to know if this is really the TTBRx_EL2 that
+ * holds the active ASID, only checking the field that might.
+ */
+ if (extract64(raw_read(env, ri) ^ value, 48, 16) &&
+ (arm_hcr_el2_eff(env) & HCR_E2H)) {
+ tlb_flush_by_mmuidx(env_cpu(env),
+ ARMMMUIdxBit_E20_2 | ARMMMUIdxBit_E20_0);
+ }
raw_write(env, ri, value);
}
=20
@@ -3849,7 +3859,7 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] =3D {
offsetof(CPUARMState, cp15.ttbr1_ns) } },
{ .name =3D "TCR_EL1", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 3, .crn =3D 2, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 2,
- .access =3D PL1_RW, .writefn =3D vmsa_tcr_el1_write,
+ .access =3D PL1_RW, .writefn =3D vmsa_tcr_el12_write,
.resetfn =3D vmsa_ttbcr_reset, .raw_writefn =3D raw_write,
.fieldoffset =3D offsetof(CPUARMState, cp15.tcr_el[1]) },
{ .name =3D "TTBCR", .cp =3D 15, .crn =3D 2, .crm =3D 0, .opc1 =3D 0, =
.opc2 =3D 2,
@@ -5175,10 +5185,8 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D {
.resetvalue =3D 0 },
{ .name =3D "TCR_EL2", .state =3D ARM_CP_STATE_BOTH,
.opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 2,
- .access =3D PL2_RW,
- /* no .writefn needed as this can't cause an ASID change;
- * no .raw_writefn or .resetfn needed as we never use mask/base_mask
- */
+ .access =3D PL2_RW, .writefn =3D vmsa_tcr_el12_write,
+ /* no .raw_writefn or .resetfn needed as we never use mask/base_mask=
*/
.fieldoffset =3D offsetof(CPUARMState, cp15.tcr_el[2]) },
{ .name =3D "VTCR", .state =3D ARM_CP_STATE_AA32,
.cp =3D 15, .opc1 =3D 4, .crn =3D 2, .crm =3D 1, .opc2 =3D 2,
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 32/48] target/arm: Flush tlbs for E2&0 translation regime
Date: Fri, 7 Feb 2020 14:33:27 +0000
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From: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 25 ++++++++++++++++++-------
1 file changed, 18 insertions(+), 7 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index f9be6b052f0..3b7b459314d 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -4174,8 +4174,12 @@ static CPAccessResult aa64_cacheop_access(CPUARMStat=
e *env,
=20
static int vae1_tlbmask(CPUARMState *env)
{
+ /* Since we exclude secure first, we may read HCR_EL2 directly. */
if (arm_is_secure_below_el3(env)) {
return ARMMMUIdxBit_SE10_1 | ARMMMUIdxBit_SE10_0;
+ } else if ((env->cp15.hcr_el2 & (HCR_E2H | HCR_TGE))
+ =3D=3D (HCR_E2H | HCR_TGE)) {
+ return ARMMMUIdxBit_E20_2 | ARMMMUIdxBit_E20_0;
} else {
return ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_0;
}
@@ -4219,6 +4223,12 @@ static int alle1_tlbmask(CPUARMState *env)
}
}
=20
+static int e2_tlbmask(CPUARMState *env)
+{
+ /* TODO: ARMv8.4-SecEL2 */
+ return ARMMMUIdxBit_E20_0 | ARMMMUIdxBit_E20_2 | ARMMMUIdxBit_E2;
+}
+
static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
@@ -4231,10 +4241,10 @@ static void tlbi_aa64_alle1_write(CPUARMState *env,=
const ARMCPRegInfo *ri,
static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- ARMCPU *cpu =3D env_archcpu(env);
- CPUState *cs =3D CPU(cpu);
+ CPUState *cs =3D env_cpu(env);
+ int mask =3D e2_tlbmask(env);
=20
- tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E2);
+ tlb_flush_by_mmuidx(cs, mask);
}
=20
static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -4259,8 +4269,9 @@ static void tlbi_aa64_alle2is_write(CPUARMState *env,=
const ARMCPRegInfo *ri,
uint64_t value)
{
CPUState *cs =3D env_cpu(env);
+ int mask =3D e2_tlbmask(env);
=20
- tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E2);
+ tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);
}
=20
static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *=
ri,
@@ -4278,11 +4289,11 @@ static void tlbi_aa64_vae2_write(CPUARMState *env, =
const ARMCPRegInfo *ri,
* Currently handles both VAE2 and VALE2, since we don't support
* flush-last-level-only.
*/
- ARMCPU *cpu =3D env_archcpu(env);
- CPUState *cs =3D CPU(cpu);
+ CPUState *cs =3D env_cpu(env);
+ int mask =3D e2_tlbmask(env);
uint64_t pageaddr =3D sextract64(value << 12, 0, 56);
=20
- tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E2);
+ tlb_flush_page_by_mmuidx(cs, pageaddr, mask);
}
=20
static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 33/48] target/arm: Update arm_phys_excp_target_el for TGE
Date: Fri, 7 Feb 2020 14:33:28 +0000
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From: Richard Henderson <richard.henderson@linaro.org>
The TGE bit routes all asynchronous exceptions to EL2.
Tested-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200206105448.4726-33-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 3b7b459314d..56a62b11d09 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -8446,6 +8446,12 @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint3=
2_t excp_idx,
break;
};
=20
+ /*
+ * For these purposes, TGE and AMO/IMO/FMO both force the
+ * interrupt to EL2. Fold TGE into the bit extracted above.
+ */
+ hcr |=3D (hcr_el2 & HCR_TGE) !=3D 0;
+
/* Perform a table-lookup for the target EL given the current state */
target_el =3D target_el_table[is64][scr][rw][hcr][secure][cur_el];
=20
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 34/48] target/arm: Update {fp,sve}_exception_el for VHE
Date: Fri, 7 Feb 2020 14:33:29 +0000
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From: Richard Henderson <richard.henderson@linaro.org>
When TGE+E2H are both set, CPACR_EL1 is ignored.
Tested-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200206105448.4726-34-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 53 ++++++++++++++++++++++++---------------------
1 file changed, 28 insertions(+), 25 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 56a62b11d09..9627b4aab15 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -5791,7 +5791,9 @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] =3D=
{
int sve_exception_el(CPUARMState *env, int el)
{
#ifndef CONFIG_USER_ONLY
- if (el <=3D 1) {
+ uint64_t hcr_el2 =3D arm_hcr_el2_eff(env);
+
+ if (el <=3D 1 && (hcr_el2 & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HCR_T=
GE)) {
bool disabled =3D false;
=20
/* The CPACR.ZEN controls traps to EL1:
@@ -5806,8 +5808,7 @@ int sve_exception_el(CPUARMState *env, int el)
}
if (disabled) {
/* route_to_el2 */
- return (arm_feature(env, ARM_FEATURE_EL2)
- && (arm_hcr_el2_eff(env) & HCR_TGE) ? 2 : 1);
+ return hcr_el2 & HCR_TGE ? 2 : 1;
}
=20
/* Check CPACR.FPEN. */
@@ -11691,8 +11692,6 @@ uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val,=
uint32_t bytes)
int fp_exception_el(CPUARMState *env, int cur_el)
{
#ifndef CONFIG_USER_ONLY
- int fpen;
-
/* CPACR and the CPTR registers don't exist before v6, so FP is
* always accessible
*/
@@ -11720,30 +11719,34 @@ int fp_exception_el(CPUARMState *env, int cur_el)
* 0, 2 : trap EL0 and EL1/PL1 accesses
* 1 : trap only EL0 accesses
* 3 : trap no accesses
+ * This register is ignored if E2H+TGE are both set.
*/
- fpen =3D extract32(env->cp15.cpacr_el1, 20, 2);
- switch (fpen) {
- case 0:
- case 2:
- if (cur_el =3D=3D 0 || cur_el =3D=3D 1) {
- /* Trap to PL1, which might be EL1 or EL3 */
- if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) {
+ if ((arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HCR_T=
GE)) {
+ int fpen =3D extract32(env->cp15.cpacr_el1, 20, 2);
+
+ switch (fpen) {
+ case 0:
+ case 2:
+ if (cur_el =3D=3D 0 || cur_el =3D=3D 1) {
+ /* Trap to PL1, which might be EL1 or EL3 */
+ if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) {
+ return 3;
+ }
+ return 1;
+ }
+ if (cur_el =3D=3D 3 && !is_a64(env)) {
+ /* Secure PL1 running at EL3 */
return 3;
}
- return 1;
+ break;
+ case 1:
+ if (cur_el =3D=3D 0) {
+ return 1;
+ }
+ break;
+ case 3:
+ break;
}
- if (cur_el =3D=3D 3 && !is_a64(env)) {
- /* Secure PL1 running at EL3 */
- return 3;
- }
- break;
- case 1:
- if (cur_el =3D=3D 0) {
- return 1;
- }
- break;
- case 3:
- break;
}
=20
/*
--=20
2.20.1
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To: qemu-devel@nongnu.org
Subject: [PULL 35/48] target/arm: check TGE and E2H flags for EL0 pauth traps
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From: Alex Benn=C3=A9e <alex.bennee@linaro.org>
According to ARM ARM we should only trap from the EL1&0 regime.
Tested-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200206105448.4726-35-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/pauth_helper.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c
index e0c401c4a9e..9746e32bf81 100644
--- a/target/arm/pauth_helper.c
+++ b/target/arm/pauth_helper.c
@@ -371,7 +371,10 @@ static void pauth_check_trap(CPUARMState *env, int el,=
uintptr_t ra)
if (el < 2 && arm_feature(env, ARM_FEATURE_EL2)) {
uint64_t hcr =3D arm_hcr_el2_eff(env);
bool trap =3D !(hcr & HCR_API);
- /* FIXME: ARMv8.1-VHE: trap only applies to EL1&0 regime. */
+ if (el =3D=3D 0) {
+ /* Trap only applies to EL1&0 regime. */
+ trap &=3D (hcr & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HCR_TGE);
+ }
/* FIXME: ARMv8.3-NV: HCR_NV trap takes precedence for ERETA[AB]. =
*/
if (trap) {
pauth_trap(env, 2, ra);
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 36/48] target/arm: Update get_a64_user_mem_index for VHE
Date: Fri, 7 Feb 2020 14:33:31 +0000
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From: Richard Henderson <richard.henderson@linaro.org>
The EL2&0 translation regime is affected by Load Register (unpriv).
The code structure used here will facilitate later changes in this
area for implementing UAO and NV.
Tested-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200206105448.4726-36-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 9 ++++----
target/arm/translate.h | 2 ++
target/arm/helper.c | 22 +++++++++++++++++++
target/arm/translate-a64.c | 44 ++++++++++++++++++++++++--------------
4 files changed, 57 insertions(+), 20 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index d091a7e2e87..2ed2667a170 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3214,10 +3214,10 @@ typedef ARMCPU ArchCPU;
* | | | TBFLAG_A32 | |
* | | +-----+----------+ TBFLAG_AM32 |
* | TBFLAG_ANY | |TBFLAG_M32| |
- * | | +-------------------------|
- * | | | TBFLAG_A64 |
- * +--------------+-----------+-------------------------+
- * 31 20 14 0
+ * | | +-+----------+--------------|
+ * | | | TBFLAG_A64 |
+ * +--------------+---------+---------------------------+
+ * 31 20 15 0
*
* Unless otherwise noted, these bits are cached in env->hflags.
*/
@@ -3283,6 +3283,7 @@ FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1)
FIELD(TBFLAG_A64, BT, 9, 1)
FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */
FIELD(TBFLAG_A64, TBID, 12, 2)
+FIELD(TBFLAG_A64, UNPRIV, 14, 1)
=20
static inline bool bswap_code(bool sctlr_b)
{
diff --git a/target/arm/translate.h b/target/arm/translate.h
index a32b6b1b3a9..5b167c416a2 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -73,6 +73,8 @@ typedef struct DisasContext {
* ie A64 LDX*, LDAX*, A32/T32 LDREX*, LDAEX*.
*/
bool is_ldex;
+ /* True if AccType_UNPRIV should be used for LDTR et al */
+ bool unpriv;
/* True if v8.3-PAuth is active. */
bool pauth_active;
/* True with v8.5-BTI and SCTLR_ELx.BT* set. */
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 9627b4aab15..ff2d957b7c6 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -12011,6 +12011,28 @@ static uint32_t rebuild_hflags_a64(CPUARMState *en=
v, int el, int fp_el,
}
}
=20
+ /* Compute the condition for using AccType_UNPRIV for LDTR et al. */
+ /* TODO: ARMv8.2-UAO */
+ switch (mmu_idx) {
+ case ARMMMUIdx_E10_1:
+ case ARMMMUIdx_SE10_1:
+ /* TODO: ARMv8.3-NV */
+ flags =3D FIELD_DP32(flags, TBFLAG_A64, UNPRIV, 1);
+ break;
+ case ARMMMUIdx_E20_2:
+ /* TODO: ARMv8.4-SecEL2 */
+ /*
+ * Note that E20_2 is gated by HCR_EL2.E2H =3D=3D 1, but E20_0 is
+ * gated by HCR_EL2.<E2H,TGE> =3D=3D '11', and so is LDTR.
+ */
+ if (env->cp15.hcr_el2 & HCR_TGE) {
+ flags =3D FIELD_DP32(flags, TBFLAG_A64, UNPRIV, 1);
+ }
+ break;
+ default:
+ break;
+ }
+
return rebuild_hflags_common(env, fp_el, mmu_idx, flags);
}
=20
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 3982e1988dc..6e82486884b 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -105,25 +105,36 @@ void a64_translate_init(void)
offsetof(CPUARMState, exclusive_high), "exclusive_high");
}
=20
-static inline int get_a64_user_mem_index(DisasContext *s)
+/*
+ * Return the core mmu_idx to use for A64 "unprivileged load/store" insns
+ */
+static int get_a64_user_mem_index(DisasContext *s)
{
- /* Return the core mmu_idx to use for A64 "unprivileged load/store" in=
sns:
- * if EL1, access as if EL0; otherwise access at current EL
+ /*
+ * If AccType_UNPRIV is not used, the insn uses AccType_NORMAL,
+ * which is the usual mmu_idx for this cpu state.
*/
- ARMMMUIdx useridx;
+ ARMMMUIdx useridx =3D s->mmu_idx;
=20
- switch (s->mmu_idx) {
- case ARMMMUIdx_E10_1:
- useridx =3D ARMMMUIdx_E10_0;
- break;
- case ARMMMUIdx_SE10_1:
- useridx =3D ARMMMUIdx_SE10_0;
- break;
- case ARMMMUIdx_Stage2:
- g_assert_not_reached();
- default:
- useridx =3D s->mmu_idx;
- break;
+ if (s->unpriv) {
+ /*
+ * We have pre-computed the condition for AccType_UNPRIV.
+ * Therefore we should never get here with a mmu_idx for
+ * which we do not know the corresponding user mmu_idx.
+ */
+ switch (useridx) {
+ case ARMMMUIdx_E10_1:
+ useridx =3D ARMMMUIdx_E10_0;
+ break;
+ case ARMMMUIdx_E20_2:
+ useridx =3D ARMMMUIdx_E20_0;
+ break;
+ case ARMMMUIdx_SE10_1:
+ useridx =3D ARMMMUIdx_SE10_0;
+ break;
+ default:
+ g_assert_not_reached();
+ }
}
return arm_to_core_mmu_idx(useridx);
}
@@ -14171,6 +14182,7 @@ static void aarch64_tr_init_disas_context(DisasCont=
extBase *dcbase,
dc->pauth_active =3D FIELD_EX32(tb_flags, TBFLAG_A64, PAUTH_ACTIVE);
dc->bt =3D FIELD_EX32(tb_flags, TBFLAG_A64, BT);
dc->btype =3D FIELD_EX32(tb_flags, TBFLAG_A64, BTYPE);
+ dc->unpriv =3D FIELD_EX32(tb_flags, TBFLAG_A64, UNPRIV);
dc->vec_len =3D 0;
dc->vec_stride =3D 0;
dc->cp_regs =3D arm_cpu->cp_regs;
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 37/48] target/arm: Update arm_cpu_do_interrupt_aarch64 for VHE
Date: Fri, 7 Feb 2020 14:33:32 +0000
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From: Richard Henderson <richard.henderson@linaro.org>
When VHE is enabled, the exception level below EL2 is not EL1,
but EL0, and so to identify the entry vector offset for exceptions
targeting EL2 we need to look at the width of EL0, not of EL1.
Tested-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200206105448.4726-37-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index ff2d957b7c6..7d15d5c933c 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -9017,14 +9017,19 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *=
cs)
* immediately lower than the target level is using AArch32 or AAr=
ch64
*/
bool is_aa64;
+ uint64_t hcr;
=20
switch (new_el) {
case 3:
is_aa64 =3D (env->cp15.scr_el3 & SCR_RW) !=3D 0;
break;
case 2:
- is_aa64 =3D (env->cp15.hcr_el2 & HCR_RW) !=3D 0;
- break;
+ hcr =3D arm_hcr_el2_eff(env);
+ if ((hcr & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HCR_TGE)) {
+ is_aa64 =3D (hcr & HCR_RW) !=3D 0;
+ break;
+ }
+ /* fall through */
case 1:
is_aa64 =3D is_a64(env);
break;
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 38/48] target/arm: Enable ARMv8.1-VHE in -cpu max
Date: Fri, 7 Feb 2020 14:33:33 +0000
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From: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200206105448.4726-38-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu64.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 2d97bf45e1e..c80fb5fd438 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -672,6 +672,7 @@ static void aarch64_max_initfn(Object *obj)
t =3D cpu->isar.id_aa64mmfr1;
t =3D FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */
t =3D FIELD_DP64(t, ID_AA64MMFR1, LO, 1);
+ t =3D FIELD_DP64(t, ID_AA64MMFR1, VH, 1);
cpu->isar.id_aa64mmfr1 =3D t;
=20
/* Replicate the same data to the 32-bit id registers. */
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 39/48] target/arm: Move arm_excp_unmasked to cpu.c
Date: Fri, 7 Feb 2020 14:33:34 +0000
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From: Richard Henderson <richard.henderson@linaro.org>
This inline function has one user in cpu.c, and need not be exposed
otherwise. Code movement only, with fixups for checkpatch.
Tested-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daud=C3=A9 <philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200206105448.4726-39-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 111 -------------------------------------------
target/arm/cpu.c | 119 +++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 119 insertions(+), 111 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 2ed2667a170..0b3036c484f 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -2709,117 +2709,6 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_s=
ync);
#define ARM_CPUID_TI915T 0x54029152
#define ARM_CPUID_TI925T 0x54029252
=20
-static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
- unsigned int target_el)
-{
- CPUARMState *env =3D cs->env_ptr;
- unsigned int cur_el =3D arm_current_el(env);
- bool secure =3D arm_is_secure(env);
- bool pstate_unmasked;
- int8_t unmasked =3D 0;
- uint64_t hcr_el2;
-
- /* Don't take exceptions if they target a lower EL.
- * This check should catch any exceptions that would not be taken but =
left
- * pending.
- */
- if (cur_el > target_el) {
- return false;
- }
-
- hcr_el2 =3D arm_hcr_el2_eff(env);
-
- switch (excp_idx) {
- case EXCP_FIQ:
- pstate_unmasked =3D !(env->daif & PSTATE_F);
- break;
-
- case EXCP_IRQ:
- pstate_unmasked =3D !(env->daif & PSTATE_I);
- break;
-
- case EXCP_VFIQ:
- if (secure || !(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) {
- /* VFIQs are only taken when hypervized and non-secure. */
- return false;
- }
- return !(env->daif & PSTATE_F);
- case EXCP_VIRQ:
- if (secure || !(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) {
- /* VIRQs are only taken when hypervized and non-secure. */
- return false;
- }
- return !(env->daif & PSTATE_I);
- default:
- g_assert_not_reached();
- }
-
- /* Use the target EL, current execution state and SCR/HCR settings to
- * determine whether the corresponding CPSR bit is used to mask the
- * interrupt.
- */
- if ((target_el > cur_el) && (target_el !=3D 1)) {
- /* Exceptions targeting a higher EL may not be maskable */
- if (arm_feature(env, ARM_FEATURE_AARCH64)) {
- /* 64-bit masking rules are simple: exceptions to EL3
- * can't be masked, and exceptions to EL2 can only be
- * masked from Secure state. The HCR and SCR settings
- * don't affect the masking logic, only the interrupt routing.
- */
- if (target_el =3D=3D 3 || !secure) {
- unmasked =3D 1;
- }
- } else {
- /* The old 32-bit-only environment has a more complicated
- * masking setup. HCR and SCR bits not only affect interrupt
- * routing but also change the behaviour of masking.
- */
- bool hcr, scr;
-
- switch (excp_idx) {
- case EXCP_FIQ:
- /* If FIQs are routed to EL3 or EL2 then there are cases w=
here
- * we override the CPSR.F in determining if the exception =
is
- * masked or not. If neither of these are set then we fall=
back
- * to the CPSR.F setting otherwise we further assess the s=
tate
- * below.
- */
- hcr =3D hcr_el2 & HCR_FMO;
- scr =3D (env->cp15.scr_el3 & SCR_FIQ);
-
- /* When EL3 is 32-bit, the SCR.FW bit controls whether the
- * CPSR.F bit masks FIQ interrupts when taken in non-secure
- * state. If SCR.FW is set then FIQs can be masked by CPSR=
.F
- * when non-secure but only when FIQs are only routed to E=
L3.
- */
- scr =3D scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr);
- break;
- case EXCP_IRQ:
- /* When EL3 execution state is 32-bit, if HCR.IMO is set t=
hen
- * we may override the CPSR.I masking when in non-secure s=
tate.
- * The SCR.IRQ setting has already been taken into conside=
ration
- * when setting the target EL, so it does not have a furth=
er
- * affect here.
- */
- hcr =3D hcr_el2 & HCR_IMO;
- scr =3D false;
- break;
- default:
- g_assert_not_reached();
- }
-
- if ((scr || hcr) && !secure) {
- unmasked =3D 1;
- }
- }
- }
-
- /* The PSTATE bits only mask the interrupt if we have not overriden the
- * ability above.
- */
- return unmasked || pstate_unmasked;
-}
-
#define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU
#define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX)
#define CPU_RESOLVING_TYPE TYPE_ARM_CPU
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 1ecf2adb6a9..b81ed44bd2b 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -410,6 +410,125 @@ static void arm_cpu_reset(CPUState *s)
arm_rebuild_hflags(env);
}
=20
+static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
+ unsigned int target_el)
+{
+ CPUARMState *env =3D cs->env_ptr;
+ unsigned int cur_el =3D arm_current_el(env);
+ bool secure =3D arm_is_secure(env);
+ bool pstate_unmasked;
+ int8_t unmasked =3D 0;
+ uint64_t hcr_el2;
+
+ /*
+ * Don't take exceptions if they target a lower EL.
+ * This check should catch any exceptions that would not be taken
+ * but left pending.
+ */
+ if (cur_el > target_el) {
+ return false;
+ }
+
+ hcr_el2 =3D arm_hcr_el2_eff(env);
+
+ switch (excp_idx) {
+ case EXCP_FIQ:
+ pstate_unmasked =3D !(env->daif & PSTATE_F);
+ break;
+
+ case EXCP_IRQ:
+ pstate_unmasked =3D !(env->daif & PSTATE_I);
+ break;
+
+ case EXCP_VFIQ:
+ if (secure || !(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) {
+ /* VFIQs are only taken when hypervized and non-secure. */
+ return false;
+ }
+ return !(env->daif & PSTATE_F);
+ case EXCP_VIRQ:
+ if (secure || !(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) {
+ /* VIRQs are only taken when hypervized and non-secure. */
+ return false;
+ }
+ return !(env->daif & PSTATE_I);
+ default:
+ g_assert_not_reached();
+ }
+
+ /*
+ * Use the target EL, current execution state and SCR/HCR settings to
+ * determine whether the corresponding CPSR bit is used to mask the
+ * interrupt.
+ */
+ if ((target_el > cur_el) && (target_el !=3D 1)) {
+ /* Exceptions targeting a higher EL may not be maskable */
+ if (arm_feature(env, ARM_FEATURE_AARCH64)) {
+ /*
+ * 64-bit masking rules are simple: exceptions to EL3
+ * can't be masked, and exceptions to EL2 can only be
+ * masked from Secure state. The HCR and SCR settings
+ * don't affect the masking logic, only the interrupt routing.
+ */
+ if (target_el =3D=3D 3 || !secure) {
+ unmasked =3D 1;
+ }
+ } else {
+ /*
+ * The old 32-bit-only environment has a more complicated
+ * masking setup. HCR and SCR bits not only affect interrupt
+ * routing but also change the behaviour of masking.
+ */
+ bool hcr, scr;
+
+ switch (excp_idx) {
+ case EXCP_FIQ:
+ /*
+ * If FIQs are routed to EL3 or EL2 then there are cases w=
here
+ * we override the CPSR.F in determining if the exception =
is
+ * masked or not. If neither of these are set then we fall=
back
+ * to the CPSR.F setting otherwise we further assess the s=
tate
+ * below.
+ */
+ hcr =3D hcr_el2 & HCR_FMO;
+ scr =3D (env->cp15.scr_el3 & SCR_FIQ);
+
+ /*
+ * When EL3 is 32-bit, the SCR.FW bit controls whether the
+ * CPSR.F bit masks FIQ interrupts when taken in non-secure
+ * state. If SCR.FW is set then FIQs can be masked by CPSR=
.F
+ * when non-secure but only when FIQs are only routed to E=
L3.
+ */
+ scr =3D scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr);
+ break;
+ case EXCP_IRQ:
+ /*
+ * When EL3 execution state is 32-bit, if HCR.IMO is set t=
hen
+ * we may override the CPSR.I masking when in non-secure s=
tate.
+ * The SCR.IRQ setting has already been taken into conside=
ration
+ * when setting the target EL, so it does not have a furth=
er
+ * affect here.
+ */
+ hcr =3D hcr_el2 & HCR_IMO;
+ scr =3D false;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ if ((scr || hcr) && !secure) {
+ unmasked =3D 1;
+ }
+ }
+ }
+
+ /*
+ * The PSTATE bits only mask the interrupt if we have not overriden the
+ * ability above.
+ */
+ return unmasked || pstate_unmasked;
+}
+
bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
CPUClass *cc =3D CPU_GET_CLASS(cs);
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 40/48] target/arm: Pass more cpu state to arm_excp_unmasked
Date: Fri, 7 Feb 2020 14:33:35 +0000
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From: Richard Henderson <richard.henderson@linaro.org>
Avoid redundant computation of cpu state by passing it in
from the caller, which has already computed it for itself.
Tested-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daud=C3=A9 <philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200206105448.4726-40-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.c | 22 ++++++++++++----------
1 file changed, 12 insertions(+), 10 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index b81ed44bd2b..fcee0a2dd45 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -411,14 +411,13 @@ static void arm_cpu_reset(CPUState *s)
}
=20
static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
- unsigned int target_el)
+ unsigned int target_el,
+ unsigned int cur_el, bool secure,
+ uint64_t hcr_el2)
{
CPUARMState *env =3D cs->env_ptr;
- unsigned int cur_el =3D arm_current_el(env);
- bool secure =3D arm_is_secure(env);
bool pstate_unmasked;
int8_t unmasked =3D 0;
- uint64_t hcr_el2;
=20
/*
* Don't take exceptions if they target a lower EL.
@@ -429,8 +428,6 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsi=
gned int excp_idx,
return false;
}
=20
- hcr_el2 =3D arm_hcr_el2_eff(env);
-
switch (excp_idx) {
case EXCP_FIQ:
pstate_unmasked =3D !(env->daif & PSTATE_F);
@@ -535,6 +532,7 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt=
_request)
CPUARMState *env =3D cs->env_ptr;
uint32_t cur_el =3D arm_current_el(env);
bool secure =3D arm_is_secure(env);
+ uint64_t hcr_el2 =3D arm_hcr_el2_eff(env);
uint32_t target_el;
uint32_t excp_idx;
bool ret =3D false;
@@ -542,7 +540,8 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt=
_request)
if (interrupt_request & CPU_INTERRUPT_FIQ) {
excp_idx =3D EXCP_FIQ;
target_el =3D arm_phys_excp_target_el(cs, excp_idx, cur_el, secure=
);
- if (arm_excp_unmasked(cs, excp_idx, target_el)) {
+ if (arm_excp_unmasked(cs, excp_idx, target_el,
+ cur_el, secure, hcr_el2)) {
cs->exception_index =3D excp_idx;
env->exception.target_el =3D target_el;
cc->do_interrupt(cs);
@@ -552,7 +551,8 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt=
_request)
if (interrupt_request & CPU_INTERRUPT_HARD) {
excp_idx =3D EXCP_IRQ;
target_el =3D arm_phys_excp_target_el(cs, excp_idx, cur_el, secure=
);
- if (arm_excp_unmasked(cs, excp_idx, target_el)) {
+ if (arm_excp_unmasked(cs, excp_idx, target_el,
+ cur_el, secure, hcr_el2)) {
cs->exception_index =3D excp_idx;
env->exception.target_el =3D target_el;
cc->do_interrupt(cs);
@@ -562,7 +562,8 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt=
_request)
if (interrupt_request & CPU_INTERRUPT_VIRQ) {
excp_idx =3D EXCP_VIRQ;
target_el =3D 1;
- if (arm_excp_unmasked(cs, excp_idx, target_el)) {
+ if (arm_excp_unmasked(cs, excp_idx, target_el,
+ cur_el, secure, hcr_el2)) {
cs->exception_index =3D excp_idx;
env->exception.target_el =3D target_el;
cc->do_interrupt(cs);
@@ -572,7 +573,8 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt=
_request)
if (interrupt_request & CPU_INTERRUPT_VFIQ) {
excp_idx =3D EXCP_VFIQ;
target_el =3D 1;
- if (arm_excp_unmasked(cs, excp_idx, target_el)) {
+ if (arm_excp_unmasked(cs, excp_idx, target_el,
+ cur_el, secure, hcr_el2)) {
cs->exception_index =3D excp_idx;
env->exception.target_el =3D target_el;
cc->do_interrupt(cs);
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 41/48] target/arm: Use bool for unmasked in arm_excp_unmasked
Date: Fri, 7 Feb 2020 14:33:36 +0000
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From: Richard Henderson <richard.henderson@linaro.org>
The value computed is fully boolean; using int8_t is odd.
Tested-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daud=C3=A9 <philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200206105448.4726-41-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index fcee0a2dd45..4ffc09909db 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -417,7 +417,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsi=
gned int excp_idx,
{
CPUARMState *env =3D cs->env_ptr;
bool pstate_unmasked;
- int8_t unmasked =3D 0;
+ bool unmasked =3D false;
=20
/*
* Don't take exceptions if they target a lower EL.
@@ -468,7 +468,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsi=
gned int excp_idx,
* don't affect the masking logic, only the interrupt routing.
*/
if (target_el =3D=3D 3 || !secure) {
- unmasked =3D 1;
+ unmasked =3D true;
}
} else {
/*
@@ -514,7 +514,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsi=
gned int excp_idx,
}
=20
if ((scr || hcr) && !secure) {
- unmasked =3D 1;
+ unmasked =3D true;
}
}
}
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 42/48] target/arm: Raise only one interrupt in
arm_cpu_exec_interrupt
Date: Fri, 7 Feb 2020 14:33:37 +0000
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From: Richard Henderson <richard.henderson@linaro.org>
The fall through organization of this function meant that we
would raise an interrupt, then might overwrite that with another.
Since interrupt prioritization is IMPLEMENTATION DEFINED, we
can recognize these in any order we choose.
Unify the code to raise the interrupt in a block at the end.
Tested-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200206105448.4726-42-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.c | 30 ++++++++++++------------------
1 file changed, 12 insertions(+), 18 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 4ffc09909db..b0762a76c4b 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -535,17 +535,15 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interru=
pt_request)
uint64_t hcr_el2 =3D arm_hcr_el2_eff(env);
uint32_t target_el;
uint32_t excp_idx;
- bool ret =3D false;
+
+ /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */
=20
if (interrupt_request & CPU_INTERRUPT_FIQ) {
excp_idx =3D EXCP_FIQ;
target_el =3D arm_phys_excp_target_el(cs, excp_idx, cur_el, secure=
);
if (arm_excp_unmasked(cs, excp_idx, target_el,
cur_el, secure, hcr_el2)) {
- cs->exception_index =3D excp_idx;
- env->exception.target_el =3D target_el;
- cc->do_interrupt(cs);
- ret =3D true;
+ goto found;
}
}
if (interrupt_request & CPU_INTERRUPT_HARD) {
@@ -553,10 +551,7 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrup=
t_request)
target_el =3D arm_phys_excp_target_el(cs, excp_idx, cur_el, secure=
);
if (arm_excp_unmasked(cs, excp_idx, target_el,
cur_el, secure, hcr_el2)) {
- cs->exception_index =3D excp_idx;
- env->exception.target_el =3D target_el;
- cc->do_interrupt(cs);
- ret =3D true;
+ goto found;
}
}
if (interrupt_request & CPU_INTERRUPT_VIRQ) {
@@ -564,10 +559,7 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrup=
t_request)
target_el =3D 1;
if (arm_excp_unmasked(cs, excp_idx, target_el,
cur_el, secure, hcr_el2)) {
- cs->exception_index =3D excp_idx;
- env->exception.target_el =3D target_el;
- cc->do_interrupt(cs);
- ret =3D true;
+ goto found;
}
}
if (interrupt_request & CPU_INTERRUPT_VFIQ) {
@@ -575,14 +567,16 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interru=
pt_request)
target_el =3D 1;
if (arm_excp_unmasked(cs, excp_idx, target_el,
cur_el, secure, hcr_el2)) {
- cs->exception_index =3D excp_idx;
- env->exception.target_el =3D target_el;
- cc->do_interrupt(cs);
- ret =3D true;
+ goto found;
}
}
+ return false;
=20
- return ret;
+ found:
+ cs->exception_index =3D excp_idx;
+ env->exception.target_el =3D target_el;
+ cc->do_interrupt(cs);
+ return true;
}
=20
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 43/48] bcm2835_dma: Fix the ylen loop in TD mode
Date: Fri, 7 Feb 2020 14:33:38 +0000
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From: Rene Stange <rsta2@o2online.de>
In TD (two dimensions) DMA mode ylen has to be increased by one after
reading it from the TXFR_LEN register, because a value of zero has to
result in one run through of the ylen loop. This has been tested on a
real Raspberry Pi 3 Model B+. In the previous implementation the ylen
loop was not passed at all for a value of zero.
Signed-off-by: Rene Stange <rsta2@o2online.de>
Reviewed-by: Philippe Mathieu-Daud=C3=A9 <philmd@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/dma/bcm2835_dma.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/dma/bcm2835_dma.c b/hw/dma/bcm2835_dma.c
index 1e458d7fba5..667d951a6f7 100644
--- a/hw/dma/bcm2835_dma.c
+++ b/hw/dma/bcm2835_dma.c
@@ -70,14 +70,14 @@ static void bcm2835_dma_update(BCM2835DMAState *s, unsi=
gned c)
ch->stride =3D ldl_le_phys(&s->dma_as, ch->conblk_ad + 16);
ch->nextconbk =3D ldl_le_phys(&s->dma_as, ch->conblk_ad + 20);
=20
+ ylen =3D 1;
if (ch->ti & BCM2708_DMA_TDMODE) {
/* 2D transfer mode */
- ylen =3D (ch->txfr_len >> 16) & 0x3fff;
+ ylen +=3D (ch->txfr_len >> 16) & 0x3fff;
xlen =3D ch->txfr_len & 0xffff;
dst_stride =3D ch->stride >> 16;
src_stride =3D ch->stride & 0xffff;
} else {
- ylen =3D 1;
xlen =3D ch->txfr_len;
dst_stride =3D 0;
src_stride =3D 0;
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 44/48] bcm2835_dma: Re-initialize xlen in TD mode
Date: Fri, 7 Feb 2020 14:33:39 +0000
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From: Rene Stange <rsta2@o2online.de>
TD (two dimensions) DMA mode did not work, because the xlen variable
has not been re-initialized before each additional ylen run through
in bcm2835_dma_update(). Fix it.
Signed-off-by: Rene Stange <rsta2@o2online.de>
Reviewed-by: Philippe Mathieu-Daud=C3=A9 <philmd@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/dma/bcm2835_dma.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/dma/bcm2835_dma.c b/hw/dma/bcm2835_dma.c
index 667d951a6f7..ccff5ed55b2 100644
--- a/hw/dma/bcm2835_dma.c
+++ b/hw/dma/bcm2835_dma.c
@@ -54,7 +54,7 @@
static void bcm2835_dma_update(BCM2835DMAState *s, unsigned c)
{
BCM2835DMAChan *ch =3D &s->chan[c];
- uint32_t data, xlen, ylen;
+ uint32_t data, xlen, xlen_td, ylen;
int16_t dst_stride, src_stride;
=20
if (!(s->enable & (1 << c))) {
@@ -82,6 +82,7 @@ static void bcm2835_dma_update(BCM2835DMAState *s, unsign=
ed c)
dst_stride =3D 0;
src_stride =3D 0;
}
+ xlen_td =3D xlen;
=20
while (ylen !=3D 0) {
/* Normal transfer mode */
@@ -117,6 +118,7 @@ static void bcm2835_dma_update(BCM2835DMAState *s, unsi=
gned c)
if (--ylen !=3D 0) {
ch->source_ad +=3D src_stride;
ch->dest_ad +=3D dst_stride;
+ xlen =3D xlen_td;
}
}
ch->cs |=3D BCM2708_DMA_END;
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 45/48] docs/arm-cpu-features: Make kvm-no-adjvtime comment
clearer
Date: Fri, 7 Feb 2020 14:33:40 +0000
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From: Philippe Mathieu-Daud=C3=A9 <philmd@redhat.com>
The bold text sounds like 'knock knock'. Only bolding the
second 'not' makes it easier to read.
Fixes: dea101a1ae
Signed-off-by: Philippe Mathieu-Daud=C3=A9 <philmd@redhat.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Message-id: 20200206225148.23923-1-philmd@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
docs/arm-cpu-features.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/docs/arm-cpu-features.rst b/docs/arm-cpu-features.rst
index dbf3b7cf42c..fc1623aeca5 100644
--- a/docs/arm-cpu-features.rst
+++ b/docs/arm-cpu-features.rst
@@ -185,7 +185,7 @@ the list of KVM VCPU features and their descriptions.
=20
kvm-no-adjvtime By default kvm-no-adjvtime is disabled. This
means that by default the virtual time
- adjustment is enabled (vtime is *not not*
+ adjustment is enabled (vtime is not *not*
adjusted).
=20
When virtual time adjustment is enabled each
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 46/48] armv7m_systick: delay timer_new to avoid memleaks
Date: Fri, 7 Feb 2020 14:33:41 +0000
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From: Pan Nengyuan <pannengyuan@huawei.com>
There is a memory leak when we call 'device_list_properties' with typename =
=3D armv7m_systick. It's easy to reproduce as follow:
virsh qemu-monitor-command vm1 --pretty '{"execute": "device-list-propert=
ies", "arguments": {"typename": "armv7m_systick"}}'
This patch delay timer_new to fix this memleaks.
Reported-by: Euler Robot <euler.robot@huawei.com>
Signed-off-by: Pan Nengyuan <pannengyuan@huawei.com>
Message-id: 20200205070659.22488-2-pannengyuan@huawei.com
Cc: qemu-arm@nongnu.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/timer/armv7m_systick.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/hw/timer/armv7m_systick.c b/hw/timer/armv7m_systick.c
index 85d122dbcbc..74c58bcf245 100644
--- a/hw/timer/armv7m_systick.c
+++ b/hw/timer/armv7m_systick.c
@@ -216,6 +216,11 @@ static void systick_instance_init(Object *obj)
memory_region_init_io(&s->iomem, obj, &systick_ops, s, "systick", 0xe0=
);
sysbus_init_mmio(sbd, &s->iomem);
sysbus_init_irq(sbd, &s->irq);
+}
+
+static void systick_realize(DeviceState *dev, Error **errp)
+{
+ SysTickState *s =3D SYSTICK(dev);
s->timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, systick_timer_tick, s);
}
=20
@@ -238,6 +243,7 @@ static void systick_class_init(ObjectClass *klass, void=
*data)
=20
dc->vmsd =3D &vmstate_systick;
dc->reset =3D systick_reset;
+ dc->realize =3D systick_realize;
}
=20
static const TypeInfo armv7m_systick_info =3D {
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 47/48] stm32f2xx_timer: delay timer_new to avoid memleaks
Date: Fri, 7 Feb 2020 14:33:42 +0000
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From: Pan Nengyuan <pannengyuan@huawei.com>
There is a memory leak when we call 'device_list_properties' with typename =
=3D stm32f2xx_timer. It's easy to reproduce as follow:
virsh qemu-monitor-command vm1 --pretty '{"execute": "device-list-prope=
rties", "arguments": {"typename": "stm32f2xx_timer"}}'
This patch delay timer_new to fix this memleaks.
Reported-by: Euler Robot <euler.robot@huawei.com>
Signed-off-by: Pan Nengyuan <pannengyuan@huawei.com>
Reviewed-by: Philippe Mathieu-Daud=C3=A9 <philmd@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200205070659.22488-3-pannengyuan@huawei.com
Cc: Alistair Francis <alistair@alistair23.me>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/timer/stm32f2xx_timer.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/hw/timer/stm32f2xx_timer.c b/hw/timer/stm32f2xx_timer.c
index fb370ce0f05..06ec8a02c25 100644
--- a/hw/timer/stm32f2xx_timer.c
+++ b/hw/timer/stm32f2xx_timer.c
@@ -314,7 +314,11 @@ static void stm32f2xx_timer_init(Object *obj)
memory_region_init_io(&s->iomem, obj, &stm32f2xx_timer_ops, s,
"stm32f2xx_timer", 0x400);
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
+}
=20
+static void stm32f2xx_timer_realize(DeviceState *dev, Error **errp)
+{
+ STM32F2XXTimerState *s =3D STM32F2XXTIMER(dev);
s->timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, stm32f2xx_timer_interrup=
t, s);
}
=20
@@ -325,6 +329,7 @@ static void stm32f2xx_timer_class_init(ObjectClass *kla=
ss, void *data)
dc->reset =3D stm32f2xx_timer_reset;
device_class_set_props(dc, stm32f2xx_timer_properties);
dc->vmsd =3D &vmstate_stm32f2xx_timer;
+ dc->realize =3D stm32f2xx_timer_realize;
}
=20
static const TypeInfo stm32f2xx_timer_info =3D {
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 48/48] stellaris: delay timer_new to avoid memleaks
Date: Fri, 7 Feb 2020 14:33:43 +0000
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From: Pan Nengyuan <pannengyuan@huawei.com>
There is a memory leak when we call 'device_list_properties' with typename =
=3D stellaris-gptm. It's easy to reproduce as follow:
virsh qemu-monitor-command vm1 --pretty '{"execute": "device-list-propert=
ies", "arguments": {"typename": "stellaris-gptm"}}'
This patch delay timer_new in realize to fix it.
Reported-by: Euler Robot <euler.robot@huawei.com>
Signed-off-by: Pan Nengyuan <pannengyuan@huawei.com>
Reviewed-by: Philippe Mathieu-Daud=C3=A9 <philmd@redhat.com>
Message-id: 20200205070659.22488-4-pannengyuan@huawei.com
Cc: qemu-arm@nongnu.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/stellaris.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index bb025e0bd0d..221a78674e3 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -347,11 +347,15 @@ static void stellaris_gptm_init(Object *obj)
sysbus_init_mmio(sbd, &s->iomem);
=20
s->opaque[0] =3D s->opaque[1] =3D s;
+}
+
+static void stellaris_gptm_realize(DeviceState *dev, Error **errp)
+{
+ gptm_state *s =3D STELLARIS_GPTM(dev);
s->timer[0] =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque=
[0]);
s->timer[1] =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque=
[1]);
}
=20
-
/* System controller. */
=20
typedef struct {
@@ -1536,6 +1540,7 @@ static void stellaris_gptm_class_init(ObjectClass *kl=
ass, void *data)
DeviceClass *dc =3D DEVICE_CLASS(klass);
=20
dc->vmsd =3D &vmstate_stellaris_gptm;
+ dc->realize =3D stellaris_gptm_realize;
}
=20
static const TypeInfo stellaris_gptm_info =3D {
--=20
2.20.1