Subject: [PULL 00/48] target-arm queue
Message-id: 20200207143343.30322-1-peter.maydell@linaro.org
Type: series

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

From https://github.com/patchew-project/qemu
 * [new tag]         patchew/20200207143343.30322-1-peter.maydell@linaro.org -> patchew/20200207143343.30322-1-peter.maydell@linaro.org
Switched to a new branch 'test'
21fd81e stellaris: delay timer_new to avoid memleaks
9f3a4b0 stm32f2xx_timer: delay timer_new to avoid memleaks
76518f5 armv7m_systick: delay timer_new to avoid memleaks
3c557d5 docs/arm-cpu-features: Make kvm-no-adjvtime comment clearer
f067b88 bcm2835_dma: Re-initialize xlen in TD mode
ccebd56 bcm2835_dma: Fix the ylen loop in TD mode
b1dbe8b target/arm: Raise only one interrupt in arm_cpu_exec_interrupt
2cfc229 target/arm: Use bool for unmasked in arm_excp_unmasked
73f5cce target/arm: Pass more cpu state to arm_excp_unmasked
b5acf5c target/arm: Move arm_excp_unmasked to cpu.c
0c40e8d target/arm: Enable ARMv8.1-VHE in -cpu max
ecb8fba target/arm: Update arm_cpu_do_interrupt_aarch64 for VHE
d805011 target/arm: Update get_a64_user_mem_index for VHE
9adfcd1 target/arm: check TGE and E2H flags for EL0 pauth traps
17f11fa target/arm: Update {fp,sve}_exception_el for VHE
437fc0d target/arm: Update arm_phys_excp_target_el for TGE
641cf18 target/arm: Flush tlbs for E2&0 translation regime
ef846bb target/arm: Flush tlb for ASID changes in EL2&0 translation regime
690016b target/arm: Add VHE timer register redirection and aliasing
a696370 target/arm: Add VHE system register redirection and aliasing
d62784b target/arm: Update define_one_arm_cp_reg_with_opaque for VHE
1416a19 target/arm: Update timer access for VHE
7ece414 target/arm: Add the hypervisor virtual counter
8372fa5 target/arm: Update ctr_el0_access for EL2
6503f80 target/arm: Update aa64_zva_access for EL2
b0433b7 target/arm: Update arm_sctlr for VHE
176d0ed target/arm: Update arm_mmu_idx for VHE
494df3c target/arm: Add regime_has_2_ranges
d910ce7 target/arm: Reorganize ARMMMUIdx
992e604 target/arm: Tidy ARMMMUIdx m-profile definitions
a872b71 target/arm: Rearrange ARMMMUIdxBit
6db7537 target/arm: Expand TBFLAG_ANY.MMUIDX to 4 bits
998fdee target/arm: Recover 4 bits from TBFLAGs
267eb0f target/arm: Rename ARMMMUIdx_S1E2 to ARMMMUIdx_E2
931babe target/arm: Rename ARMMMUIdx*_S1E3 to ARMMMUIdx*_SE3
67e93ee target/arm: Rename ARMMMUIdx_S1SE[01] to ARMMMUIdx_SE10_[01]
973a730 target/arm: Rename ARMMMUIdx_S1NSE* to ARMMMUIdx_Stage1_E*
86b8130 target/arm: Rename ARMMMUIdx_S2NS to ARMMMUIdx_Stage2
792f87a target/arm: Rename ARMMMUIdx*_S12NSE* to ARMMMUIdx*_E10_*
309e8fc target/arm: Simplify tlb_force_broadcast alternatives
b66912d target/arm: Split out alle1_tlbmask
eb9d654 target/arm: Split out vae1_tlbmask
284399c target/arm: Update CNTVCT_EL0 for VHE
8d578f1 target/arm: Add TTBR1_EL2
3e41e3f target/arm: Add CONTEXTIDR_EL2
9760424 target/arm: Enable HCR_E2H for VHE
77ff225 target/arm: Define isar_feature_aa64_vh
341d6e1 target/arm/monitor: query-cpu-model-expansion crashed qemu when using machine type none

=== OUTPUT BEGIN ===
1/48 Checking commit 341d6e1ee7cc (target/arm/monitor: query-cpu-model-expansion crashed qemu when using machine type none)
2/48 Checking commit 77ff225252b8 (target/arm: Define isar_feature_aa64_vh)
3/48 Checking commit 9760424e306e (target/arm: Enable HCR_E2H for VHE)
4/48 Checking commit 3e41e3fa78bd (target/arm: Add CONTEXTIDR_EL2)
5/48 Checking commit 8d578f18f2c6 (target/arm: Add TTBR1_EL2)
6/48 Checking commit 284399c03783 (target/arm: Update CNTVCT_EL0 for VHE)
7/48 Checking commit eb9d654ae1af (target/arm: Split out vae1_tlbmask)
8/48 Checking commit b66912d7b29b (target/arm: Split out alle1_tlbmask)
9/48 Checking commit 309e8fcb205a (target/arm: Simplify tlb_force_broadcast alternatives)
10/48 Checking commit 792f87a3190e (target/arm: Rename ARMMMUIdx*_S12NSE* to ARMMMUIdx*_E10_*)
11/48 Checking commit 86b81302343c (target/arm: Rename ARMMMUIdx_S2NS to ARMMMUIdx_Stage2)
12/48 Checking commit 973a7309bde0 (target/arm: Rename ARMMMUIdx_S1NSE* to ARMMMUIdx_Stage1_E*)
13/48 Checking commit 67e93ee01e8c (target/arm: Rename ARMMMUIdx_S1SE[01] to ARMMMUIdx_SE10_[01])
14/48 Checking commit 931babe38503 (target/arm: Rename ARMMMUIdx*_S1E3 to ARMMMUIdx*_SE3)
15/48 Checking commit 267eb0fde645 (target/arm: Rename ARMMMUIdx_S1E2 to ARMMMUIdx_E2)
16/48 Checking commit 998fdee69f2d (target/arm: Recover 4 bits from TBFLAGs)
17/48 Checking commit 6db75371eea5 (target/arm: Expand TBFLAG_ANY.MMUIDX to 4 bits)
18/48 Checking commit a872b71cb564 (target/arm: Rearrange ARMMMUIdxBit)
19/48 Checking commit 992e604d3e33 (target/arm: Tidy ARMMMUIdx m-profile definitions)
20/48 Checking commit d910ce7eac37 (target/arm: Reorganize ARMMMUIdx)
21/48 Checking commit 494df3c4224e (target/arm: Add regime_has_2_ranges)
22/48 Checking commit 176d0ed0ec16 (target/arm: Update arm_mmu_idx for VHE)
23/48 Checking commit b0433b7f4453 (target/arm: Update arm_sctlr for VHE)
24/48 Checking commit 6503f8089d30 (target/arm: Update aa64_zva_access for EL2)
25/48 Checking commit 8372fa5625da (target/arm: Update ctr_el0_access for EL2)
26/48 Checking commit 7ece4140f114 (target/arm: Add the hypervisor virtual counter)
27/48 Checking commit 1416a1917af6 (target/arm: Update timer access for VHE)
28/48 Checking commit d62784b94e94 (target/arm: Update define_one_arm_cp_reg_with_opaque for VHE)
29/48 Checking commit a696370b5727 (target/arm: Add VHE system register redirection and aliasing)
30/48 Checking commit 690016b12d0f (target/arm: Add VHE timer register redirection and aliasing)
31/48 Checking commit ef846bbb26a3 (target/arm: Flush tlb for ASID changes in EL2&0 translation regime)
32/48 Checking commit 641cf1858a81 (target/arm: Flush tlbs for E2&0 translation regime)
33/48 Checking commit 437fc0d2dfec (target/arm: Update arm_phys_excp_target_el for TGE)
34/48 Checking commit 17f11fa2cefa (target/arm: Update {fp,sve}_exception_el for VHE)
35/48 Checking commit 9adfcd1f7553 (target/arm: check TGE and E2H flags for EL0 pauth traps)
36/48 Checking commit d8050118c0a4 (target/arm: Update get_a64_user_mem_index for VHE)
37/48 Checking commit ecb8fba6b7ee (target/arm: Update arm_cpu_do_interrupt_aarch64 for VHE)
38/48 Checking commit 0c40e8d6c4a2 (target/arm: Enable ARMv8.1-VHE in -cpu max)
39/48 Checking commit b5acf5c0a412 (target/arm: Move arm_excp_unmasked to cpu.c)
40/48 Checking commit 73f5cce2011b (target/arm: Pass more cpu state to arm_excp_unmasked)
41/48 Checking commit 2cfc22964abb (target/arm: Use bool for unmasked in arm_excp_unmasked)
42/48 Checking commit b1dbe8bcf576 (target/arm: Raise only one interrupt in arm_cpu_exec_interrupt)
43/48 Checking commit ccebd560320b (bcm2835_dma: Fix the ylen loop in TD mode)
44/48 Checking commit f067b88c355e (bcm2835_dma: Re-initialize xlen in TD mode)
45/48 Checking commit 3c557d506a6f (docs/arm-cpu-features: Make kvm-no-adjvtime comment clearer)
46/48 Checking commit 76518f5cbcd0 (armv7m_systick: delay timer_new to avoid memleaks)
47/48 Checking commit 9f3a4b06d77f (stm32f2xx_timer: delay timer_new to avoid memleaks)
48/48 Checking commit 21fd81ef9d78 (stellaris: delay timer_new to avoid memleaks)
=== OUTPUT END ===

Test command exited with code: 0