From nobody Tue Feb 10 04:56:03 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580986673311259.6779867354529; Thu, 6 Feb 2020 02:57:53 -0800 (PST) Received: from localhost ([::1]:35724 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1izer2-0000BL-71 for importer@patchew.org; Thu, 06 Feb 2020 05:57:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:49743) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1izeoH-0002x9-7Q for qemu-devel@nongnu.org; Thu, 06 Feb 2020 05:55:02 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1izeoE-0006aT-Ju for qemu-devel@nongnu.org; Thu, 06 Feb 2020 05:55:01 -0500 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:46400) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1izeoE-0006NX-Bj for qemu-devel@nongnu.org; Thu, 06 Feb 2020 05:54:58 -0500 Received: by mail-wr1-x444.google.com with SMTP id z7so6532960wrl.13 for ; Thu, 06 Feb 2020 02:54:58 -0800 (PST) Received: from cloudburst.c.hoisthospitality.com ([135.196.99.211]) by smtp.gmail.com with ESMTPSA id m21sm3364995wmi.27.2020.02.06.02.54.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Feb 2020 02:54:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=diptFi6gnEr4A7ejwzLshh6k//+fjXBlKBTtRRGDoNE=; b=EyCGoJv4cG7JiRdQhTsj1Sx2SYd4iOK/TaV5xpqvpIMPS16NgJmS+e3ZGvVTIoFa3r eekNVZme0Qbi6emYTB7a2WtCnm5gl7OWkNZ6ZKFcQNGwic6sykH5F1l4R4Ba2eDv3y3S hb8q96l+EQHL7pCIcoWmeuLdCdT50ZAqTSkCFeyamGm848QK2zbeMzSAwQxzjgdN0IZn 6M3f8eVtkd8/umt4x2TrG8y5QcoyrOBhSsKdspYYbqzXWs05o80U6gWDxso1f5tKoY5Q 9n39xuHgJ58exiRhV5H2agrQjRDoo1Spr0OJPA8KFIHCVOt6NHwM2hFc9l2CU3cURx8j o+nw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=diptFi6gnEr4A7ejwzLshh6k//+fjXBlKBTtRRGDoNE=; b=OJ21OoxoCjBuDdQ0XVwwunCVFqDhSHZfuplyjua+7PSP8lp+mjuTj2cv2Zz2+fJHPv SrU1XjsVeShZwLEuX7fQmbqZ3epuwuFh0qnBSOD7NHnuGZ3gXqfb/OI/6M57urJFpWeN XNxtRYL/ME7ugG5TjgDEqQ4/hCC/ioEoGaYvghHp4V9uuiexIzy4IYqBC8QGw8E/52iV EhOtns4wO+YmNTDlmJi99gM8Vxt/C5GFTe53kDsI+zEIxeOLYjovITchWezwwBt1145G N3S9I1Qwbjn2lzMHX0WjPE8YCII/xsIFiqGKwZdtF6obJT90tJKGoWyjlNqo9O16u4hO fkWg== X-Gm-Message-State: APjAAAV6tgmqQcBPUcPjW8it4YWAq1Qo0xZz5KXJHSy+qRRFxjPna7js 4cYbXBDBpbjSAJDpzBaP/YJ/VkQOp9UxcA== X-Google-Smtp-Source: APXvYqwB6sAzQJqF0bOvOZduS9caW4jKcX+Wx05tqrbzDSYNWP78VznSFphMFlV9Od/bvPzhpumiCQ== X-Received: by 2002:adf:ee41:: with SMTP id w1mr3222584wro.368.1580986495493; Thu, 06 Feb 2020 02:54:55 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v7 07/41] target/arm: Split out alle1_tlbmask Date: Thu, 6 Feb 2020 10:54:14 +0000 Message-Id: <20200206105448.4726-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200206105448.4726-1-richard.henderson@linaro.org> References: <20200206105448.4726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) No functional change, but unify code sequences. Tested-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- v5: Do not confuse things by prefixing "vm". --- target/arm/helper.c | 86 +++++++++++++-------------------------------- 1 file changed, 24 insertions(+), 62 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 8b3bb51dee..49da685b29 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3972,34 +3972,31 @@ static void tlbi_aa64_vmalle1_write(CPUARMState *en= v, const ARMCPRegInfo *ri, tlb_flush_by_mmuidx(cs, mask); } =20 -static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) +static int alle1_tlbmask(CPUARMState *env) { - /* Note that the 'ALL' scope must invalidate both stage 1 and + /* + * Note that the 'ALL' scope must invalidate both stage 1 and * stage 2 translations, whereas most other scopes only invalidate * stage 1 translations. */ - ARMCPU *cpu =3D env_archcpu(env); - CPUState *cs =3D CPU(cpu); - if (arm_is_secure_below_el3(env)) { - tlb_flush_by_mmuidx(cs, - ARMMMUIdxBit_S1SE1 | - ARMMMUIdxBit_S1SE0); + return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0; + } else if (arm_feature(env, ARM_FEATURE_EL2)) { + return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0 | ARMMMUIdxBit_= S2NS; } else { - if (arm_feature(env, ARM_FEATURE_EL2)) { - tlb_flush_by_mmuidx(cs, - ARMMMUIdxBit_S12NSE1 | - ARMMMUIdxBit_S12NSE0 | - ARMMMUIdxBit_S2NS); - } else { - tlb_flush_by_mmuidx(cs, - ARMMMUIdxBit_S12NSE1 | - ARMMMUIdxBit_S12NSE0); - } + return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0; } } =20 +static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + CPUState *cs =3D env_cpu(env); + int mask =3D alle1_tlbmask(env); + + tlb_flush_by_mmuidx(cs, mask); +} + static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -4021,28 +4018,10 @@ static void tlbi_aa64_alle3_write(CPUARMState *env,= const ARMCPRegInfo *ri, static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *= ri, uint64_t value) { - /* Note that the 'ALL' scope must invalidate both stage 1 and - * stage 2 translations, whereas most other scopes only invalidate - * stage 1 translations. - */ CPUState *cs =3D env_cpu(env); - bool sec =3D arm_is_secure_below_el3(env); - bool has_el2 =3D arm_feature(env, ARM_FEATURE_EL2); + int mask =3D alle1_tlbmask(env); =20 - if (sec) { - tlb_flush_by_mmuidx_all_cpus_synced(cs, - ARMMMUIdxBit_S1SE1 | - ARMMMUIdxBit_S1SE0); - } else if (has_el2) { - tlb_flush_by_mmuidx_all_cpus_synced(cs, - ARMMMUIdxBit_S12NSE1 | - ARMMMUIdxBit_S12NSE0 | - ARMMMUIdxBit_S2NS); - } else { - tlb_flush_by_mmuidx_all_cpus_synced(cs, - ARMMMUIdxBit_S12NSE1 | - ARMMMUIdxBit_S12NSE0); - } + tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); } =20 static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *= ri, @@ -4092,20 +4071,11 @@ static void tlbi_aa64_vae3_write(CPUARMState *env, = const ARMCPRegInfo *ri, static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *r= i, uint64_t value) { - ARMCPU *cpu =3D env_archcpu(env); - CPUState *cs =3D CPU(cpu); - bool sec =3D arm_is_secure_below_el3(env); + CPUState *cs =3D env_cpu(env); + int mask =3D vae1_tlbmask(env); uint64_t pageaddr =3D sextract64(value << 12, 0, 56); =20 - if (sec) { - tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, - ARMMMUIdxBit_S1SE1 | - ARMMMUIdxBit_S1SE0); - } else { - tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, - ARMMMUIdxBit_S12NSE1 | - ARMMMUIdxBit_S12NSE0); - } + tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, mask); } =20 static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -4116,8 +4086,8 @@ static void tlbi_aa64_vae1_write(CPUARMState *env, co= nst ARMCPRegInfo *ri, * since we don't support flush-for-specific-ASID-only or * flush-last-level-only. */ - ARMCPU *cpu =3D env_archcpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); + int mask =3D vae1_tlbmask(env); uint64_t pageaddr =3D sextract64(value << 12, 0, 56); =20 if (tlb_force_broadcast(env)) { @@ -4125,15 +4095,7 @@ static void tlbi_aa64_vae1_write(CPUARMState *env, c= onst ARMCPRegInfo *ri, return; } =20 - if (arm_is_secure_below_el3(env)) { - tlb_flush_page_by_mmuidx(cs, pageaddr, - ARMMMUIdxBit_S1SE1 | - ARMMMUIdxBit_S1SE0); - } else { - tlb_flush_page_by_mmuidx(cs, pageaddr, - ARMMMUIdxBit_S12NSE1 | - ARMMMUIdxBit_S12NSE0); - } + tlb_flush_page_by_mmuidx(cs, pageaddr, mask); } =20 static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *r= i, --=20 2.20.1