From nobody Tue Feb 10 07:23:31 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580987616446269.95107861427573; Thu, 6 Feb 2020 03:13:36 -0800 (PST) Received: from localhost ([::1]:36196 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1izf6F-00042e-9e for importer@patchew.org; Thu, 06 Feb 2020 06:13:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50121) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1izeoX-0003OM-Jl for qemu-devel@nongnu.org; Thu, 06 Feb 2020 05:55:19 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1izeoW-0007yx-7b for qemu-devel@nongnu.org; Thu, 06 Feb 2020 05:55:17 -0500 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:45292) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1izeoV-0007tf-Tx for qemu-devel@nongnu.org; Thu, 06 Feb 2020 05:55:16 -0500 Received: by mail-wr1-x444.google.com with SMTP id a6so6528825wrx.12 for ; Thu, 06 Feb 2020 02:55:15 -0800 (PST) Received: from cloudburst.c.hoisthospitality.com ([135.196.99.211]) by smtp.gmail.com with ESMTPSA id m21sm3364995wmi.27.2020.02.06.02.55.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Feb 2020 02:55:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=s6izLxVkzfpWzTSxiliPLXkwhbsXlNldqMSOd9icaXQ=; b=Vx6EHATH3Mea9UR/SecyMDGVqkHyHWQ9nJ22W+Zj1/ShJ9c4iVF1r6j6rTBeAxdlDl H4OoW//f0qf9Rff96I5s11u2gY6QhRXKVx9rVCcbFK2FsX2seKgb8mSfRXQT27iCDzf2 aIiW/NIfN+ZhCbRyxC+wKITk/HwQC4eaMxo+7iIgTTnS1nbsBV11NOr6Y1PEcgavlq2P yZDSfAy6uo3bKDOoNgZqw+Wkb3rm3SmgGBeaWuve3EzYmopO7adQpAUXv/rV462dErvJ mKBdocBo87IdAlZfMsK73FO5ZV3BvWL/Lm/xmuoX0c6bgdUMn51SOaN1jd2O3xWzVjxB VxAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=s6izLxVkzfpWzTSxiliPLXkwhbsXlNldqMSOd9icaXQ=; b=oFDJrnPlrllV3uS6Iixrtw7kYzArKGXqxVsOXWwKUhjJw5+D52tXEvEz0Gmdg4ApDz NwqyY7gYZCSxckH0tboWrvN8OqHfekWMAJrt50hZeC9rDyET0dgpKgfqSRztrF0TFFCH K/skBpzdhMI2UoyidIN8RNEDLeq/k4As7HsDs6K8LIjXkQ4nqDSC47wTefC883Ui4OZz 7NRaypt6/mbfgr0o3WkSRQiiNIKwMn/ZBLbhHBxOF5//xVZUqEYY8ngo9dcBqlVjSACY kpcMhSG4mI9WvtkvciLedBVRyHe9ZBdu7BZtvkBOVgAQYlBnnJ7mlEQxfGVvZhMzyd3q cSYw== X-Gm-Message-State: APjAAAUGyigPwF+T5UfjdgYPWOPp+naQdWc6MNRNGh33Da92TfCM6QOd JiHwCGxvF2Nfk6J3Pe5plY1ddwWsabZU3w== X-Google-Smtp-Source: APXvYqyHYSXkLluLDSsvBd/kzKGBnS4UgfEkTE+Bp4VUo+gnXs9PyEN6kbgUGUadNhnpEy9bKkr33w== X-Received: by 2002:adf:f8c4:: with SMTP id f4mr3045030wrq.243.1580986514657; Thu, 06 Feb 2020 02:55:14 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v7 30/41] target/arm: Flush tlb for ASID changes in EL2&0 translation regime Date: Thu, 6 Feb 2020 10:54:37 +0000 Message-Id: <20200206105448.4726-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200206105448.4726-1-richard.henderson@linaro.org> References: <20200206105448.4726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Since we only support a single ASID, flush the tlb when it changes. Note that TCR_EL2, like TCR_EL1, has the A1 bit that chooses between the two TTBR* registers for the location of the ASID. Tested-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index cfa6ce59dc..f9be6b052f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3763,7 +3763,7 @@ static void vmsa_ttbcr_reset(CPUARMState *env, const = ARMCPRegInfo *ri) tcr->base_mask =3D 0xffffc000u; } =20 -static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, +static void vmsa_tcr_el12_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { ARMCPU *cpu =3D env_archcpu(env); @@ -3789,7 +3789,17 @@ static void vmsa_ttbr_write(CPUARMState *env, const = ARMCPRegInfo *ri, static void vmsa_tcr_ttbr_el2_write(CPUARMState *env, const ARMCPRegInfo *= ri, uint64_t value) { - /* TODO: There are ASID fields in here with HCR_EL2.E2H */ + /* + * If we are running with E2&0 regime, then an ASID is active. + * Flush if that might be changing. Note we're not checking + * TCR_EL2.A1 to know if this is really the TTBRx_EL2 that + * holds the active ASID, only checking the field that might. + */ + if (extract64(raw_read(env, ri) ^ value, 48, 16) && + (arm_hcr_el2_eff(env) & HCR_E2H)) { + tlb_flush_by_mmuidx(env_cpu(env), + ARMMMUIdxBit_E20_2 | ARMMMUIdxBit_E20_0); + } raw_write(env, ri, value); } =20 @@ -3849,7 +3859,7 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] =3D { offsetof(CPUARMState, cp15.ttbr1_ns) } }, { .name =3D "TCR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .crn =3D 2, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 2, - .access =3D PL1_RW, .writefn =3D vmsa_tcr_el1_write, + .access =3D PL1_RW, .writefn =3D vmsa_tcr_el12_write, .resetfn =3D vmsa_ttbcr_reset, .raw_writefn =3D raw_write, .fieldoffset =3D offsetof(CPUARMState, cp15.tcr_el[1]) }, { .name =3D "TTBCR", .cp =3D 15, .crn =3D 2, .crm =3D 0, .opc1 =3D 0, = .opc2 =3D 2, @@ -5175,10 +5185,8 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { .resetvalue =3D 0 }, { .name =3D "TCR_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 2, - .access =3D PL2_RW, - /* no .writefn needed as this can't cause an ASID change; - * no .raw_writefn or .resetfn needed as we never use mask/base_mask - */ + .access =3D PL2_RW, .writefn =3D vmsa_tcr_el12_write, + /* no .raw_writefn or .resetfn needed as we never use mask/base_mask= */ .fieldoffset =3D offsetof(CPUARMState, cp15.tcr_el[2]) }, { .name =3D "VTCR", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 4, .crn =3D 2, .crm =3D 1, .opc2 =3D 2, --=20 2.20.1