From nobody Tue Feb 10 07:23:39 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580987262751361.00287835910046; Thu, 6 Feb 2020 03:07:42 -0800 (PST) Received: from localhost ([::1]:36018 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1izf0X-0000zN-KC for importer@patchew.org; Thu, 06 Feb 2020 06:07:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:49879) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1izeoO-00034O-7C for qemu-devel@nongnu.org; Thu, 06 Feb 2020 05:55:09 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1izeoM-0007B3-LQ for qemu-devel@nongnu.org; Thu, 06 Feb 2020 05:55:08 -0500 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:42610) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1izeoM-00073k-C0 for qemu-devel@nongnu.org; Thu, 06 Feb 2020 05:55:06 -0500 Received: by mail-wr1-x442.google.com with SMTP id k11so6550050wrd.9 for ; Thu, 06 Feb 2020 02:55:05 -0800 (PST) Received: from cloudburst.c.hoisthospitality.com ([135.196.99.211]) by smtp.gmail.com with ESMTPSA id m21sm3364995wmi.27.2020.02.06.02.55.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Feb 2020 02:55:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6GrGdVij1LEfH8uaHPt30B16FVSaZDBvRCDaruXRkoU=; b=ir8HeMz5HCdyrAlZGKVgmJN7uHvxQsqIz0ME+V66o15woP0EDhQm3qZW5I3lT+F3TO U3zwZr5zqCtmKlL3ueaznMdHauNTj5GXRHVM1jV1RNulmW+dp2IlvhBD53wbz8CwrKE5 pFJtYou+hIDnoh0Ik6IQ5F5wve9sgWmSGNqmhlVNSQ0iuQJd78UZQ0pfI2L05sO8bRqa +coUAlfwJ0RJmCIuSEtYuTyYGP5Mho87mjQCIAIto3r1nZ8TcG+oqpu9NSxNv6uxAUhS sDAktYWRDgTfNx/lrdDUEc90onSix88jj55YL4HDmG7bOM/UlcEXGNdTZ+QWbBKCC790 ASqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6GrGdVij1LEfH8uaHPt30B16FVSaZDBvRCDaruXRkoU=; b=oGD3+ulA0GMOPPW64cgN9uPuVz4M2qW+L0n57JBxA8AWjmZX+mvIYYDpvETRd7kPkp D0jFgYJW5dRzafwfxdMr536WS6gJxYE/qD/0uosXaf+RfwRfOczA45LtiwgmHv74XHTN YHD58EwvrsdMn+Yd93BJer2hyK+7GxOjnm9J5kZxBd8FKQYAReDnC98dfAYW5kr/DaPC rkUn/G1Qu7XUaeZWG96i5nOVPO9F6sY9mwwTQhc0DlswSIui2qptbVh/XJQzzvNRfSpr 48mJ2Ck5cDRiqSjxjYRWrWKVAYlo3x4RCsKlqicVx3PB+O3blpOCQC8vOCWP+nHlZH3D NolQ== X-Gm-Message-State: APjAAAVzLqoNx1Xt3/uMe58h23wBlSXKnT1Vluh28dulY/EEphDpQnla b0lFzEGyff/0I8PFQm89ARNdRNvE/lWOzA== X-Google-Smtp-Source: APXvYqzSDBYzqxPx5lZMbVEzyCC7wkC0zVfq2NMTCbE/UL8d2nucwQwHIAIZvoGaftobiyhag1/ZzQ== X-Received: by 2002:adf:ca07:: with SMTP id o7mr3117668wrh.49.1580986504442; Thu, 06 Feb 2020 02:55:04 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v7 17/41] target/arm: Rearrange ARMMMUIdxBit Date: Thu, 6 Feb 2020 10:54:24 +0000 Message-Id: <20200206105448.4726-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200206105448.4726-1-richard.henderson@linaro.org> References: <20200206105448.4726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Define via macro expansion, so that renumbering of the base ARMMMUIdx symbols is automatically reflected in the bit definitions. Tested-by: Alex Benn=C3=A9e Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/arm/cpu.h | 39 +++++++++++++++++++++++---------------- 1 file changed, 23 insertions(+), 16 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index aa9728cff6..aa121cd9d0 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2927,27 +2927,34 @@ typedef enum ARMMMUIdx { ARMMMUIdx_Stage1_E1 =3D 1 | ARM_MMU_IDX_NOTLB, } ARMMMUIdx; =20 -/* Bit macros for the core-mmu-index values for each index, +/* + * Bit macros for the core-mmu-index values for each index, * for use when calling tlb_flush_by_mmuidx() and friends. */ +#define TO_CORE_BIT(NAME) \ + ARMMMUIdxBit_##NAME =3D 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_M= ASK) + typedef enum ARMMMUIdxBit { - ARMMMUIdxBit_E10_0 =3D 1 << 0, - ARMMMUIdxBit_E10_1 =3D 1 << 1, - ARMMMUIdxBit_E2 =3D 1 << 2, - ARMMMUIdxBit_SE3 =3D 1 << 3, - ARMMMUIdxBit_SE10_0 =3D 1 << 4, - ARMMMUIdxBit_SE10_1 =3D 1 << 5, - ARMMMUIdxBit_Stage2 =3D 1 << 6, - ARMMMUIdxBit_MUser =3D 1 << 0, - ARMMMUIdxBit_MPriv =3D 1 << 1, - ARMMMUIdxBit_MUserNegPri =3D 1 << 2, - ARMMMUIdxBit_MPrivNegPri =3D 1 << 3, - ARMMMUIdxBit_MSUser =3D 1 << 4, - ARMMMUIdxBit_MSPriv =3D 1 << 5, - ARMMMUIdxBit_MSUserNegPri =3D 1 << 6, - ARMMMUIdxBit_MSPrivNegPri =3D 1 << 7, + TO_CORE_BIT(E10_0), + TO_CORE_BIT(E10_1), + TO_CORE_BIT(E2), + TO_CORE_BIT(SE10_0), + TO_CORE_BIT(SE10_1), + TO_CORE_BIT(SE3), + TO_CORE_BIT(Stage2), + + TO_CORE_BIT(MUser), + TO_CORE_BIT(MPriv), + TO_CORE_BIT(MUserNegPri), + TO_CORE_BIT(MPrivNegPri), + TO_CORE_BIT(MSUser), + TO_CORE_BIT(MSPriv), + TO_CORE_BIT(MSUserNegPri), + TO_CORE_BIT(MSPrivNegPri), } ARMMMUIdxBit; =20 +#undef TO_CORE_BIT + #define MMU_USER_IDX 0 =20 static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx) --=20 2.20.1