From nobody Thu Nov 13 15:06:52 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580741327931695.5006586149789; Mon, 3 Feb 2020 06:48:47 -0800 (PST) Received: from localhost ([::1]:42368 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iyd1o-0008W5-G3 for importer@patchew.org; Mon, 03 Feb 2020 09:48:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44533) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iyd0W-0006bf-DF for qemu-devel@nongnu.org; Mon, 03 Feb 2020 09:47:25 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iyd0V-00036o-5F for qemu-devel@nongnu.org; Mon, 03 Feb 2020 09:47:24 -0500 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:40912) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iyd0U-000362-VY for qemu-devel@nongnu.org; Mon, 03 Feb 2020 09:47:23 -0500 Received: by mail-wm1-x343.google.com with SMTP id t14so17462462wmi.5 for ; Mon, 03 Feb 2020 06:47:22 -0800 (PST) Received: from cloudburst.c.hoisthospitality.com ([135.196.99.211]) by smtp.gmail.com with ESMTPSA id h2sm26429739wrt.45.2020.02.03.06.47.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Feb 2020 06:47:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2RHX+9VAaI14LH2Ijti0R37fLYBPx3ELl/51B+kqxLE=; b=cIUPm46rPwr1I2vTyH53gapoGurLqsjkZf01uMi+qP3jbXo851VSVwMIuA1zXtKENk OiyA3e6ZIYbSA1Bzi+BD4i2viejbv4XVgMDnhThQtbVQiScPQ6uid0LUt5dnMYPZXzGA tiBKbnmn+X176XgmSMyNmMaKwS0tEDEHbNDbwswKaxRtfFYAmH3pnX720lrlVdzJsrz9 L0ltE/KnTV/FoMte2heRWvgsgbqQTzQMTal3Miz0oRMkAtQErH6MN9zbZy5DHT56Byo4 3jQMFvUE8vt9alwOfCx0Ako1mG1GTBkdEfOn23e12OBgINtxqpuCb1y3Uyn8H7tpM8Ym RQSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2RHX+9VAaI14LH2Ijti0R37fLYBPx3ELl/51B+kqxLE=; b=e9Jah7JOCghFkxFMGzxSl0BuDrpd8vqcHTnO84VkA8lj2Z/ZR45oKydzHUZFwCcnq4 6gpIOIGnoWSRkiZbc+t329qH8OcVCBk+cRLVXNYR/ltb+RofP7nISKAAd9bgsqHxzbrd tX22beE1DKsLJzOpVAwOyXwWwrMPPinsF9IYDLjpfTlLt4RJw/3fVftq1YSj1nzLc5Bx OGLhnhjXFYNAr9rRrPLiLb50D3ZDE4qumw+P1fS3rHb0wZPDAOTYx71XDirvXxjCqcf/ xmzgkMW8Vd0wb0K4kOcJTWDeYYZmtjBO5K/5f6lwt/hZIpnInqr4UTC/X7+EsYpOOQN4 vx3Q== X-Gm-Message-State: APjAAAUjwDRPjLEv22YnlQzVtO64VF9tfVuSdM/tqzFB9qnRlEDuM7FN HGwdr/ynFCTuqdusxD64AQbRJC8NcS99Pg== X-Google-Smtp-Source: APXvYqyOvMQ+ffoeAHDFEZZ3/wYB6JcYlNYIzO3tik8dShR+rv2kh0TAuFfgfwk3ei1VGHdLPOUzyA== X-Received: by 2002:a1c:cc11:: with SMTP id h17mr28766142wmb.19.1580741241613; Mon, 03 Feb 2020 06:47:21 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 04/20] target/arm: Move LOR regdefs to file scope Date: Mon, 3 Feb 2020 14:47:00 +0000 Message-Id: <20200203144716.32204-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200203144716.32204-1-richard.henderson@linaro.org> References: <20200203144716.32204-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) For static const regdefs, file scope is preferred. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- target/arm/helper.c | 57 +++++++++++++++++++++++---------------------- 1 file changed, 29 insertions(+), 28 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 739d2d4cc5..795ef727d0 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6343,6 +6343,35 @@ static CPAccessResult access_lor_other(CPUARMState *= env, return access_lor_ns(env); } =20 +/* + * A trivial implementation of ARMv8.1-LOR leaves all of these + * registers fixed at 0, which indicates that there are zero + * supported Limited Ordering regions. + */ +static const ARMCPRegInfo lor_reginfo[] =3D { + { .name =3D "LORSA_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D 0, + .access =3D PL1_RW, .accessfn =3D access_lor_other, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "LOREA_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D 1, + .access =3D PL1_RW, .accessfn =3D access_lor_other, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "LORN_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D 2, + .access =3D PL1_RW, .accessfn =3D access_lor_other, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "LORC_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D 3, + .access =3D PL1_RW, .accessfn =3D access_lor_other, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "LORID_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D 7, + .access =3D PL1_R, .accessfn =3D access_lorid, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + REGINFO_SENTINEL +}; + #ifdef TARGET_AARCH64 static CPAccessResult access_pauth(CPUARMState *env, const ARMCPRegInfo *r= i, bool isread) @@ -7577,34 +7606,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) } =20 if (cpu_isar_feature(aa64_lor, cpu)) { - /* - * A trivial implementation of ARMv8.1-LOR leaves all of these - * registers fixed at 0, which indicates that there are zero - * supported Limited Ordering regions. - */ - static const ARMCPRegInfo lor_reginfo[] =3D { - { .name =3D "LORSA_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D= 0, - .access =3D PL1_RW, .accessfn =3D access_lor_other, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "LOREA_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D= 1, - .access =3D PL1_RW, .accessfn =3D access_lor_other, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "LORN_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D= 2, - .access =3D PL1_RW, .accessfn =3D access_lor_other, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "LORC_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D= 3, - .access =3D PL1_RW, .accessfn =3D access_lor_other, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "LORID_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D= 7, - .access =3D PL1_R, .accessfn =3D access_lorid, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - REGINFO_SENTINEL - }; define_arm_cp_regs(cpu, lor_reginfo); } =20 --=20 2.20.1