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[40.133.212.210]) by smtp.gmail.com with ESMTPSA id 13sm14678975pfi.78.2020.02.01.17.04.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Feb 2020 17:04:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DvbJD7vPe2BsG6TgBfcVzI1uqZumbSEbIYT2NtMlLpk=; b=vvUjZoa+/LL0C/AN/0AGL5eMsk6DVxcaSHoBItCQCW5gHaov7jExUmTE812xO1cHSu 63jS4MAump+2TtJrxusWlT+8gsdJVg1s0Mgq/f0bcPegmF2z46PA6JF67T9dfEzM0p7Q yhX2iMVqjyMatd6teaCrxBkmNF3mwmfYElC6w5uozqmC7hGrZAcT32e0grGcy8B07T2Z imkHvxr+NULmUE4Wvap4WH2bG9ZcEN/Bes7RIY8EhMg4TF5bAuxS17Duil+cnqyyRdDh NXgoiqNdALlB04Ofvin0KEUk4OY5AeooFjMiUvetvheNMpNo4F3+oi/92tXQl97II51w AEIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DvbJD7vPe2BsG6TgBfcVzI1uqZumbSEbIYT2NtMlLpk=; b=IOd81TI473HBBhuk/54ehsXuvCmoSGTvQq81B40ndvJ2wp2ohcKMy4ExRs1mnj4sw3 zSSU1SkNgg+uZfVjCzetQbKLZ1hO3jIIVCRoKvpyY9v7jVERhSzZEvhIV/yt0oO74X6J Nrw5fyIv8TLLvVDo93bXukc94bKAPVr+QWu4oS8XOKmooTF73zAEagt+KcMBcxV3FDph F0b47SVAEdxjX8rw61/TDjvzC2mzbb3bxwq4HpW4IbcCuwl8xkYsgNt0Z5RDPDds11zR NMekt7w8By7WwqasDdzNGoAOfwJTlUXoTaEcdC15hOcRqav+2d74zf5jwZoedwzQ1tC8 Dmwg== X-Gm-Message-State: APjAAAUefvmkb0AsAqEcU5xOI7YspH+/qWNuAg8XOQZP/YOlltdf/ETD 5bhLKPbKvCM8YHzP73y9Hps3Q8Oarnc= X-Google-Smtp-Source: APXvYqxvmmrktTn4csSReixRmwT3RVqVomIOIz08EHe9EsVyAXTq8UZlaAcNBogtWE/3Gkr4JePYzg== X-Received: by 2002:a17:90a:a08e:: with SMTP id r14mr3673544pjp.120.1580605486112; Sat, 01 Feb 2020 17:04:46 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 04/14] target/arm: Move LOR regdefs to file scope Date: Sat, 1 Feb 2020 17:04:29 -0800 Message-Id: <20200202010439.6410-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200202010439.6410-1-richard.henderson@linaro.org> References: <20200202010439.6410-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1041 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" For static const regdefs, file scope is preferred. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- target/arm/helper.c | 57 +++++++++++++++++++++++---------------------- 1 file changed, 29 insertions(+), 28 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 739d2d4cc5..795ef727d0 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6343,6 +6343,35 @@ static CPAccessResult access_lor_other(CPUARMState *= env, return access_lor_ns(env); } =20 +/* + * A trivial implementation of ARMv8.1-LOR leaves all of these + * registers fixed at 0, which indicates that there are zero + * supported Limited Ordering regions. + */ +static const ARMCPRegInfo lor_reginfo[] =3D { + { .name =3D "LORSA_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D 0, + .access =3D PL1_RW, .accessfn =3D access_lor_other, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "LOREA_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D 1, + .access =3D PL1_RW, .accessfn =3D access_lor_other, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "LORN_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D 2, + .access =3D PL1_RW, .accessfn =3D access_lor_other, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "LORC_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D 3, + .access =3D PL1_RW, .accessfn =3D access_lor_other, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "LORID_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D 7, + .access =3D PL1_R, .accessfn =3D access_lorid, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + REGINFO_SENTINEL +}; + #ifdef TARGET_AARCH64 static CPAccessResult access_pauth(CPUARMState *env, const ARMCPRegInfo *r= i, bool isread) @@ -7577,34 +7606,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) } =20 if (cpu_isar_feature(aa64_lor, cpu)) { - /* - * A trivial implementation of ARMv8.1-LOR leaves all of these - * registers fixed at 0, which indicates that there are zero - * supported Limited Ordering regions. - */ - static const ARMCPRegInfo lor_reginfo[] =3D { - { .name =3D "LORSA_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D= 0, - .access =3D PL1_RW, .accessfn =3D access_lor_other, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "LOREA_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D= 1, - .access =3D PL1_RW, .accessfn =3D access_lor_other, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "LORN_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D= 2, - .access =3D PL1_RW, .accessfn =3D access_lor_other, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "LORC_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D= 3, - .access =3D PL1_RW, .accessfn =3D access_lor_other, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "LORID_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D= 7, - .access =3D PL1_R, .accessfn =3D access_lorid, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - REGINFO_SENTINEL - }; define_arm_cp_regs(cpu, lor_reginfo); } =20 --=20 2.20.1