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[40.133.212.210]) by smtp.gmail.com with ESMTPSA id 13sm14678975pfi.78.2020.02.01.17.04.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Feb 2020 17:04:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=l/G8fLMWaw+s2JrEJLiGNPxIjNmHgqejNi56OPBy7lc=; b=EgaQAMmtBFnVIr2PMYg6VORoesp4mzCyTZCJ2SXtAWppLldzgL4AqZC3GXPWB+JjiL bFhglyVtZuyRA2C5cpnfwjwe+GTvRSiBL7u2WtuOExLx31G4+u1xdb5/6YGwWjb1I7Hg cNBpOUdBFbT0nSM9vyMpciCRBZY9hqLrcMA6bIxrxzGb0G0d5IbAtCWUn6TnJ8vr7inw LkfR1z5CqIVDpMHY+o2RNssqIMVkDNSRXNZbX04VWa6hKfA3fQk1Yr18bAE6xFYninrX ItMdq8lpQjudkVjFpmVPOF/wluAmCOtZ+cvqFmK5l11GdcsyJ4XLPtSL9k0qM3TIJr/s Fg2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=l/G8fLMWaw+s2JrEJLiGNPxIjNmHgqejNi56OPBy7lc=; b=TYAy2z9yPQTa+XRVKaYbLws+YYjRaMM88nQHwFC3SASQVcwCIlj5Y6YGSSIXJZreel rLO8i7cf0JyKqFKIx0ZC8aslxJ5Kvrs1OH+hfOZtRMeiW4zQuGghRjplO5joXPi9Ofd6 6Qw9EHmdvBvhEKby1cy30OdqWrlETqjkQrEd489HgGUNVbmxWEEYeHfokGW/Qyiw/x+3 5wIQGLqWozknFKN1GDAW27wCSila/gySTvay08ydFuNG+NDZXQSHLQdVIdFBuYfTYfd3 Xuk83Ug5DNg7F8tYAmY0HHATNXCqgJHXyS36+lixLyUW69klNEyT7reXjxj2vIeFoJ22 t1zA== X-Gm-Message-State: APjAAAVObgnHOHZuVIAo5d7836/eOahFbVA151BTYiahGHU9iFLmNEFq Z6/iCtls9U0WDHgTKFpq9JdEFbk7F1E= X-Google-Smtp-Source: APXvYqz9FdR+wnYoEmij+n70m6sdjztyL6qyXI4YH5I5UX4oF5Z1oaCqJyKFEz2+O9Ue0mbigmv9tw== X-Received: by 2002:a65:6454:: with SMTP id s20mr18761683pgv.59.1580605482346; Sat, 01 Feb 2020 17:04:42 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 01/14] target/arm: Add arm_mmu_idx_is_stage1_of_2 Date: Sat, 1 Feb 2020 17:04:26 -0800 Message-Id: <20200202010439.6410-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200202010439.6410-1-richard.henderson@linaro.org> References: <20200202010439.6410-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Use a common predicate for querying stage1-ness. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- v2: Rename from arm_mmu_idx_is_stage1 to arm_mmu_idx_is_stage1_of_2 --- target/arm/internals.h | 18 ++++++++++++++++++ target/arm/helper.c | 8 +++----- 2 files changed, 21 insertions(+), 5 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 6d4a942bde..1f8ee5f573 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1034,6 +1034,24 @@ static inline ARMMMUIdx arm_stage1_mmu_idx(CPUARMSta= te *env) ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env); #endif =20 +/** + * arm_mmu_idx_is_stage1_of_2: + * @mmu_idx: The ARMMMUIdx to test + * + * Return true if @mmu_idx is a NOTLB mmu_idx that is the + * first stage of a two stage regime. + */ +static inline bool arm_mmu_idx_is_stage1_of_2(ARMMMUIdx mmu_idx) +{ + switch (mmu_idx) { + case ARMMMUIdx_Stage1_E0: + case ARMMMUIdx_Stage1_E1: + return true; + default: + return false; + } +} + /* * Parameters of a given virtual address, as extracted from the * translation control register (TCR) for a given regime. diff --git a/target/arm/helper.c b/target/arm/helper.c index 70b10428c5..852fd71dcc 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3261,8 +3261,7 @@ static uint64_t do_ats_write(CPUARMState *env, uint64= _t value, bool take_exc =3D false; =20 if (fi.s1ptw && current_el =3D=3D 1 && !arm_is_secure(env) - && (mmu_idx =3D=3D ARMMMUIdx_Stage1_E1 || - mmu_idx =3D=3D ARMMMUIdx_Stage1_E0)) { + && arm_mmu_idx_is_stage1_of_2(mmu_idx)) { /* * Synchronous stage 2 fault on an access made as part of the * translation table walk for AT S1E0* or AT S1E1* insn @@ -9294,8 +9293,7 @@ static inline bool regime_translation_disabled(CPUARM= State *env, } } =20 - if ((env->cp15.hcr_el2 & HCR_DC) && - (mmu_idx =3D=3D ARMMMUIdx_Stage1_E0 || mmu_idx =3D=3D ARMMMUIdx_St= age1_E1)) { + if ((env->cp15.hcr_el2 & HCR_DC) && arm_mmu_idx_is_stage1_of_2(mmu_idx= )) { /* HCR.DC means SCTLR_EL1.M behaves as 0 */ return true; } @@ -9604,7 +9602,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMM= MUIdx mmu_idx, hwaddr addr, MemTxAttrs txattrs, ARMMMUFaultInfo *fi) { - if ((mmu_idx =3D=3D ARMMMUIdx_Stage1_E0 || mmu_idx =3D=3D ARMMMUIdx_St= age1_E1) && + if (arm_mmu_idx_is_stage1_of_2(mmu_idx) && !regime_translation_disabled(env, ARMMMUIdx_Stage2)) { target_ulong s2size; hwaddr s2pa; --=20 2.20.1 From nobody Thu Nov 13 12:02:47 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 158060556902481.0131438907083; Sat, 1 Feb 2020 17:06:09 -0800 (PST) Received: from localhost ([::1]:52100 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iy3iB-0005Kf-St for importer@patchew.org; Sat, 01 Feb 2020 20:06:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45563) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iy3gt-0003U0-Rb for qemu-devel@nongnu.org; Sat, 01 Feb 2020 20:04:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iy3gr-0001tn-Tx for qemu-devel@nongnu.org; Sat, 01 Feb 2020 20:04:47 -0500 Received: from mail-pf1-x442.google.com ([2607:f8b0:4864:20::442]:42887) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iy3gr-0001sf-LY for qemu-devel@nongnu.org; Sat, 01 Feb 2020 20:04:45 -0500 Received: by mail-pf1-x442.google.com with SMTP id 4so5522515pfz.9 for ; Sat, 01 Feb 2020 17:04:45 -0800 (PST) Received: from cloudburst.WiFi.IPv4InfoBelow (h210.212.133.40.static.ip.windstream.net. [40.133.212.210]) by smtp.gmail.com with ESMTPSA id 13sm14678975pfi.78.2020.02.01.17.04.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Feb 2020 17:04:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lXly93NqueP/gLlxsmljJxdXiOdoAObq4hnqgfdniG8=; b=Qmy6zotaeLEuIoehGOds3kL73dXCpyGVS86Mm2ULN4p8RWkBCTY+ir4maW6OxujbVR noTOleCdOr2WPOSM47RgOIhThtV1YQC3JTE4bkhBqqYwvYea+x12kga8QS3k3bs5ltUb /iAiYgnWoGHhIPfbud7ZUTK3QDoZSegFZB+LTZja7V5wqXFutL+qVLNnHTLM8DPH4f72 uY1sSBQ1o9RvlWrUB9ZmerpyY4qdwUU6RZwOARVnMmhAnI5sWipLR86hD2UWXOB3m3cv ThWtZRmtRp0rJ94xKuXXKN0ti1rwsNr0YC79m9MCmKQwW4k/Bu2d3jGMAyDcj6DM07MT IhLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lXly93NqueP/gLlxsmljJxdXiOdoAObq4hnqgfdniG8=; b=tIV/9iXIQ71WF3WKW2yxPMVoEt/BLwk6qiAN+Yi27b62zlTlzfJxdZdtL+K71hsoaT EoDIPHP1cQsLW5kN5HTVMS3kaRnXagfrS/Avi+C5onEFjejj/465L2QrWZyO3z0aWUwL tk3/cSCjdfsEJlJqXs0o+QSDfMNbs063B0oMjCYWavraoPIEAyhmuiHepyqChmLAsaGN RQVPy15bT3yawJxU9oGFHaZYsPVgoYkn+RAOt5Tx7jZ1xmkTAlYBKORSJlIW5QR/+opC bXXQ4QcAGq9q/kwtdWBI6quHq9+Oy7fzb4TkxJiGdk0AWrwGbYl3L1gNVeTyGmMUT8We 9+tQ== X-Gm-Message-State: APjAAAV+NNxFveVjpTj4eF6CnF3T1morfyn6lUsluu+wTYdAxlvGAqB6 Eb0vN0p6NkKmhrUNOdwBFjYfrtaA9UA= X-Google-Smtp-Source: APXvYqx5zrQWsM99J7bIoO7Ke1lIRJcs5y9xAxyGRtAAKpaX37gwKNo6U8df4zCg8nebEvBtUfRspA== X-Received: by 2002:a62:fc93:: with SMTP id e141mr17225254pfh.262.1580605483608; Sat, 01 Feb 2020 17:04:43 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 02/14] target/arm: Add mmu_idx for EL1 and EL2 w/ PAN enabled Date: Sat, 1 Feb 2020 17:04:27 -0800 Message-Id: <20200202010439.6410-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200202010439.6410-1-richard.henderson@linaro.org> References: <20200202010439.6410-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" To implement PAN, we will want to swap, for short periods of time, to a different privileged mmu_idx. In addition, we cannot do this with flushing alone, because the AT* instructions have both PAN and PAN-less versions. Add the ARMMMUIdx*_PAN constants where necessary next to the corresponding ARMMMUIdx* constant. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- target/arm/cpu-param.h | 2 +- target/arm/cpu.h | 33 ++++++++++++++------- target/arm/internals.h | 9 ++++++ target/arm/helper.c | 60 +++++++++++++++++++++++++++++++------- target/arm/translate-a64.c | 3 ++ target/arm/translate.c | 2 ++ 6 files changed, 87 insertions(+), 22 deletions(-) diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 18ac562346..d593b60b28 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -29,6 +29,6 @@ # define TARGET_PAGE_BITS_MIN 10 #endif =20 -#define NB_MMU_MODES 9 +#define NB_MMU_MODES 12 =20 #endif diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0b3036c484..c63bceaaa5 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2751,20 +2751,24 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_s= ync); * 5. we want to be able to use the TLB for accesses done as part of a * stage1 page table walk, rather than having to walk the stage2 page * table over and over. + * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access + * Never (PAN) bit within PSTATE. * * This gives us the following list of cases: * * NS EL0 EL1&0 stage 1+2 (aka NS PL0) * NS EL1 EL1&0 stage 1+2 (aka NS PL1) + * NS EL1 EL1&0 stage 1+2 +PAN * NS EL0 EL2&0 - * NS EL2 EL2&0 + * NS EL2 EL2&0 +PAN * NS EL2 (aka NS PL2) * S EL0 EL1&0 (aka S PL0) * S EL1 EL1&0 (not used if EL3 is 32 bit) + * S EL1 EL1&0 +PAN * S EL3 (aka S PL1) * NS EL1&0 stage 2 * - * for a total of 9 different mmu_idx. + * for a total of 12 different mmu_idx. * * R profile CPUs have an MPU, but can use the same set of MMU indexes * as A profile. They only need to distinguish NS EL0 and NS EL1 (and @@ -2819,19 +2823,22 @@ typedef enum ARMMMUIdx { /* * A-profile. */ - ARMMMUIdx_E10_0 =3D 0 | ARM_MMU_IDX_A, - ARMMMUIdx_E20_0 =3D 1 | ARM_MMU_IDX_A, + ARMMMUIdx_E10_0 =3D 0 | ARM_MMU_IDX_A, + ARMMMUIdx_E20_0 =3D 1 | ARM_MMU_IDX_A, =20 - ARMMMUIdx_E10_1 =3D 2 | ARM_MMU_IDX_A, + ARMMMUIdx_E10_1 =3D 2 | ARM_MMU_IDX_A, + ARMMMUIdx_E10_1_PAN =3D 3 | ARM_MMU_IDX_A, =20 - ARMMMUIdx_E2 =3D 3 | ARM_MMU_IDX_A, - ARMMMUIdx_E20_2 =3D 4 | ARM_MMU_IDX_A, + ARMMMUIdx_E2 =3D 4 | ARM_MMU_IDX_A, + ARMMMUIdx_E20_2 =3D 5 | ARM_MMU_IDX_A, + ARMMMUIdx_E20_2_PAN =3D 6 | ARM_MMU_IDX_A, =20 - ARMMMUIdx_SE10_0 =3D 5 | ARM_MMU_IDX_A, - ARMMMUIdx_SE10_1 =3D 6 | ARM_MMU_IDX_A, - ARMMMUIdx_SE3 =3D 7 | ARM_MMU_IDX_A, + ARMMMUIdx_SE10_0 =3D 7 | ARM_MMU_IDX_A, + ARMMMUIdx_SE10_1 =3D 8 | ARM_MMU_IDX_A, + ARMMMUIdx_SE10_1_PAN =3D 9 | ARM_MMU_IDX_A, + ARMMMUIdx_SE3 =3D 10 | ARM_MMU_IDX_A, =20 - ARMMMUIdx_Stage2 =3D 8 | ARM_MMU_IDX_A, + ARMMMUIdx_Stage2 =3D 11 | ARM_MMU_IDX_A, =20 /* * These are not allocated TLBs and are used only for AT system @@ -2839,6 +2846,7 @@ typedef enum ARMMMUIdx { */ ARMMMUIdx_Stage1_E0 =3D 0 | ARM_MMU_IDX_NOTLB, ARMMMUIdx_Stage1_E1 =3D 1 | ARM_MMU_IDX_NOTLB, + ARMMMUIdx_Stage1_E1_PAN =3D 2 | ARM_MMU_IDX_NOTLB, =20 /* * M-profile. @@ -2864,10 +2872,13 @@ typedef enum ARMMMUIdxBit { TO_CORE_BIT(E10_0), TO_CORE_BIT(E20_0), TO_CORE_BIT(E10_1), + TO_CORE_BIT(E10_1_PAN), TO_CORE_BIT(E2), TO_CORE_BIT(E20_2), + TO_CORE_BIT(E20_2_PAN), TO_CORE_BIT(SE10_0), TO_CORE_BIT(SE10_1), + TO_CORE_BIT(SE10_1_PAN), TO_CORE_BIT(SE3), TO_CORE_BIT(Stage2), =20 diff --git a/target/arm/internals.h b/target/arm/internals.h index 1f8ee5f573..6be8b2d1a9 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -843,12 +843,16 @@ static inline bool regime_has_2_ranges(ARMMMUIdx mmu_= idx) switch (mmu_idx) { case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_Stage1_E1: + case ARMMMUIdx_Stage1_E1_PAN: case ARMMMUIdx_E10_0: case ARMMMUIdx_E10_1: + case ARMMMUIdx_E10_1_PAN: case ARMMMUIdx_E20_0: case ARMMMUIdx_E20_2: + case ARMMMUIdx_E20_2_PAN: case ARMMMUIdx_SE10_0: case ARMMMUIdx_SE10_1: + case ARMMMUIdx_SE10_1_PAN: return true; default: return false; @@ -861,10 +865,13 @@ static inline bool regime_is_secure(CPUARMState *env,= ARMMMUIdx mmu_idx) switch (mmu_idx) { case ARMMMUIdx_E10_0: case ARMMMUIdx_E10_1: + case ARMMMUIdx_E10_1_PAN: case ARMMMUIdx_E20_0: case ARMMMUIdx_E20_2: + case ARMMMUIdx_E20_2_PAN: case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_Stage1_E1: + case ARMMMUIdx_Stage1_E1_PAN: case ARMMMUIdx_E2: case ARMMMUIdx_Stage2: case ARMMMUIdx_MPrivNegPri: @@ -875,6 +882,7 @@ static inline bool regime_is_secure(CPUARMState *env, A= RMMMUIdx mmu_idx) case ARMMMUIdx_SE3: case ARMMMUIdx_SE10_0: case ARMMMUIdx_SE10_1: + case ARMMMUIdx_SE10_1_PAN: case ARMMMUIdx_MSPrivNegPri: case ARMMMUIdx_MSUserNegPri: case ARMMMUIdx_MSPriv: @@ -1046,6 +1054,7 @@ static inline bool arm_mmu_idx_is_stage1_of_2(ARMMMUI= dx mmu_idx) switch (mmu_idx) { case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_Stage1_E1: + case ARMMMUIdx_Stage1_E1_PAN: return true; default: return false; diff --git a/target/arm/helper.c b/target/arm/helper.c index 852fd71dcc..739d2d4cc5 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -671,6 +671,7 @@ static void tlbiall_nsnh_write(CPUARMState *env, const = ARMCPRegInfo *ri, =20 tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E10_1 | + ARMMMUIdxBit_E10_1_PAN | ARMMMUIdxBit_E10_0 | ARMMMUIdxBit_Stage2); } @@ -682,6 +683,7 @@ static void tlbiall_nsnh_is_write(CPUARMState *env, con= st ARMCPRegInfo *ri, =20 tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E10_1 | + ARMMMUIdxBit_E10_1_PAN | ARMMMUIdxBit_E10_0 | ARMMMUIdxBit_Stage2); } @@ -2700,6 +2702,7 @@ static int gt_phys_redir_timeridx(CPUARMState *env) switch (arm_mmu_idx(env)) { case ARMMMUIdx_E20_0: case ARMMMUIdx_E20_2: + case ARMMMUIdx_E20_2_PAN: return GTIMER_HYP; default: return GTIMER_PHYS; @@ -2711,6 +2714,7 @@ static int gt_virt_redir_timeridx(CPUARMState *env) switch (arm_mmu_idx(env)) { case ARMMMUIdx_E20_0: case ARMMMUIdx_E20_2: + case ARMMMUIdx_E20_2_PAN: return GTIMER_HYPVIRT; default: return GTIMER_VIRT; @@ -3337,7 +3341,9 @@ static uint64_t do_ats_write(CPUARMState *env, uint64= _t value, format64 =3D arm_s1_regime_using_lpae_format(env, mmu_idx); =20 if (arm_feature(env, ARM_FEATURE_EL2)) { - if (mmu_idx =3D=3D ARMMMUIdx_E10_0 || mmu_idx =3D=3D ARMMMUIdx= _E10_1) { + if (mmu_idx =3D=3D ARMMMUIdx_E10_0 || + mmu_idx =3D=3D ARMMMUIdx_E10_1 || + mmu_idx =3D=3D ARMMMUIdx_E10_1_PAN) { format64 |=3D env->cp15.hcr_el2 & (HCR_VM | HCR_DC); } else { format64 |=3D arm_current_el(env) =3D=3D 2; @@ -3797,7 +3803,9 @@ static void vmsa_tcr_ttbr_el2_write(CPUARMState *env,= const ARMCPRegInfo *ri, if (extract64(raw_read(env, ri) ^ value, 48, 16) && (arm_hcr_el2_eff(env) & HCR_E2H)) { tlb_flush_by_mmuidx(env_cpu(env), - ARMMMUIdxBit_E20_2 | ARMMMUIdxBit_E20_0); + ARMMMUIdxBit_E20_2 | + ARMMMUIdxBit_E20_2_PAN | + ARMMMUIdxBit_E20_0); } raw_write(env, ri, value); } @@ -3815,6 +3823,7 @@ static void vttbr_write(CPUARMState *env, const ARMCP= RegInfo *ri, if (raw_read(env, ri) !=3D value) { tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E10_1 | + ARMMMUIdxBit_E10_1_PAN | ARMMMUIdxBit_E10_0 | ARMMMUIdxBit_Stage2); raw_write(env, ri, value); @@ -4175,12 +4184,18 @@ static int vae1_tlbmask(CPUARMState *env) { /* Since we exclude secure first, we may read HCR_EL2 directly. */ if (arm_is_secure_below_el3(env)) { - return ARMMMUIdxBit_SE10_1 | ARMMMUIdxBit_SE10_0; + return ARMMMUIdxBit_SE10_1 | + ARMMMUIdxBit_SE10_1_PAN | + ARMMMUIdxBit_SE10_0; } else if ((env->cp15.hcr_el2 & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)) { - return ARMMMUIdxBit_E20_2 | ARMMMUIdxBit_E20_0; + return ARMMMUIdxBit_E20_2 | + ARMMMUIdxBit_E20_2_PAN | + ARMMMUIdxBit_E20_0; } else { - return ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_0; + return ARMMMUIdxBit_E10_1 | + ARMMMUIdxBit_E10_1_PAN | + ARMMMUIdxBit_E10_0; } } =20 @@ -4214,18 +4229,28 @@ static int alle1_tlbmask(CPUARMState *env) * stage 1 translations. */ if (arm_is_secure_below_el3(env)) { - return ARMMMUIdxBit_SE10_1 | ARMMMUIdxBit_SE10_0; + return ARMMMUIdxBit_SE10_1 | + ARMMMUIdxBit_SE10_1_PAN | + ARMMMUIdxBit_SE10_0; } else if (arm_feature(env, ARM_FEATURE_EL2)) { - return ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_0 | ARMMMUIdxBit_Stag= e2; + return ARMMMUIdxBit_E10_1 | + ARMMMUIdxBit_E10_1_PAN | + ARMMMUIdxBit_E10_0 | + ARMMMUIdxBit_Stage2; } else { - return ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_0; + return ARMMMUIdxBit_E10_1 | + ARMMMUIdxBit_E10_1_PAN | + ARMMMUIdxBit_E10_0; } } =20 static int alle2_tlbmask(CPUARMState *env) { /* TODO: ARMv8.4-SecEL2 */ - return ARMMMUIdxBit_E20_0 | ARMMMUIdxBit_E20_2 | ARMMMUIdxBit_E2; + return ARMMMUIdxBit_E20_0 | + ARMMMUIdxBit_E20_2 | + ARMMMUIdxBit_E20_2_PAN | + ARMMMUIdxBit_E2; } =20 static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -9215,6 +9240,7 @@ static uint32_t regime_el(CPUARMState *env, ARMMMUIdx= mmu_idx) switch (mmu_idx) { case ARMMMUIdx_E20_0: case ARMMMUIdx_E20_2: + case ARMMMUIdx_E20_2_PAN: case ARMMMUIdx_Stage2: case ARMMMUIdx_E2: return 2; @@ -9223,10 +9249,13 @@ static uint32_t regime_el(CPUARMState *env, ARMMMUI= dx mmu_idx) case ARMMMUIdx_SE10_0: return arm_el_is_aa64(env, 3) ? 1 : 3; case ARMMMUIdx_SE10_1: + case ARMMMUIdx_SE10_1_PAN: case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_Stage1_E1: + case ARMMMUIdx_Stage1_E1_PAN: case ARMMMUIdx_E10_0: case ARMMMUIdx_E10_1: + case ARMMMUIdx_E10_1_PAN: case ARMMMUIdx_MPrivNegPri: case ARMMMUIdx_MUserNegPri: case ARMMMUIdx_MPriv: @@ -9342,6 +9371,8 @@ static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu= _idx) return ARMMMUIdx_Stage1_E0; case ARMMMUIdx_E10_1: return ARMMMUIdx_Stage1_E1; + case ARMMMUIdx_E10_1_PAN: + return ARMMMUIdx_Stage1_E1_PAN; default: return mmu_idx; } @@ -9388,6 +9419,7 @@ static inline bool regime_is_user(CPUARMState *env, A= RMMMUIdx mmu_idx) return false; case ARMMMUIdx_E10_0: case ARMMMUIdx_E10_1: + case ARMMMUIdx_E10_1_PAN: g_assert_not_reached(); } } @@ -11280,7 +11312,9 @@ bool get_phys_addr(CPUARMState *env, target_ulong a= ddress, target_ulong *page_size, ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) { - if (mmu_idx =3D=3D ARMMMUIdx_E10_0 || mmu_idx =3D=3D ARMMMUIdx_E10_1) { + if (mmu_idx =3D=3D ARMMMUIdx_E10_0 || + mmu_idx =3D=3D ARMMMUIdx_E10_1 || + mmu_idx =3D=3D ARMMMUIdx_E10_1_PAN) { /* Call ourselves recursively to do the stage 1 and then stage 2 * translations. */ @@ -11807,10 +11841,13 @@ int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) case ARMMMUIdx_SE10_0: return 0; case ARMMMUIdx_E10_1: + case ARMMMUIdx_E10_1_PAN: case ARMMMUIdx_SE10_1: + case ARMMMUIdx_SE10_1_PAN: return 1; case ARMMMUIdx_E2: case ARMMMUIdx_E20_2: + case ARMMMUIdx_E20_2_PAN: return 2; case ARMMMUIdx_SE3: return 3; @@ -12027,11 +12064,14 @@ static uint32_t rebuild_hflags_a64(CPUARMState *e= nv, int el, int fp_el, /* TODO: ARMv8.2-UAO */ switch (mmu_idx) { case ARMMMUIdx_E10_1: + case ARMMMUIdx_E10_1_PAN: case ARMMMUIdx_SE10_1: + case ARMMMUIdx_SE10_1_PAN: /* TODO: ARMv8.3-NV */ flags =3D FIELD_DP32(flags, TBFLAG_A64, UNPRIV, 1); break; case ARMMMUIdx_E20_2: + case ARMMMUIdx_E20_2_PAN: /* TODO: ARMv8.4-SecEL2 */ /* * Note that E20_2 is gated by HCR_EL2.E2H =3D=3D 1, but E20_0 is diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 6e82486884..49631c2340 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -124,12 +124,15 @@ static int get_a64_user_mem_index(DisasContext *s) */ switch (useridx) { case ARMMMUIdx_E10_1: + case ARMMMUIdx_E10_1_PAN: useridx =3D ARMMMUIdx_E10_0; break; case ARMMMUIdx_E20_2: + case ARMMMUIdx_E20_2_PAN: useridx =3D ARMMMUIdx_E20_0; break; case ARMMMUIdx_SE10_1: + case ARMMMUIdx_SE10_1_PAN: useridx =3D ARMMMUIdx_SE10_0; break; default: diff --git a/target/arm/translate.c b/target/arm/translate.c index e11a5871d0..d58c328e08 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -155,10 +155,12 @@ static inline int get_a32_user_mem_index(DisasContext= *s) case ARMMMUIdx_E2: /* this one is UNPREDICTABLE */ case ARMMMUIdx_E10_0: case ARMMMUIdx_E10_1: + case ARMMMUIdx_E10_1_PAN: return arm_to_core_mmu_idx(ARMMMUIdx_E10_0); case ARMMMUIdx_SE3: case ARMMMUIdx_SE10_0: case ARMMMUIdx_SE10_1: + case ARMMMUIdx_SE10_1_PAN: return arm_to_core_mmu_idx(ARMMMUIdx_SE10_0); case ARMMMUIdx_MUser: case ARMMMUIdx_MPriv: --=20 2.20.1 From nobody Thu Nov 13 12:02:47 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[40.133.212.210]) by smtp.gmail.com with ESMTPSA id 13sm14678975pfi.78.2020.02.01.17.04.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Feb 2020 17:04:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hPQ0dR0RCVOoDHLNqnKbILWZrurFdQJzDpp0jJ4Jtv4=; b=PMDiici73X5qrzNu3CGsv++vvI7YAWVLMsXO2GjxyqJohfoAQj6m9r+CCzGf3voyBY IXveZCVic9//JAcYsq0OkKuUnggyDdXm8wKyiSXi6dvhtgytPSzRks7ovC1un0eWB9Z9 F125KVK8fW1pMOCcTMuP3XmapQ6bUoPfiuY53G8Z0DopQELVMEUD1KfQtBWEx0AXYNLR P1moRd5RfJuCPDbHVI44dUhUltYxmdc2X39v5vFh6woP3S7OAmBMbjt9BYZ0TaFvvee1 HQU6cdoNnqFSnZ3Wn52q8NvocrtZ83Ia4q/8bbunl8y5YJyDxRvZU7T7L+5ng4FuXAXY 0NFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hPQ0dR0RCVOoDHLNqnKbILWZrurFdQJzDpp0jJ4Jtv4=; b=s+N/NqHsIKx1LdlN1rlcQTvp5wub65secYU7UpCHKy+ZrlYB5YjWAcL3Ou6eJsLmb3 nilToRPzeNBUPdHFt/V/Y3KeTZtY6QXcxbww625lVNouFy8jYgcQGykHfD0o63Q9QoNi z0gIwVT0nC7zbOkxscB6S8oRNNyaevOyr4WsvSJCPCbU1LHSHatSs8ceH9eb756GfBfl fsJ+q7+9BrauH0wmpch6T7VxocZ6m2a5bKbipVBGmwSjkycbtIqM7TLTwTKbht9rSUyF 5owbIO+uob3EotUel9hAANEGq11pU99CcyquDz2zlHFPQxDia9MgB70UmtVwdaFb1mPR kP6Q== X-Gm-Message-State: APjAAAXXH2TQAqAwul4PxHcY0Sp6fE1w8lzwllDL4Ag64SdBXk90Yj99 MpLkJzRLLR4L/ZNmV+vqhtPOgo7lT0A= X-Google-Smtp-Source: APXvYqynsExQQSTXqD5AMJW32L5Uu2PO2ieHj1Sc7/yDlGoitZ7+Ns5iyw/5sUXO35VVcB9+WxPHAw== X-Received: by 2002:a62:5547:: with SMTP id j68mr18389545pfb.6.1580605484830; Sat, 01 Feb 2020 17:04:44 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 03/14] target/arm: Add isar_feature tests for PAN + ATS1E1 Date: Sat, 1 Feb 2020 17:04:28 -0800 Message-Id: <20200202010439.6410-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200202010439.6410-1-richard.henderson@linaro.org> References: <20200202010439.6410-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Include definitions for all of the bits in ID_MMFR3. We already have a definition for ID_AA64MMFR1.PAN. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- target/arm/cpu.h | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c63bceaaa5..08b2f5d73e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1727,6 +1727,15 @@ FIELD(ID_ISAR6, FHM, 8, 4) FIELD(ID_ISAR6, SB, 12, 4) FIELD(ID_ISAR6, SPECRES, 16, 4) =20 +FIELD(ID_MMFR3, CMAINTVA, 0, 4) +FIELD(ID_MMFR3, CMAINTSW, 4, 4) +FIELD(ID_MMFR3, BPMAINT, 8, 4) +FIELD(ID_MMFR3, MAINTBCST, 12, 4) +FIELD(ID_MMFR3, PAN, 16, 4) +FIELD(ID_MMFR3, COHWALK, 20, 4) +FIELD(ID_MMFR3, CMEMSZ, 24, 4) +FIELD(ID_MMFR3, SUPERSEC, 28, 4) + FIELD(ID_MMFR4, SPECSEI, 0, 4) FIELD(ID_MMFR4, AC2, 4, 4) FIELD(ID_MMFR4, XNX, 8, 4) @@ -3443,6 +3452,16 @@ static inline bool isar_feature_aa32_vminmaxnm(const= ARMISARegisters *id) return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >=3D 4; } =20 +static inline bool isar_feature_aa32_pan(const ARMISARegisters *id) +{ + return FIELD_EX64(id->mvfr0, ID_MMFR3, PAN) !=3D 0; +} + +static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id) +{ + return FIELD_EX64(id->mvfr0, ID_MMFR3, PAN) >=3D 2; +} + /* * 64-bit feature tests via id registers. */ @@ -3602,6 +3621,16 @@ static inline bool isar_feature_aa64_lor(const ARMIS= ARegisters *id) return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) !=3D 0; } =20 +static inline bool isar_feature_aa64_pan(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) !=3D 0; +} + +static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >=3D 2; +} + static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) !=3D 0; --=20 2.20.1 From nobody Thu Nov 13 12:02:47 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 158060564441295.98837188771142; Sat, 1 Feb 2020 17:07:24 -0800 (PST) Received: from localhost ([::1]:52144 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iy3jP-00008e-5J for importer@patchew.org; Sat, 01 Feb 2020 20:07:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45578) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iy3gu-0003VD-Nm for qemu-devel@nongnu.org; Sat, 01 Feb 2020 20:04:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iy3gt-0001wa-IE for qemu-devel@nongnu.org; Sat, 01 Feb 2020 20:04:48 -0500 Received: from mail-pj1-x1041.google.com ([2607:f8b0:4864:20::1041]:39811) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iy3gt-0001vK-Cc for qemu-devel@nongnu.org; Sat, 01 Feb 2020 20:04:47 -0500 Received: by mail-pj1-x1041.google.com with SMTP id e9so4737566pjr.4 for ; Sat, 01 Feb 2020 17:04:47 -0800 (PST) Received: from cloudburst.WiFi.IPv4InfoBelow (h210.212.133.40.static.ip.windstream.net. [40.133.212.210]) by smtp.gmail.com with ESMTPSA id 13sm14678975pfi.78.2020.02.01.17.04.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Feb 2020 17:04:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DvbJD7vPe2BsG6TgBfcVzI1uqZumbSEbIYT2NtMlLpk=; b=vvUjZoa+/LL0C/AN/0AGL5eMsk6DVxcaSHoBItCQCW5gHaov7jExUmTE812xO1cHSu 63jS4MAump+2TtJrxusWlT+8gsdJVg1s0Mgq/f0bcPegmF2z46PA6JF67T9dfEzM0p7Q yhX2iMVqjyMatd6teaCrxBkmNF3mwmfYElC6w5uozqmC7hGrZAcT32e0grGcy8B07T2Z imkHvxr+NULmUE4Wvap4WH2bG9ZcEN/Bes7RIY8EhMg4TF5bAuxS17Duil+cnqyyRdDh NXgoiqNdALlB04Ofvin0KEUk4OY5AeooFjMiUvetvheNMpNo4F3+oi/92tXQl97II51w AEIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DvbJD7vPe2BsG6TgBfcVzI1uqZumbSEbIYT2NtMlLpk=; b=IOd81TI473HBBhuk/54ehsXuvCmoSGTvQq81B40ndvJ2wp2ohcKMy4ExRs1mnj4sw3 zSSU1SkNgg+uZfVjCzetQbKLZ1hO3jIIVCRoKvpyY9v7jVERhSzZEvhIV/yt0oO74X6J Nrw5fyIv8TLLvVDo93bXukc94bKAPVr+QWu4oS8XOKmooTF73zAEagt+KcMBcxV3FDph F0b47SVAEdxjX8rw61/TDjvzC2mzbb3bxwq4HpW4IbcCuwl8xkYsgNt0Z5RDPDds11zR NMekt7w8By7WwqasDdzNGoAOfwJTlUXoTaEcdC15hOcRqav+2d74zf5jwZoedwzQ1tC8 Dmwg== X-Gm-Message-State: APjAAAUefvmkb0AsAqEcU5xOI7YspH+/qWNuAg8XOQZP/YOlltdf/ETD 5bhLKPbKvCM8YHzP73y9Hps3Q8Oarnc= X-Google-Smtp-Source: APXvYqxvmmrktTn4csSReixRmwT3RVqVomIOIz08EHe9EsVyAXTq8UZlaAcNBogtWE/3Gkr4JePYzg== X-Received: by 2002:a17:90a:a08e:: with SMTP id r14mr3673544pjp.120.1580605486112; Sat, 01 Feb 2020 17:04:46 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 04/14] target/arm: Move LOR regdefs to file scope Date: Sat, 1 Feb 2020 17:04:29 -0800 Message-Id: <20200202010439.6410-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200202010439.6410-1-richard.henderson@linaro.org> References: <20200202010439.6410-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1041 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" For static const regdefs, file scope is preferred. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- target/arm/helper.c | 57 +++++++++++++++++++++++---------------------- 1 file changed, 29 insertions(+), 28 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 739d2d4cc5..795ef727d0 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6343,6 +6343,35 @@ static CPAccessResult access_lor_other(CPUARMState *= env, return access_lor_ns(env); } =20 +/* + * A trivial implementation of ARMv8.1-LOR leaves all of these + * registers fixed at 0, which indicates that there are zero + * supported Limited Ordering regions. + */ +static const ARMCPRegInfo lor_reginfo[] =3D { + { .name =3D "LORSA_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D 0, + .access =3D PL1_RW, .accessfn =3D access_lor_other, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "LOREA_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D 1, + .access =3D PL1_RW, .accessfn =3D access_lor_other, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "LORN_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D 2, + .access =3D PL1_RW, .accessfn =3D access_lor_other, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "LORC_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D 3, + .access =3D PL1_RW, .accessfn =3D access_lor_other, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "LORID_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D 7, + .access =3D PL1_R, .accessfn =3D access_lorid, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + REGINFO_SENTINEL +}; + #ifdef TARGET_AARCH64 static CPAccessResult access_pauth(CPUARMState *env, const ARMCPRegInfo *r= i, bool isread) @@ -7577,34 +7606,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) } =20 if (cpu_isar_feature(aa64_lor, cpu)) { - /* - * A trivial implementation of ARMv8.1-LOR leaves all of these - * registers fixed at 0, which indicates that there are zero - * supported Limited Ordering regions. - */ - static const ARMCPRegInfo lor_reginfo[] =3D { - { .name =3D "LORSA_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D= 0, - .access =3D PL1_RW, .accessfn =3D access_lor_other, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "LOREA_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D= 1, - .access =3D PL1_RW, .accessfn =3D access_lor_other, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "LORN_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D= 2, - .access =3D PL1_RW, .accessfn =3D access_lor_other, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "LORC_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D= 3, - .access =3D PL1_RW, .accessfn =3D access_lor_other, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "LORID_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D= 7, - .access =3D PL1_R, .accessfn =3D access_lorid, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - REGINFO_SENTINEL - }; define_arm_cp_regs(cpu, lor_reginfo); } =20 --=20 2.20.1 From nobody Thu Nov 13 12:02:47 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 158060564090679.4928106668076; Sat, 1 Feb 2020 17:07:20 -0800 (PST) Received: from localhost ([::1]:52140 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iy3jL-0008NW-6P for importer@patchew.org; Sat, 01 Feb 2020 20:07:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45606) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iy3gw-0003Y2-Ep for qemu-devel@nongnu.org; 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[40.133.212.210]) by smtp.gmail.com with ESMTPSA id 13sm14678975pfi.78.2020.02.01.17.04.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Feb 2020 17:04:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2dN7CvXa72imyZeXEO8CPZOnz+QzApICtq/G6FJy1z4=; b=ZYIJxZNMn+Cuf/SgOVYrAv6nGy7xOv59j1lQvOh3gjCFiMfLSsyfqMsDH191JkIAyq IjyXrIBhQG99B+pMY6NZp5lUjjQhxdYXdt+ZeSCddtWcXAbsuSrqpEOr79ppLvPop0fK QdKtPiD+u7f9o80enhcXh0gJyQEvfMsRtRUlo0YQsq5+X9Wh7ccBjyfBGz9168WY0Lzc zhyO85q6B2owsMFSaDLoRh7dhlPKyjGdzpH8dOr4A+4NK/aqQGR9z53kIateVLFwVdZS MAuWYYuNncUUQ24JGey1NclrMZzoLg/ld4XuY+c+1GOzj7NOh98BvKYj8C0Ufh23jUEw LQmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2dN7CvXa72imyZeXEO8CPZOnz+QzApICtq/G6FJy1z4=; b=DW3CEbhQWMTPmcwmZxiaGBxo/weU6XZZS5EbqDWxNp/WPFycfsWFp3hSKOLcRlNNqb vNbTbUZ6yK7KeN+oyxXGvnC2CN6RSG65JxmCk1BbdKX6VRVqqBbJlKm4rcf0lnQPIEFO 1iGkuBIf6pMOqXvwuWvi1sTgD0OBoT42t9KP+nj7yxPqN9Nk3wIVy8mXfjZpYRH80Qhd kdQG2ZjDtVapy3XQNiyZKXjUd2qOAM/iA2N1omgGTympXnhN2hvAPUGuPxjpahHwBTSn QGRBp1SnuVt1dpRWnEskDR0xrZUl9NQFbdXr1HK8Ypc2zNd3sl6gJGG6xoCRDh/9t0Fr kyng== X-Gm-Message-State: APjAAAW9bJAnSi/lTIudJhwAC3FuvtvyIBHhcZuJqm9bIozmNm6jwkDL pHCg6hOB4iHjT4jkeR4NHqTTrhP/Szc= X-Google-Smtp-Source: APXvYqxfUYg7SFsKjXO1kmeDV7bOfh9f0RF+Npxr1zOHRm86voNIa8n/uGBo9m+DeS7wD/5PfWPR7g== X-Received: by 2002:a17:90a:2ec5:: with SMTP id h5mr21250636pjs.79.1580605487261; Sat, 01 Feb 2020 17:04:47 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 05/14] target/arm: Update MSR access for PAN Date: Sat, 1 Feb 2020 17:04:30 -0800 Message-Id: <20200202010439.6410-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200202010439.6410-1-richard.henderson@linaro.org> References: <20200202010439.6410-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1041 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" For aarch64, there's a dedicated msr (imm, reg) insn. For aarch32, this is done via msr to cpsr; and writes from el0 are ignored. Since v8.0, the CPSR_RESERVED bits have been allocated. We are not yet implementing ARMv8.0-SSBS or ARMv8.4-DIT, so retain CPSR_RESERVED for now, so that the bits remain RES0. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- v2: Move regdef to file scope; merge patch for CPSR_RESERVED: do not remove CPSR_SSBS from CPSR_RESERVED yet, mask PAN from CPSR if feature not enabled (pmm). --- target/arm/cpu.h | 11 +++++++++-- target/arm/helper-a64.c | 6 ++++++ target/arm/helper.c | 21 +++++++++++++++++++++ target/arm/op_helper.c | 9 ++++++++- target/arm/translate-a64.c | 14 ++++++++++++++ target/arm/translate.c | 6 +++++- 6 files changed, 63 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 08b2f5d73e..b11fdc3001 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1186,12 +1186,18 @@ void pmu_init(ARMCPU *cpu); #define CPSR_IT_2_7 (0xfc00U) #define CPSR_GE (0xfU << 16) #define CPSR_IL (1U << 20) -/* Note that the RESERVED bits include bit 21, which is PSTATE_SS in +/* + * Note that the RESERVED bits include bit 21, which is PSTATE_SS in * an AArch64 SPSR but RES0 in AArch32 SPSR and CPSR. In QEMU we use * env->uncached_cpsr bit 21 to store PSTATE.SS when executing in AArch32, * where it is live state but not accessible to the AArch32 code. + * + * TODO: With ARMv8.4-DIT, bit 21 is DIT in AArch32 (bit 24 for AArch64). + * We will need to move AArch32 SS somewhere else at that point. + * TODO: With ARMv8.0-SSBS, bit 23 is SSBS in AArch32 (bit 12 for AArch64). */ -#define CPSR_RESERVED (0x7U << 21) +#define CPSR_RESERVED (5U << 21) +#define CPSR_PAN (1U << 22) #define CPSR_J (1U << 24) #define CPSR_IT_0_1 (3U << 25) #define CPSR_Q (1U << 27) @@ -1258,6 +1264,7 @@ void pmu_init(ARMCPU *cpu); #define PSTATE_BTYPE (3U << 10) #define PSTATE_IL (1U << 20) #define PSTATE_SS (1U << 21) +#define PSTATE_PAN (1U << 22) #define PSTATE_V (1U << 28) #define PSTATE_C (1U << 29) #define PSTATE_Z (1U << 30) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index bf45f8a785..70d6407f80 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -1014,6 +1014,9 @@ void HELPER(exception_return)(CPUARMState *env, uint6= 4_t new_pc) * will sort the register banks out for us, and we've already * caught all the bad-mode cases in el_from_spsr(). */ + if (!cpu_isar_feature(aa32_pan, env_archcpu(env))) { + spsr &=3D ~CPSR_PAN; + } cpsr_write(env, spsr, ~0, CPSRWriteRaw); if (!arm_singlestep_active(env)) { env->uncached_cpsr &=3D ~PSTATE_SS; @@ -1031,6 +1034,9 @@ void HELPER(exception_return)(CPUARMState *env, uint6= 4_t new_pc) cur_el, new_el, env->regs[15]); } else { env->aarch64 =3D 1; + if (!cpu_isar_feature(aa64_pan, env_archcpu(env))) { + spsr &=3D ~PSTATE_PAN; + } pstate_write(env, spsr); if (!arm_singlestep_active(env)) { env->pstate &=3D ~PSTATE_SS; diff --git a/target/arm/helper.c b/target/arm/helper.c index 795ef727d0..90a22921dc 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4163,6 +4163,24 @@ static void aa64_daif_write(CPUARMState *env, const = ARMCPRegInfo *ri, env->daif =3D value & PSTATE_DAIF; } =20 +static uint64_t aa64_pan_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->pstate & PSTATE_PAN; +} + +static void aa64_pan_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + env->pstate =3D (env->pstate & ~PSTATE_PAN) | (value & PSTATE_PAN); +} + +static const ARMCPRegInfo pan_reginfo =3D { + .name =3D "PAN", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 4, .crm =3D 2, .opc2 =3D 3, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_RW, + .readfn =3D aa64_pan_read, .writefn =3D aa64_pan_write +}; + static CPAccessResult aa64_cacheop_access(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) @@ -7608,6 +7626,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_lor, cpu)) { define_arm_cp_regs(cpu, lor_reginfo); } + if (cpu_isar_feature(aa64_pan, cpu)) { + define_one_arm_cp_reg(cpu, &pan_reginfo); + } =20 if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu= )) { define_arm_cp_regs(cpu, vhe_reginfo); diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 27d16ad9ad..7ba578e826 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -400,11 +400,18 @@ void HELPER(cpsr_write)(CPUARMState *env, uint32_t va= l, uint32_t mask) /* Write the CPSR for a 32-bit exception return */ void HELPER(cpsr_write_eret)(CPUARMState *env, uint32_t val) { + uint32_t mask; + qemu_mutex_lock_iothread(); arm_call_pre_el_change_hook(env_archcpu(env)); qemu_mutex_unlock_iothread(); =20 - cpsr_write(env, val, CPSR_ERET_MASK, CPSRWriteExceptionReturn); + mask =3D CPSR_ERET_MASK; + if (!cpu_isar_feature(aa32_pan, env_archcpu(env))) { + mask &=3D ~CPSR_PAN; + } + + cpsr_write(env, val, mask, CPSRWriteExceptionReturn); =20 /* Generated code has already stored the new PC value, but * without masking out its low bits, because which bits need diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 49631c2340..d8ba240a15 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1602,6 +1602,20 @@ static void handle_msr_i(DisasContext *s, uint32_t i= nsn, s->base.is_jmp =3D DISAS_NEXT; break; =20 + case 0x04: /* PAN */ + if (!dc_isar_feature(aa64_pan, s) || s->current_el =3D=3D 0) { + goto do_unallocated; + } + if (crm & 1) { + set_pstate_bits(PSTATE_PAN); + } else { + clear_pstate_bits(PSTATE_PAN); + } + t1 =3D tcg_const_i32(s->current_el); + gen_helper_rebuild_hflags_a64(cpu_env, t1); + tcg_temp_free_i32(t1); + break; + case 0x05: /* SPSel */ if (s->current_el =3D=3D 0) { goto do_unallocated; diff --git a/target/arm/translate.c b/target/arm/translate.c index d58c328e08..0b1f0e0fea 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -2760,13 +2760,17 @@ static uint32_t msr_mask(DisasContext *s, int flags= , int spsr) if (!arm_dc_feature(s, ARM_FEATURE_THUMB2)) { mask &=3D ~CPSR_IT; } + if (!dc_isar_feature(aa32_pan, s)) { + mask &=3D ~CPSR_PAN; + } /* Mask out execution state and reserved bits. */ if (!spsr) { mask &=3D ~(CPSR_EXEC | CPSR_RESERVED); } /* Mask out privileged bits. */ - if (IS_USER(s)) + if (IS_USER(s)) { mask &=3D CPSR_USER; + } return mask; } =20 --=20 2.20.1 From nobody Thu Nov 13 12:02:47 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580605716310503.4037713827371; Sat, 1 Feb 2020 17:08:36 -0800 (PST) Received: from localhost ([::1]:52184 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iy3kZ-0002zs-9A for importer@patchew.org; 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[40.133.212.210]) by smtp.gmail.com with ESMTPSA id 13sm14678975pfi.78.2020.02.01.17.04.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Feb 2020 17:04:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Vm99WKNsbIgWAw0gtT4tkIR4+ETnRFNvmZH5RsHuOfI=; b=PdE5fkFrg8A8UJiG/TF69h1FFceh69fibJBHeJjz8ZgMVAQMgQw5EBSLyi9SqGEDX4 e6Bdinb9ZZMAeJUQIJaQiC457uZSzj8myDjAdQWT7BMh26rPrp+1JX1f1NZS7WgRgyd7 C9cM4s8y/iZmc+Sb2EwXxJb/Ztl+w4lmripTiZkou+hHYLWfQI8PI5OZeZkJnAaMJJtF xHVFnl5Nq+16YGRPcmh7GoJKLy7tjgBAXa1S+hPMDa3G3Wsd2qLwpfSn4ASnvZPcEm6E Vn3SDxXVArdr8gGEy9P3HaG2TqxNLjfN4Pyvs8y9034Vk/BospJPuiUNLtDQz1BJRyGs 2RTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Vm99WKNsbIgWAw0gtT4tkIR4+ETnRFNvmZH5RsHuOfI=; b=Om3epyU4TS/As2PBcjB4kpG26duUTAL8L/nPn/SvllwWOeQdWhm0gqy2I7kCMaIL8c UF8cJI0LTA3snK2yov98FKfN2B12n13NipoTCWIaBHWwvJ5JnlHvrFCxqn0j8iVNVuwL ri8D6artIkM92sHaYZ5N8EOS991+eSdUfJJOamNH6q9JxYAlFILUTp8yNJC9B7V8bDb8 mcHS/JiBWZx6iLtEnYG4QlLLtztDWHBmf+tWRMYG6WwNHv9RGFvEL4N3pz2pYkuNYhjT V6Fi1awef0iM3JyAja7/VMM+jLxXLEoooOGAliyL7FEW7qsDpRY8Udds9gD9gQkAOfhd 0lkg== X-Gm-Message-State: APjAAAUKucxKsUlKBLkrGnP9Vrkr36r4vZqdjufzDEmvHDYasuMhv8tl Z2h8ANmp3ESRVu0njdPiKCN+cSlDw8U= X-Google-Smtp-Source: APXvYqw0XqwXY8swZZaxxc2zioeMhKT6UH91gvgw7kRRrx8rAC85rBTWLLDmclIBVh4NnMr/80KDWA== X-Received: by 2002:a63:ba43:: with SMTP id l3mr3402636pgu.120.1580605488451; Sat, 01 Feb 2020 17:04:48 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 06/14] target/arm: Update arm_mmu_idx_el for PAN Date: Sat, 1 Feb 2020 17:04:31 -0800 Message-Id: <20200202010439.6410-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200202010439.6410-1-richard.henderson@linaro.org> References: <20200202010439.6410-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Examine the PAN bit for EL1, EL2, and Secure EL1 to determine if it applies. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- target/arm/helper.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 90a22921dc..638abe6af0 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11904,13 +11904,22 @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el) return ARMMMUIdx_E10_0; case 1: if (arm_is_secure_below_el3(env)) { + if (env->pstate & PSTATE_PAN) { + return ARMMMUIdx_SE10_1_PAN; + } return ARMMMUIdx_SE10_1; } + if (env->pstate & PSTATE_PAN) { + return ARMMMUIdx_E10_1_PAN; + } return ARMMMUIdx_E10_1; case 2: /* TODO: ARMv8.4-SecEL2 */ /* Note that TGE does not apply at EL2. */ if ((env->cp15.hcr_el2 & HCR_E2H) && arm_el_is_aa64(env, 2)) { + if (env->pstate & PSTATE_PAN) { + return ARMMMUIdx_E20_2_PAN; + } return ARMMMUIdx_E20_2; } return ARMMMUIdx_E2; --=20 2.20.1 From nobody Thu Nov 13 12:02:47 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580605718851142.69756267840216; Sat, 1 Feb 2020 17:08:38 -0800 (PST) Received: from localhost ([::1]:52188 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iy3kb-00036R-Qt for importer@patchew.org; Sat, 01 Feb 2020 20:08:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45635) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iy3gy-0003dM-5A for qemu-devel@nongnu.org; Sat, 01 Feb 2020 20:04:53 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iy3gx-00024I-4Z for qemu-devel@nongnu.org; Sat, 01 Feb 2020 20:04:52 -0500 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:34090) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iy3gw-00022w-UJ for qemu-devel@nongnu.org; Sat, 01 Feb 2020 20:04:51 -0500 Received: by mail-pg1-x541.google.com with SMTP id j4so5748889pgi.1 for ; Sat, 01 Feb 2020 17:04:50 -0800 (PST) Received: from cloudburst.WiFi.IPv4InfoBelow (h210.212.133.40.static.ip.windstream.net. [40.133.212.210]) by smtp.gmail.com with ESMTPSA id 13sm14678975pfi.78.2020.02.01.17.04.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Feb 2020 17:04:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=U1CXib6JNYX6xUt67ormhDS8FAN7+A7WszdUWC4DAwU=; b=vUh6Ca+UaYzIBPj9QmdQoAB8fVRDMeiEbBjr2APcdq7JQqfuPmI9PTFQ+RC9bsO/EY 5ZRe7Gvaj6aaqiNahLoreV19WaDePDKbprA5FqvCDyrUkhWmGsIyvRDzBeK8sM9XnTbn oqBW7fHxQtliiQc0DgkgbGvEU5dTockkbpu9E+pXe3XfjyxYVDaYfMO4JY3Ue9Lx9/E+ zLMgeTFB0sv6Tz+72aac3uVmi8zmDgkSpxrZEDYIiXG9cTkN/6VtSsGRWdhA0AvDDcAX 1HqVnmbldnQoF+C445l4X31ymyY2/Gs980N1klyOhpW+1LWfkjdPr+xL9+A5+rmQYl5P GJBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=U1CXib6JNYX6xUt67ormhDS8FAN7+A7WszdUWC4DAwU=; b=D98GqwXqEGjVED2sU39Qlq/CHnbq7+adR3yqEMomujgjDQTJEr7vmggERryKwi4bp9 pMWmHh97Hmencjwwhn2CqdYZ/kuZujU2KdM0jI1cVDgWuYxv+aPrt4JXIQQpPE8xHG3W Se0aGHeoZ9fUqBsYCep56yhEQVz6cUuJCLhtr0dD0lNaZIV8x9RC57IVYwq1cN984VbP 1Z15KgDxDvSrmwpGHjxLuj4X00h2y60v2q7DU+sbpUwuX6SzMcnxc0yuwIYeYkRutXg7 jfsowZfVbS+pogKPpRIXKIOvMjCEHcecJKqczmgEUgDUQb2/7fOZmV6bn9F3BbDWMpN5 JMOQ== X-Gm-Message-State: APjAAAVuWgtHLInmpLpsWmj7SdKroY1k8miaw39aHSNX7k7oaodKpZ/7 8EHtMf/ah7TeklPIja6dbZmdy0W6LAg= X-Google-Smtp-Source: APXvYqx31egw9nUshmCihxP2bBcOIAkgU0CVLuRPU/pc5yXIDcYpVKYhzanTHZyct80QGVJ05p4WfA== X-Received: by 2002:aa7:947b:: with SMTP id t27mr18395390pfq.212.1580605489713; Sat, 01 Feb 2020 17:04:49 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 07/14] target/arm: Enforce PAN semantics in get_S1prot Date: Sat, 1 Feb 2020 17:04:32 -0800 Message-Id: <20200202010439.6410-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200202010439.6410-1-richard.henderson@linaro.org> References: <20200202010439.6410-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" If we have a PAN-enforcing mmu_idx, set prot =3D=3D 0 if user_rw !=3D 0. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- target/arm/internals.h | 13 +++++++++++++ target/arm/helper.c | 3 +++ 2 files changed, 16 insertions(+) diff --git a/target/arm/internals.h b/target/arm/internals.h index 6be8b2d1a9..819de9037f 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -893,6 +893,19 @@ static inline bool regime_is_secure(CPUARMState *env, = ARMMMUIdx mmu_idx) } } =20 +static inline bool regime_is_pan(CPUARMState *env, ARMMMUIdx mmu_idx) +{ + switch (mmu_idx) { + case ARMMMUIdx_Stage1_E1_PAN: + case ARMMMUIdx_E10_1_PAN: + case ARMMMUIdx_E20_2_PAN: + case ARMMMUIdx_SE10_1_PAN: + return true; + default: + return false; + } +} + /* Return the FSR value for a debug exception (watchpoint, hardware * breakpoint or BKPT insn) targeting the specified exception level. */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 638abe6af0..18e4cbb63c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9578,6 +9578,9 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu= _idx, bool is_aa64, if (is_user) { prot_rw =3D user_rw; } else { + if (user_rw && regime_is_pan(env, mmu_idx)) { + return 0; + } prot_rw =3D simple_ap_to_rw_prot_is_user(ap, false); } =20 --=20 2.20.1 From nobody Thu Nov 13 12:02:47 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580605790961422.0835011175334; Sat, 1 Feb 2020 17:09:50 -0800 (PST) Received: from localhost ([::1]:52218 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iy3ll-0005Wc-Vj for importer@patchew.org; Sat, 01 Feb 2020 20:09:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45656) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iy3gz-0003hZ-IA for qemu-devel@nongnu.org; Sat, 01 Feb 2020 20:04:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iy3gy-00026a-AY for qemu-devel@nongnu.org; Sat, 01 Feb 2020 20:04:53 -0500 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:46034) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iy3gy-00025Q-42 for qemu-devel@nongnu.org; Sat, 01 Feb 2020 20:04:52 -0500 Received: by mail-pg1-x541.google.com with SMTP id b9so5712355pgk.12 for ; Sat, 01 Feb 2020 17:04:52 -0800 (PST) Received: from cloudburst.WiFi.IPv4InfoBelow (h210.212.133.40.static.ip.windstream.net. [40.133.212.210]) by smtp.gmail.com with ESMTPSA id 13sm14678975pfi.78.2020.02.01.17.04.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Feb 2020 17:04:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LdEIwR4tXW88OebyAe9sT02I9h4JxavRP0Kmc9yS4sc=; b=C9kv1ZVjKKQMfNYOlK7ZVqvZpsVvWdMPdcSlIAmOmf6jge2A/N0JbGqQ/8hKZrIJcq I0eXalnRgc1DgJT+aCyptQ4C29z+a8hqCxBy8gbtM7TyH7yLL4WZA0+zoo60qQEnwE9O i+OITKQRtmG3YESPPD+MSX/DUuWh+ySRjZfUgWLrv/SkSP/slqH3iJDAAXL3eUkEmq1k Rv9rjhSf1WzIC0EMNfxA74w8yOhYbI5Fq/HFo7oSaqQx3pJQ2/73/7n31HbWoXw4lWXn /5QKDq8+OTaMDpFrOA8M64cfWpJ8JvdUy7h52J6HAwoZKYWnNbabICKX7tu+opnR+dJN qxEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LdEIwR4tXW88OebyAe9sT02I9h4JxavRP0Kmc9yS4sc=; b=DR/dZKWn51ZyRJnOv/F47ZX+XdWpb3osP9lJl+nyX2eS0oJF4lYdjr0rnKcfb7Pd2O yw3jfvBTCKndb0hwqW6ZJAqjMS19JmDT1xfcCKBcpbv+1Daj6lyhqTgJ8/KBkLoX45NZ kTDPtdEkE7GStGyTipxH81JLvxKigvDFOGUkTbMGPb89/FAkVQlWhtr2T+YSkuokSA/0 IRrwR3z6RT+nJljj9j8dmAQfFsLtPZIPVO0vB0Q/qhkZ/hKy9CzAbvsUIiFk/DD/pCnJ 2ghvpXprLLI1Ved8qftwIbhHSNhu3nFgS3GPSUTnz1q6Ht679Ciilo6sfncpPyumrUU0 BjuA== X-Gm-Message-State: APjAAAU1Joo7rzN1+Mpd9BjbAreORc/9/iAidjN+ux+YxYDSYGlsgSBt lMQLdlHO3IAw+M3IMigDWgNBB/1vCFQ= X-Google-Smtp-Source: APXvYqwgI6kiGm5sSix1bEGS9PzDlRsUSSDsv2d3yQ1+OJpjRLej7ZiNLNLPkfFnNdRJ+xlWJTBGKg== X-Received: by 2002:a62:cece:: with SMTP id y197mr18383547pfg.9.1580605490891; Sat, 01 Feb 2020 17:04:50 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 08/14] target/arm: Set PAN bit as required on exception entry Date: Sat, 1 Feb 2020 17:04:33 -0800 Message-Id: <20200202010439.6410-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200202010439.6410-1-richard.henderson@linaro.org> References: <20200202010439.6410-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The PAN bit is preserved, or set as per SCTLR_ELx.SPAN, plus several other conditions listed in the ARM ARM. Signed-off-by: Richard Henderson --- v2: Tidy preservation of CPSR_PAN in take_aarch32_exception (pmm). --- target/arm/helper.c | 40 +++++++++++++++++++++++++++++++++++++--- 1 file changed, 37 insertions(+), 3 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 18e4cbb63c..4c0eb7e7d9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8772,8 +8772,12 @@ static void take_aarch32_exception(CPUARMState *env,= int new_mode, uint32_t mask, uint32_t offset, uint32_t newpc) { + int new_el; + /* Change the CPU state so as to actually take the exception. */ switch_mode(env, new_mode); + new_el =3D arm_current_el(env); + /* * For exceptions taken to AArch32 we must clear the SS bit in both * PSTATE and in the old-state value we save to SPSR_, so zero i= t now. @@ -8786,7 +8790,7 @@ static void take_aarch32_exception(CPUARMState *env, = int new_mode, env->uncached_cpsr =3D (env->uncached_cpsr & ~CPSR_M) | new_mode; /* Set new mode endianness */ env->uncached_cpsr &=3D ~CPSR_E; - if (env->cp15.sctlr_el[arm_current_el(env)] & SCTLR_EE) { + if (env->cp15.sctlr_el[new_el] & SCTLR_EE) { env->uncached_cpsr |=3D CPSR_E; } /* J and IL must always be cleared for exception entry */ @@ -8797,6 +8801,12 @@ static void take_aarch32_exception(CPUARMState *env,= int new_mode, env->thumb =3D (env->cp15.sctlr_el[2] & SCTLR_TE) !=3D 0; env->elr_el[2] =3D env->regs[15]; } else { + /* CPSR.PAN is preserved unless target is EL1 and SCTLR.SPAN =3D= =3D 0. */ + if (cpu_isar_feature(aa64_pan, env_archcpu(env)) + && new_el =3D=3D 1 + && !(env->cp15.sctlr_el[1] & SCTLR_SPAN)) { + env->uncached_cpsr |=3D CPSR_PAN; + } /* * this is a lie, as there was no c1_sys on V4T/V5, but who cares * and we should just guard the thumb mode on V4 @@ -9059,6 +9069,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) unsigned int new_el =3D env->exception.target_el; target_ulong addr =3D env->cp15.vbar_el[new_el]; unsigned int new_mode =3D aarch64_pstate_mode(new_el, true); + unsigned int old_mode; unsigned int cur_el =3D arm_current_el(env); =20 /* @@ -9138,20 +9149,43 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *= cs) } =20 if (is_a64(env)) { - env->banked_spsr[aarch64_banked_spsr_index(new_el)] =3D pstate_rea= d(env); + old_mode =3D pstate_read(env); aarch64_save_sp(env, arm_current_el(env)); env->elr_el[new_el] =3D env->pc; } else { - env->banked_spsr[aarch64_banked_spsr_index(new_el)] =3D cpsr_read(= env); + old_mode =3D cpsr_read(env); env->elr_el[new_el] =3D env->regs[15]; =20 aarch64_sync_32_to_64(env); =20 env->condexec_bits =3D 0; } + env->banked_spsr[aarch64_banked_spsr_index(new_el)] =3D old_mode; + qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n", env->elr_el[new_el]); =20 + if (cpu_isar_feature(aa64_pan, cpu)) { + /* The value of PSTATE.PAN is normally preserved, except when ... = */ + new_mode |=3D old_mode & PSTATE_PAN; + switch (new_el) { + case 2: + /* ... the target is EL2 with HCR_EL2.{E2H,TGE} =3D=3D '11' ..= . */ + if ((arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) + !=3D (HCR_E2H | HCR_TGE)) { + break; + } + /* fall through */ + case 1: + /* ... the target is EL1 ... */ + /* ... and SCTLR_ELx.SPAN =3D=3D 0, then set to 1. */ + if ((env->cp15.sctlr_el[new_el] & SCTLR_SPAN) =3D=3D 0) { + new_mode |=3D PSTATE_PAN; + } + break; + } + } + pstate_write(env, PSTATE_DAIF | new_mode); env->aarch64 =3D 1; aarch64_restore_sp(env, new_el); --=20 2.20.1 From nobody Thu Nov 13 12:02:47 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 158060579354099.56368897986408; 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[40.133.212.210]) by smtp.gmail.com with ESMTPSA id 13sm14678975pfi.78.2020.02.01.17.04.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Feb 2020 17:04:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ABlKw+Ee4niadP/JeYKLANZAwZirqXwkkASseIFrEXM=; b=PcHBbJ1RlfITAOyME7zPemx8OjVC2hcpfNOn+1Xk2qkG3u5+vFwVQ83sF7MVTgNsTE ulOvnpL3+FnOfjx4sSIjWVRLAyoz4rRANBKt6d8GCOaEDdVKZ+TNWgcIkswmk3kiNTP5 aVaoy/rHKarILH8ZuD2Yg1EctVn/zeHc3FLEu5Krjx9QklZ1pR8Onei/jTdrdetoTIOo GHIDDyhmLr4QFKkgFcuebECb7w6Hjs4LU0c4MP207Z39QH9NirvGrY5fdwtnO+Hdvcz0 /poePsnJt5RibP7Y4eJYfnae+HNHHbUW+7UjPsvPGH+bIRnu2+r8+IZ1tcdjiGKHINEz uSDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ABlKw+Ee4niadP/JeYKLANZAwZirqXwkkASseIFrEXM=; b=p5IeI5mJaAmdbQ4YQyzcEZxC3b0jtJfntGzut/TOYeFe5j5o3z4rKZzJ1xqLpDmyM5 vU1KAMSHcMx2AL5ZJ7ZwaWK0V1ZSByXcY9lGwPwWzLl8cHzXQgr36luPjcJqTCtwz7Yw PUUwDlLejGB7+oxuSjS4gvx/QSWiDVrsKD8M9CakHQEga0yzcjYCfPdjs1OhJnHbe2E9 hUleTEj0A1C2SLnXSe+JnRX4iIef1fMkRmeYcz7QbK05+4BEnQ0/qEA5u7mjsVEHT/ek RaOK3J6mLC0zMJdUsCBa06tBGxo/p19H7sWGvdkG+n3LjCKerVA9kUMP8obFVu4YL+aF WyBA== X-Gm-Message-State: APjAAAXpCWblGK0QZl4CMVqz8CRHQISeZoZ89LNEhtkCJQPjJKGyA3gf /k2aCG9QqFLfpb4Hhq8JqHi2neOcJyE= X-Google-Smtp-Source: APXvYqxFzNP2rJm3iGS5OjHLFsRYxn3kP8+FLNtIsoBpqvSQNZdgnEnQV9SD6k+yTgrt/E1kpXsKRA== X-Received: by 2002:a62:8e0a:: with SMTP id k10mr18270835pfe.49.1580605492196; Sat, 01 Feb 2020 17:04:52 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 09/14] target/arm: Implement ATS1E1 system registers Date: Sat, 1 Feb 2020 17:04:34 -0800 Message-Id: <20200202010439.6410-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200202010439.6410-1-richard.henderson@linaro.org> References: <20200202010439.6410-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" This is a minor enhancement over ARMv8.1-PAN. The *_PAN mmu_idx are used with the existing do_ats_write. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Move regdefs to file scope (pmm). --- target/arm/helper.c | 56 ++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 50 insertions(+), 6 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 4c0eb7e7d9..e69cde801f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3409,16 +3409,21 @@ static void ats_write(CPUARMState *env, const ARMCP= RegInfo *ri, uint64_t value) =20 switch (ri->opc2 & 6) { case 0: - /* stage 1 current state PL1: ATS1CPR, ATS1CPW */ + /* stage 1 current state PL1: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP= */ switch (el) { case 3: mmu_idx =3D ARMMMUIdx_SE3; break; case 2: - mmu_idx =3D ARMMMUIdx_Stage1_E1; - break; + g_assert(!secure); /* TODO: ARMv8.4-SecEL2 */ + /* fall through */ case 1: - mmu_idx =3D secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_Stage1_E1; + if (ri->crm =3D=3D 9 && (env->uncached_cpsr & CPSR_PAN)) { + mmu_idx =3D (secure ? ARMMMUIdx_SE10_1_PAN + : ARMMMUIdx_Stage1_E1_PAN); + } else { + mmu_idx =3D secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_Stage1_E= 1; + } break; default: g_assert_not_reached(); @@ -3487,8 +3492,13 @@ static void ats_write64(CPUARMState *env, const ARMC= PRegInfo *ri, switch (ri->opc2 & 6) { case 0: switch (ri->opc1) { - case 0: /* AT S1E1R, AT S1E1W */ - mmu_idx =3D secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_Stage1_E1; + case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */ + if (ri->crm =3D=3D 9 && (env->pstate & PSTATE_PAN)) { + mmu_idx =3D (secure ? ARMMMUIdx_SE10_1_PAN + : ARMMMUIdx_Stage1_E1_PAN); + } else { + mmu_idx =3D secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_Stage1_E= 1; + } break; case 4: /* AT S1E2R, AT S1E2W */ mmu_idx =3D ARMMMUIdx_E2; @@ -6692,6 +6702,32 @@ static const ARMCPRegInfo vhe_reginfo[] =3D { REGINFO_SENTINEL }; =20 +#ifndef CONFIG_USER_ONLY +static const ARMCPRegInfo ats1e1_reginfo[] =3D { + { .name =3D "AT_S1E1R", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 9, .opc2 =3D 0, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn =3D ats_write64 }, + { .name =3D "AT_S1E1W", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 9, .opc2 =3D 1, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn =3D ats_write64 }, + REGINFO_SENTINEL +}; + +static const ARMCPRegInfo ats1cp_reginfo[] =3D { + { .name =3D "ATS1CPRP", + .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 9, .opc2 =3D 0, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn =3D ats_write }, + { .name =3D "ATS1CPWP", + .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 9, .opc2 =3D 1, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn =3D ats_write }, + REGINFO_SENTINEL +}; +#endif + void register_cp_regs_for_features(ARMCPU *cpu) { /* Register all the coprocessor registers based on feature bits */ @@ -7629,6 +7665,14 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_pan, cpu)) { define_one_arm_cp_reg(cpu, &pan_reginfo); } +#ifndef CONFIG_USER_ONLY + if (cpu_isar_feature(aa64_ats1e1, cpu)) { + define_arm_cp_regs(cpu, ats1e1_reginfo); + } + if (cpu_isar_feature(aa32_ats1e1, cpu)) { + define_arm_cp_regs(cpu, ats1cp_reginfo); + } +#endif =20 if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu= )) { define_arm_cp_regs(cpu, vhe_reginfo); --=20 2.20.1 From nobody Thu Nov 13 12:02:47 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580605674458902.0113455876119; Sat, 1 Feb 2020 17:07:54 -0800 (PST) Received: from localhost ([::1]:52152 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iy3jt-0001Jf-BE for importer@patchew.org; Sat, 01 Feb 2020 20:07:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45686) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iy3h5-0003nq-IE for qemu-devel@nongnu.org; Sat, 01 Feb 2020 20:05:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iy3h0-0002AK-JQ for qemu-devel@nongnu.org; Sat, 01 Feb 2020 20:04:59 -0500 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:42884) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iy3h0-00029E-CN for qemu-devel@nongnu.org; Sat, 01 Feb 2020 20:04:54 -0500 Received: by mail-pg1-x541.google.com with SMTP id s64so5713299pgb.9 for ; Sat, 01 Feb 2020 17:04:54 -0800 (PST) Received: from cloudburst.WiFi.IPv4InfoBelow (h210.212.133.40.static.ip.windstream.net. [40.133.212.210]) by smtp.gmail.com with ESMTPSA id 13sm14678975pfi.78.2020.02.01.17.04.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Feb 2020 17:04:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pbTFZCO7ADOXNmgFtzr7ygDnLBWMHSNndfGhWIzZQwI=; b=kvJbbi/e/ah++Z8bA/jeiNK/zEI8r+LxCSD2L8Lxo5j+OSUFuisYSgMiVvBOZheMZ7 oRX4ZCxjIA3W0hknMWH+UXvHInePAb5qk6wMlhLsDks14BjDegd4kFg0dS+fBjcUgsyq MlyliUefO/Gv6xYraceKqStJs7n+n/rm/GlDlw1gU5QMas5ftWBtlAWIRJ0H2Ut/jwhx V9KG/90ff3HdZQVN/XdXmKZrxhugBolpqtDfxoeejDW7nYYb2b3mwTo5QmH0ZyOc/Bn9 EAGA2ZWy1o9gf5zmHZOsID1b/C0TsQmx8LhtShoILlvyaXx/AY3gaLfGTgzNXyW7E79E +RzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pbTFZCO7ADOXNmgFtzr7ygDnLBWMHSNndfGhWIzZQwI=; b=DJSdE6tcngm0rmpEnArvCZjjO4rau7t4rkZ7DJjxZcRYgTc0Q8wWpMR40/45ZB1pn7 0qGpgkydWu8L9EjK9erZgSeZ4+JvytRDoU4lz+5VnP8/tfrh38W5/JNW5Fyjke8PrOro YTSv7nbwyr7LJioqqGy/8iYP8oH9a9+0U6PjAXmwM2G7F/1kiGyPZp2NHfV9ycxZeA25 HYV+dX75/yPGPOkf7P84xeXUSyuqe0fgmTvXXgVtntWphIneOH8cU5XSGZhSfCwG/V8X QClot8toaEGRH68TctX0iSx3ilxuSO9I/F123mHYighyibm4+g1snW7G9iNuTDuMI1IV rUFA== X-Gm-Message-State: APjAAAWkteV/p9+lw/EBAFBctJhbMQs3RHng4mOBRdXZrGH0XOmAb4VY 6ydmYPLkRXsm8rgvncxxPbyfrYVO/cE= X-Google-Smtp-Source: APXvYqwebZoX+QwJCpH7ZyngcTQRhVgKKtEYExmKLVBaQzzRghWDIkODVpqGwVNcwvziY1cOs63OQw== X-Received: by 2002:a62:788a:: with SMTP id t132mr17931725pfc.134.1580605493230; Sat, 01 Feb 2020 17:04:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 10/14] target/arm: Enable ARMv8.2-ATS1E1 in -cpu max Date: Sat, 1 Feb 2020 17:04:35 -0800 Message-Id: <20200202010439.6410-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200202010439.6410-1-richard.henderson@linaro.org> References: <20200202010439.6410-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" This includes enablement of ARMv8.1-PAN. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.c | 4 ++++ target/arm/cpu64.c | 5 +++++ 2 files changed, 9 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index b0762a76c4..de733aceeb 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2709,6 +2709,10 @@ static void arm_max_initfn(Object *obj) t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ cpu->isar.mvfr2 =3D t; =20 + t =3D cpu->id_mmfr3; + t =3D FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ + cpu->id_mmfr3 =3D t; + t =3D cpu->id_mmfr4; t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ cpu->id_mmfr4 =3D t; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index c80fb5fd43..57fbc5eade 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -673,6 +673,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */ t =3D FIELD_DP64(t, ID_AA64MMFR1, LO, 1); t =3D FIELD_DP64(t, ID_AA64MMFR1, VH, 1); + t =3D FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */ cpu->isar.id_aa64mmfr1 =3D t; =20 /* Replicate the same data to the 32-bit id registers. */ @@ -693,6 +694,10 @@ static void aarch64_max_initfn(Object *obj) u =3D FIELD_DP32(u, ID_ISAR6, SPECRES, 1); cpu->isar.id_isar6 =3D u; =20 + u =3D cpu->id_mmfr3; + u =3D FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */ + cpu->id_mmfr3 =3D u; + /* * FIXME: We do not yet support ARMv8.2-fp16 for AArch32 yet, * so do not set MVFR1.FPHP. Strictly speaking this is not legal, --=20 2.20.1 From nobody Thu Nov 13 12:02:47 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580605648538185.12604927145333; Sat, 1 Feb 2020 17:07:28 -0800 (PST) Received: from localhost ([::1]:52148 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iy3jT-0000Ir-49 for importer@patchew.org; Sat, 01 Feb 2020 20:07:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45728) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iy3h7-0003s7-3q for qemu-devel@nongnu.org; Sat, 01 Feb 2020 20:05:02 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iy3h5-0002IX-P5 for qemu-devel@nongnu.org; Sat, 01 Feb 2020 20:05:00 -0500 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]:40301) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iy3h5-0002BY-IE for qemu-devel@nongnu.org; Sat, 01 Feb 2020 20:04:59 -0500 Received: by mail-pg1-x542.google.com with SMTP id k25so5732601pgt.7 for ; Sat, 01 Feb 2020 17:04:55 -0800 (PST) Received: from cloudburst.WiFi.IPv4InfoBelow (h210.212.133.40.static.ip.windstream.net. [40.133.212.210]) by smtp.gmail.com with ESMTPSA id 13sm14678975pfi.78.2020.02.01.17.04.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Feb 2020 17:04:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KjwTFN6CUEBdRUTSe2tL6jsQUXS+xcPxOv/fxUl6Yjg=; b=tLUVZZU3IiiE6c+5+O4zKdTjjhqk32qAsYhjCgSlU2qPJ4+SAtvDTcOUTA7gYMQdw/ JySPSXKxxi8OQY4RGzyDOxrD/IX8hzHhOIFYY+klJwrtqAcG0VXMjHHEaL+7M6Z1BiiD o6to0uWzasSzUItfAwLibSJL4G8k7E9ZASb7Gtx2X/2cV01GwWf9SrzmegM/KWsyHAai I6hXCoN04zFRv6yaIEu5ycEUEYEkB2ZdAz4FC2Tnh8plaJrsoNTSnZl/aKytptbbSJn+ ztLwjaLbecxXWoQcJv99d9d4bzw+UEYO9ybfCnsnZf0ovwfNcJvzAne8xW69YxZ28bv/ VfCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KjwTFN6CUEBdRUTSe2tL6jsQUXS+xcPxOv/fxUl6Yjg=; b=Ocq2JbLz6td/XrqnLI+lNNxBIwCMJ3d0IFxNhurYfeHdSoropDC0yJmbvWcK/Hh33x f1mybl8bZGCouNVzozWhW42F0eawE6ripBYASp/Gm33cs4FxF1BF6M+5QRnp64xlgl/3 8ErO2NveUU8WtOuO5TfhN9rksiTCWqPetNQq4Lap8oIXhciD6aS3WrfR4eRI1x+nGjML G+nSZMjSgA9PCkVfGINoVaht7FA7LaxCKDyCP83WQM1kt7aDAwM/RjzYL8JURJ5JEglb nH5CmiYlKdmdICwVqO8ifbzwZd1v/iyv0SBBfMRigjIpbwaf6psMnWQUKdlz2sqiP0er j0ZA== X-Gm-Message-State: APjAAAUHoPx3qpxv/V+tGP4dlgRB1YxkOtTMUAx8FjJDoEV7Lmxq1nYJ YYeIDbeq3UM34VpV6QGPE4GtsaaIX90= X-Google-Smtp-Source: APXvYqztXIAe2oOhow9VHUAT9LMCyXEx+MGAfUAOG1C5a+LVOpewkfs/E0xTo9gsIz5n2oTZHq4/5g== X-Received: by 2002:a63:4b24:: with SMTP id y36mr17665182pga.176.1580605494507; Sat, 01 Feb 2020 17:04:54 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 11/14] target/arm: Add ID_AA64MMFR2_EL1 Date: Sat, 1 Feb 2020 17:04:36 -0800 Message-Id: <20200202010439.6410-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200202010439.6410-1-richard.henderson@linaro.org> References: <20200202010439.6410-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Add definitions for all of the fields, up to ARMv8.5. Convert the existing RESERVED register to a full register. Query KVM for the value of the register for the host. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 17 +++++++++++++++++ target/arm/helper.c | 4 ++-- target/arm/kvm64.c | 2 ++ 3 files changed, 21 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b11fdc3001..a6a8f74be8 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -871,6 +871,7 @@ struct ARMCPU { uint64_t id_aa64pfr1; uint64_t id_aa64mmfr0; uint64_t id_aa64mmfr1; + uint64_t id_aa64mmfr2; } isar; uint32_t midr; uint32_t revidr; @@ -1816,6 +1817,22 @@ FIELD(ID_AA64MMFR1, PAN, 20, 4) FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) FIELD(ID_AA64MMFR1, XNX, 28, 4) =20 +FIELD(ID_AA64MMFR2, CNP, 0, 4) +FIELD(ID_AA64MMFR2, UAO, 4, 4) +FIELD(ID_AA64MMFR2, LSM, 8, 4) +FIELD(ID_AA64MMFR2, IESB, 12, 4) +FIELD(ID_AA64MMFR2, VARANGE, 16, 4) +FIELD(ID_AA64MMFR2, CCIDX, 20, 4) +FIELD(ID_AA64MMFR2, NV, 24, 4) +FIELD(ID_AA64MMFR2, ST, 28, 4) +FIELD(ID_AA64MMFR2, AT, 32, 4) +FIELD(ID_AA64MMFR2, IDS, 36, 4) +FIELD(ID_AA64MMFR2, FWB, 40, 4) +FIELD(ID_AA64MMFR2, TTL, 48, 4) +FIELD(ID_AA64MMFR2, BBM, 52, 4) +FIELD(ID_AA64MMFR2, EVT, 56, 4) +FIELD(ID_AA64MMFR2, E0PD, 60, 4) + FIELD(ID_DFR0, COPDBG, 0, 4) FIELD(ID_DFR0, COPSDBG, 4, 4) FIELD(ID_DFR0, MMAPDBG, 8, 4) diff --git a/target/arm/helper.c b/target/arm/helper.c index e69cde801f..a48f37dc05 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7082,11 +7082,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, .resetvalue =3D cpu->isar.id_aa64mmfr1 }, - { .name =3D "ID_AA64MMFR2_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, + { .name =3D "ID_AA64MMFR2_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 2, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D 0 }, + .resetvalue =3D cpu->isar.id_aa64mmfr2 }, { .name =3D "ID_AA64MMFR3_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 3, .access =3D PL1_R, .type =3D ARM_CP_CONST, diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index fb21ab9e73..3bae9e4a66 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -549,6 +549,8 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *= ahcf) ARM64_SYS_REG(3, 0, 0, 7, 0)); err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr1, ARM64_SYS_REG(3, 0, 0, 7, 1)); + err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr2, + ARM64_SYS_REG(3, 0, 0, 7, 2)); =20 /* * Note that if AArch32 support is not present in the host, --=20 2.20.1 From nobody Thu Nov 13 12:02:47 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580605906938735.178132491587; Sat, 1 Feb 2020 17:11:46 -0800 (PST) Received: from localhost ([::1]:52264 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iy3nd-0007zC-UV for importer@patchew.org; Sat, 01 Feb 2020 20:11:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45729) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iy3h7-0003sD-4z for qemu-devel@nongnu.org; Sat, 01 Feb 2020 20:05:02 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iy3h5-0002IR-P5 for qemu-devel@nongnu.org; Sat, 01 Feb 2020 20:05:01 -0500 Received: from mail-pf1-x442.google.com ([2607:f8b0:4864:20::442]:39161) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iy3h5-0002FD-IN for qemu-devel@nongnu.org; Sat, 01 Feb 2020 20:04:59 -0500 Received: by mail-pf1-x442.google.com with SMTP id 84so5526471pfy.6 for ; Sat, 01 Feb 2020 17:04:57 -0800 (PST) Received: from cloudburst.WiFi.IPv4InfoBelow (h210.212.133.40.static.ip.windstream.net. [40.133.212.210]) by smtp.gmail.com with ESMTPSA id 13sm14678975pfi.78.2020.02.01.17.04.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Feb 2020 17:04:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xC4Xxk2IMOJbSiLn0Ct8GHjNAdWvn3ZYodeP0ZE4BIc=; b=qJ0m8RND6J49V6WyTN9F8sOrTXj4Mn74tmtzVQzSKgVKJuVoKcGCk6RJKvgU1iU58Q yMMkKBsosYqs9/yD53n0zfxOreO3O/OUXCUTcAQn/WoqgU4/lJrpRYsrghGrug8OTJML JhRijioW+O9wIwI4bb9M3SNWMFe0/cgkzeiHSdRwsQN4SUT5giWD1pxp2FktkTvmsdo6 q9bj7URQKsD4c2KeCIQD4yAdCvfjoOatPHnBdQI7fKhCyKFINq9/RI5thu+bLT3x/+zf 9pibnRBdyjHiN6HNZrO2U/1kcoETjLMI2IBhUQBc79Wm+hpo/7AjOSE4m8ynzIIG/p95 xw5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xC4Xxk2IMOJbSiLn0Ct8GHjNAdWvn3ZYodeP0ZE4BIc=; b=XCz9eI4ijOOuucFePIKXe7WXWXyKTM/PpxmRbpMDYeWEMZNNSnuUAZNVGjDaaTv3m+ IBp8WFGaQ3ZTnQ3k1Avqc3XmzuvGyHqATeab6qHqyxfzM/9/TLMqUyv1a4tHHYT/udll 3bPDT+s5a/nRvpI24jyw9+4CJkAaHb+5nF/E/BZi+I5lbx0VKI/4j0z7gROCWpTrs/OQ BEH7QjL7OG2wiQWv5TzCaLTCpv9vy7D415Jr1+sj+fjH3UHOgexFlpKv/FwQNleU7INA EObs+eSWBZ7RmRNPBBXpcic9Lt8sFeYAazcloLj1wCAHXnzxPfnXQidegyHkzmc2BG8j oNQA== X-Gm-Message-State: APjAAAWGuQ7dQ578BWR5yiPeDcqo/BQ/W0KpbY5W4q+GMI7YHv0aj1dK qDAGePgMFSOFJYwl4aiCl5ZZU16VKPQ= X-Google-Smtp-Source: APXvYqzYu12ZsUV0LXflVGzHueHPlkO1WIICtLX/VZXNQ9bbQNuDKv+fMn5/WwuQmRt1AlRyq+XogA== X-Received: by 2002:a63:234f:: with SMTP id u15mr17836020pgm.88.1580605495952; Sat, 01 Feb 2020 17:04:55 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 12/14] target/arm: Update MSR access to UAO Date: Sat, 1 Feb 2020 17:04:37 -0800 Message-Id: <20200202010439.6410-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200202010439.6410-1-richard.henderson@linaro.org> References: <20200202010439.6410-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- v2: Move reginfo to file scope; avoid setting uao from spsr when the feature is not enabled (pmm). --- target/arm/cpu.h | 6 ++++++ target/arm/helper-a64.c | 3 +++ target/arm/helper.c | 21 +++++++++++++++++++++ target/arm/translate-a64.c | 14 ++++++++++++++ 4 files changed, 44 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a6a8f74be8..a0ac70e0fb 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1266,6 +1266,7 @@ void pmu_init(ARMCPU *cpu); #define PSTATE_IL (1U << 20) #define PSTATE_SS (1U << 21) #define PSTATE_PAN (1U << 22) +#define PSTATE_UAO (1U << 23) #define PSTATE_V (1U << 28) #define PSTATE_C (1U << 29) #define PSTATE_Z (1U << 30) @@ -3655,6 +3656,11 @@ static inline bool isar_feature_aa64_ats1e1(const AR= MISARegisters *id) return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >=3D 2; } =20 +static inline bool isar_feature_aa64_uao(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) !=3D 0; +} + static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) !=3D 0; diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 70d6407f80..9dda94644f 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -1037,6 +1037,9 @@ void HELPER(exception_return)(CPUARMState *env, uint6= 4_t new_pc) if (!cpu_isar_feature(aa64_pan, env_archcpu(env))) { spsr &=3D ~PSTATE_PAN; } + if (!cpu_isar_feature(aa64_uao, env_archcpu(env))) { + spsr &=3D ~PSTATE_UAO; + } pstate_write(env, spsr); if (!arm_singlestep_active(env)) { env->pstate &=3D ~PSTATE_SS; diff --git a/target/arm/helper.c b/target/arm/helper.c index a48f37dc05..d847b0f40b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4191,6 +4191,24 @@ static const ARMCPRegInfo pan_reginfo =3D { .readfn =3D aa64_pan_read, .writefn =3D aa64_pan_write }; =20 +static uint64_t aa64_uao_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->pstate & PSTATE_UAO; +} + +static void aa64_uao_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + env->pstate =3D (env->pstate & ~PSTATE_UAO) | (value & PSTATE_UAO); +} + +static const ARMCPRegInfo uao_reginfo =3D { + .name =3D "UAO", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 4, .crm =3D 2, .opc2 =3D 4, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_RW, + .readfn =3D aa64_uao_read, .writefn =3D aa64_uao_write +}; + static CPAccessResult aa64_cacheop_access(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) @@ -7673,6 +7691,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, ats1cp_reginfo); } #endif + if (cpu_isar_feature(aa64_uao, cpu)) { + define_one_arm_cp_reg(cpu, &uao_reginfo); + } =20 if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu= )) { define_arm_cp_regs(cpu, vhe_reginfo); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index d8ba240a15..7c26c3bfeb 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1602,6 +1602,20 @@ static void handle_msr_i(DisasContext *s, uint32_t i= nsn, s->base.is_jmp =3D DISAS_NEXT; break; =20 + case 0x03: /* UAO */ + if (!dc_isar_feature(aa64_uao, s) || s->current_el =3D=3D 0) { + goto do_unallocated; + } + if (crm & 1) { + set_pstate_bits(PSTATE_UAO); + } else { + clear_pstate_bits(PSTATE_UAO); + } + t1 =3D tcg_const_i32(s->current_el); + gen_helper_rebuild_hflags_a64(cpu_env, t1); + tcg_temp_free_i32(t1); + break; + case 0x04: /* PAN */ if (!dc_isar_feature(aa64_pan, s) || s->current_el =3D=3D 0) { goto do_unallocated; --=20 2.20.1 From nobody Thu Nov 13 12:02:47 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580605747345935.9713367072351; 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[40.133.212.210]) by smtp.gmail.com with ESMTPSA id 13sm14678975pfi.78.2020.02.01.17.04.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Feb 2020 17:04:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JSoxWa3cljnlHVlVCNXL6Dtt3Ft2EaSM4NkE+KvUy1o=; b=jMhuUb+8Iu0SZPfw/HYaoc8Iv7kFANTJKaDpqfvHl0ScGvxqcVtemXr9ef1s8WKQlI kkj9Bn1amg01jejKOGbemwkOwHQ2I5T4pOdmRoEKYKh3anJUHZmhra0HsMshyG6huHRK oNk+WfjwumlV61wCaLaPTdWGPQRfZ2kHpD68T8wkxTYe/NKd8i/cmCOW7/VLmWuW/ZQD p2j0vGq05xMrHwIE2PSAoLD+dYN1OSOTHUIOdw0KW+z1iPm+Ol3U7xFmfFLabpMBOYJE wjEhzQKtodrGCqnA0qAvhshEZ6Rht+nvlDY8YizsUaOsVEZwXQmFlD3iAH0Rh2P9MaHn hYAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JSoxWa3cljnlHVlVCNXL6Dtt3Ft2EaSM4NkE+KvUy1o=; b=As8RQF9AXIUzpfFgK++AUT17aPq9hHdpQc4idUsQeGG1xHIHLKdS4z1VFMs5LnHHDb i7DAI2ReBS51Jj0Wtugm5F14hzAltk6qOCPJF3MUPr9rxXJvOdxJriPz0Gg7haLplnhN EKSyq3pHRbZYjwWItDQWg7ktjtKV+dnFegir3u8WXjYdlBVrJZAPyul/fJeDz5kIhIu0 2t73ACqp/j5Jds13tshXSOUPABwZwrkUHl2nwM0ivNSABLNBvrgkuqMNhWqCcm+P7I1s qerL0GQOVEoWDl3e35l2/JOhaRsPyAYuuQ6uOS1Lce8QP9YQgyZZkg99GTaIvxtiVGiX +HNQ== X-Gm-Message-State: APjAAAX0oJ6FwR76gGdCTnZOh1dpwl9/IilnMKvL95t3LxcGFGDs06hg gXp0PvslixvnkJgSyKpZaOf/4Lp8Q4Q= X-Google-Smtp-Source: APXvYqw715xIgNml0iG/Vsma7M+y3BLsFCWoiN4JC6Fx5HXsV5N5GRGQET9qP/h+aL6vUPm6IYYzWw== X-Received: by 2002:aa7:961b:: with SMTP id q27mr17953413pfg.23.1580605497176; Sat, 01 Feb 2020 17:04:57 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 13/14] target/arm: Implement UAO semantics Date: Sat, 1 Feb 2020 17:04:38 -0800 Message-Id: <20200202010439.6410-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200202010439.6410-1-richard.henderson@linaro.org> References: <20200202010439.6410-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" We need only override the current condition under which TBFLAG_A64.UNPRIV is set. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 41 +++++++++++++++++++++-------------------- 1 file changed, 21 insertions(+), 20 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index d847b0f40b..b24a6a6526 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12194,28 +12194,29 @@ static uint32_t rebuild_hflags_a64(CPUARMState *e= nv, int el, int fp_el, } =20 /* Compute the condition for using AccType_UNPRIV for LDTR et al. */ - /* TODO: ARMv8.2-UAO */ - switch (mmu_idx) { - case ARMMMUIdx_E10_1: - case ARMMMUIdx_E10_1_PAN: - case ARMMMUIdx_SE10_1: - case ARMMMUIdx_SE10_1_PAN: - /* TODO: ARMv8.3-NV */ - flags =3D FIELD_DP32(flags, TBFLAG_A64, UNPRIV, 1); - break; - case ARMMMUIdx_E20_2: - case ARMMMUIdx_E20_2_PAN: - /* TODO: ARMv8.4-SecEL2 */ - /* - * Note that E20_2 is gated by HCR_EL2.E2H =3D=3D 1, but E20_0 is - * gated by HCR_EL2. =3D=3D '11', and so is LDTR. - */ - if (env->cp15.hcr_el2 & HCR_TGE) { + if (!(env->pstate & PSTATE_UAO)) { + switch (mmu_idx) { + case ARMMMUIdx_E10_1: + case ARMMMUIdx_E10_1_PAN: + case ARMMMUIdx_SE10_1: + case ARMMMUIdx_SE10_1_PAN: + /* TODO: ARMv8.3-NV */ flags =3D FIELD_DP32(flags, TBFLAG_A64, UNPRIV, 1); + break; + case ARMMMUIdx_E20_2: + case ARMMMUIdx_E20_2_PAN: + /* TODO: ARMv8.4-SecEL2 */ + /* + * Note that EL20_2 is gated by HCR_EL2.E2H =3D=3D 1, but EL20= _0 is + * gated by HCR_EL2. =3D=3D '11', and so is LDTR. + */ + if (env->cp15.hcr_el2 & HCR_TGE) { + flags =3D FIELD_DP32(flags, TBFLAG_A64, UNPRIV, 1); + } + break; + default: + break; } - break; - default: - break; } =20 return rebuild_hflags_common(env, fp_el, mmu_idx, flags); --=20 2.20.1 From nobody Thu Nov 13 12:02:47 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580605855200361.60637449220906; Sat, 1 Feb 2020 17:10:55 -0800 (PST) Received: from localhost ([::1]:52252 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iy3mo-0007AZ-5J for importer@patchew.org; Sat, 01 Feb 2020 20:10:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45723) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iy3h6-0003rh-Us for qemu-devel@nongnu.org; Sat, 01 Feb 2020 20:05:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iy3h5-0002Ie-SF for qemu-devel@nongnu.org; Sat, 01 Feb 2020 20:05:00 -0500 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]:33534) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iy3h5-0002HC-MJ for qemu-devel@nongnu.org; Sat, 01 Feb 2020 20:04:59 -0500 Received: by mail-pl1-x644.google.com with SMTP id ay11so4366513plb.0 for ; Sat, 01 Feb 2020 17:04:59 -0800 (PST) Received: from cloudburst.WiFi.IPv4InfoBelow (h210.212.133.40.static.ip.windstream.net. [40.133.212.210]) by smtp.gmail.com with ESMTPSA id 13sm14678975pfi.78.2020.02.01.17.04.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Feb 2020 17:04:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=n25wa1lNKzA3qMHXUq9DJlF06TNEvhgokWarr1Y211Q=; b=qJQTwYxARCZRy2tr365rmVLsk7PBL8w7RyM55/FVJyutM/vpW6hvX5iqgiAXWk5xab whX+Ok3xKf9rd2qp+Dik5/zzKNgKThOTz6hF7P92pK3RaBvOMfwdiaCZCG1A22m45Kg0 cSFlFOY6fITRR4WQBcqiMkRo/J2S49ZW4FzLnd+IYXixaG3Diqb91FyDECR69AVr9MG2 pVPMuSij+YdSwel0ktbbcXjnvAAE33RfvKsNAYEUfmKTtGCyuMFByNNkrWYoRHyDheCB Db0rp74ilO9HAz8hUjm4RJWiuhM9ammSJXER0aqpdx/0W51C+PiT92EVIynVcNeJxykk VlhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=n25wa1lNKzA3qMHXUq9DJlF06TNEvhgokWarr1Y211Q=; b=WoIC/9NxneGVKtDil5CtXCntH9KpJRYJd2jEFGkuEFhIICuWSAEDqrckNMN1Sy6+yR Zm8MFZUqJEDSEfrfMqg2DugnOnIeyHTbBesJmYGP/FtYLMB1ODjtLGwCMx8stEYgEN0d KGuIlgaaeOpHOYPD/ecydmBTrcFp0vEgRUrBX0/uGAu/rk6SmKS97PigxMgjpjtwEDbl 3Y7qCP9SCRiNixkJ4zEpBW5kaix8YTlQOoCFSHSZwxv8uJxC5enpOBJRru6AwzjX41Jo TBeZphMvKGKNUFHY++F49F9FxePqJvFRn35u9sT0Cq4xYPNYog4ivOXMMtiCxDIARx30 Z+Ug== X-Gm-Message-State: APjAAAXtLdKJU1efX7psxy7Y4zNMrt/OSInR6N0fyhDlbxF2nSQg36v5 Og9yGgccv68y7AXLhOwcHcS86f/JMUY= X-Google-Smtp-Source: APXvYqzQhJr1/9xmDfSHPIUA7+JHbSa2Zq4zBHYPgpLqxbgCb+opFu+eye76tJh9Sub25BNyYXdAAg== X-Received: by 2002:a17:902:7c87:: with SMTP id y7mr16881737pll.24.1580605498446; Sat, 01 Feb 2020 17:04:58 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 14/14] target/arm: Enable ARMv8.2-UAO in -cpu max Date: Sat, 1 Feb 2020 17:04:39 -0800 Message-Id: <20200202010439.6410-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200202010439.6410-1-richard.henderson@linaro.org> References: <20200202010439.6410-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu64.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 57fbc5eade..1359564c55 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -676,6 +676,10 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */ cpu->isar.id_aa64mmfr1 =3D t; =20 + t =3D cpu->isar.id_aa64mmfr2; + t =3D FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); + cpu->isar.id_aa64mmfr2 =3D t; + /* Replicate the same data to the 32-bit id registers. */ u =3D cpu->isar.id_isar5; u =3D FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */ --=20 2.20.1