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X-Received-From: 2607:f8b0:4864:20::541 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- target/arm/cpu.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 608fcbd0b7..2a53f5d09b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3685,6 +3685,11 @@ static inline bool isar_feature_aa64_sve(const ARMIS= ARegisters *id) return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) !=3D 0; } =20 +static inline bool isar_feature_aa64_vh(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) !=3D 0; +} + static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) !=3D 0; --=20 2.20.1 From nobody Mon Feb 9 12:19:52 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580585446768884.3251796418782; Sat, 1 Feb 2020 11:30:46 -0800 (PST) Received: from localhost ([::1]:49240 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixyTd-0000Cn-Ah for importer@patchew.org; Sat, 01 Feb 2020 14:30:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58526) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixySI-0006z7-Ro for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ixySH-0006PG-PR for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:22 -0500 Received: from mail-pl1-x643.google.com ([2607:f8b0:4864:20::643]:38704) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ixySH-0006Ob-Js for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:21 -0500 Received: by mail-pl1-x643.google.com with SMTP id t6so4179475plj.5 for ; Sat, 01 Feb 2020 11:29:21 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id l7sm3668509pga.27.2020.02.01.11.29.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Feb 2020 11:29:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=oFV70oqbuZ/Iy95AzfvjMyE40zNVPl8rlhZhKbOLyGc=; b=KVqusxt925s5xNMtWuBNbTLVSFlutSBAabOba8Xe8V0Jz4eRdkxjxCxFnzAdASqprw j8mW2kj4YNj2rJINMNjECS6CQdTukkGnZmcyjYYu/vmVKeaEodoisfrs7mKV20zveS3a nq2ikw/Ro6b5XzjsDseoGF2TZTojLWONKNhYZnfTQyOVD2LZV5ejFiyEn7oIJUwAJub2 XZdrV0dAvwY/igu7n6RRkU+FYN46HzcAdynf7tV/W5dO/bbZqjhepanUyGbI5/WfxO6P tEdSZHdyMBakYRGOZQYM7pu/osl+hGcfSk7rPBFvhbi58628eA+zK2v9T5Bv6rir3uLT w+6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oFV70oqbuZ/Iy95AzfvjMyE40zNVPl8rlhZhKbOLyGc=; b=o2CIP8PFV64fKSK76mXYo2gnld3i+dnKK0cikjeuoWPFhk7v7Thy5FGW9CxWRBiGxh DKLKD/8fManTx1NGYMQDP8OwgT/q3+mOtL3jXa8RzcMh2BIFJMle+nLWRReRVXEdWSgE 1RMf+2sVV+JO9Daz8E8d6O3i9bjKHpfSyiOQrD3KIaJ7sRtoXjizIn2dctWSPXuC3uRZ /ibJqDhiuOWV+yh/8XH+nHG2Py4cQGQ1mNeS/rQHbbowk3xfirrNWyLxh4i0nPt5dmsd W7me6Un3sujqL8Zx6XmBTm0rRCpJFqRVO+JYDNICGLf38ft/DLQ1JZW1y4hPzUBUwrdN fgAQ== X-Gm-Message-State: APjAAAWN2fFEC7iGYu1MP9Y/5EDGvtlyhrXeLsy517PISDqgO2eromQ4 dwHBkiSaRK3VUteNox+2Y0+Aoz3Y3lw= X-Google-Smtp-Source: APXvYqzUtk9y8n1yj/y4sM5bC955jHFlNU1yovEKYK8CTfE3oGc2uPsyNwsb+84HWp8yxrb0Zib9oQ== X-Received: by 2002:a17:902:8a8e:: with SMTP id p14mr16190961plo.28.1580585360262; Sat, 01 Feb 2020 11:29:20 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 02/41] target/arm: Enable HCR_E2H for VHE Date: Sat, 1 Feb 2020 11:28:37 -0800 Message-Id: <20200201192916.31796-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200201192916.31796-1-richard.henderson@linaro.org> References: <20200201192916.31796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- target/arm/cpu.h | 7 ------- target/arm/helper.c | 6 +++++- 2 files changed, 5 insertions(+), 8 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 2a53f5d09b..0e68704a90 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1424,13 +1424,6 @@ static inline void xpsr_write(CPUARMState *env, uint= 32_t val, uint32_t mask) #define HCR_ATA (1ULL << 56) #define HCR_DCT (1ULL << 57) =20 -/* - * When we actually implement ARMv8.1-VHE we should add HCR_E2H to - * HCR_MASK and then clear it again if the feature bit is not set in - * hcr_write(). - */ -#define HCR_MASK ((1ULL << 34) - 1) - #define SCR_NS (1U << 0) #define SCR_IRQ (1U << 1) #define SCR_FIQ (1U << 2) diff --git a/target/arm/helper.c b/target/arm/helper.c index 19a57a17da..f5ce05fdf3 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4721,7 +4721,8 @@ static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = =3D { static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= alue) { ARMCPU *cpu =3D env_archcpu(env); - uint64_t valid_mask =3D HCR_MASK; + /* Begin with bits defined in base ARMv8.0. */ + uint64_t valid_mask =3D MAKE_64BIT_MASK(0, 34); =20 if (arm_feature(env, ARM_FEATURE_EL3)) { valid_mask &=3D ~HCR_HCD; @@ -4735,6 +4736,9 @@ static void hcr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) */ valid_mask &=3D ~HCR_TSC; } + if (cpu_isar_feature(aa64_vh, cpu)) { + valid_mask |=3D HCR_E2H; + } if (cpu_isar_feature(aa64_lor, cpu)) { valid_mask |=3D HCR_TLOR; } --=20 2.20.1 From nobody Mon Feb 9 12:19:52 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580585748853522.87876801424; Sat, 1 Feb 2020 11:35:48 -0800 (PST) Received: from localhost ([::1]:49338 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixyYV-00074K-Pk for importer@patchew.org; Sat, 01 Feb 2020 14:35:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58538) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixySK-0006zq-5N for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:25 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ixySI-0006Q5-TJ for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:24 -0500 Received: from mail-pf1-x443.google.com ([2607:f8b0:4864:20::443]:32980) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ixySI-0006Pc-NH for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:22 -0500 Received: by mail-pf1-x443.google.com with SMTP id n7so5290455pfn.0 for ; Sat, 01 Feb 2020 11:29:22 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id l7sm3668509pga.27.2020.02.01.11.29.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Feb 2020 11:29:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QDSFHnHYdNMk1UthAHV8+Um/pzdBXbq/7AhRW+XbQEk=; b=nzU9ZySdlneXPb/EmJv24bsdhrNUTdzjUwo8rip9ll4jiAfBrj5Q/hLWEVnrr+4hKd 0s+ChScOHBVJH79XlJdCLBr+eVapJE5gsNRxgxbWBvoR7WhK2IHDmZPcFliBgxTZZtoO IoR38GUk6nPPwIvABikenaTQvwxWcktqnF1dv0AtKVnO3iWlkIslIIiBvzcu0xhR8fw1 8gB6Xsmk+d1K/G/rfcNmCkvnSS89RJ20i+6mLSD43DhmvYhJzoDyPfn0jtK3dxnUoOYc I7a+zXQv3J7Ovf1jCVAxAIHq31E892v7crQpkQ8Nden0PxtER95KwX0rlEpumv8SSHBX P1yQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QDSFHnHYdNMk1UthAHV8+Um/pzdBXbq/7AhRW+XbQEk=; b=e3hjpDdL0AJ+xSHbPisMgNgs8pAKh59LKiQurF2JjTFF/dhkfgFzBzKK/BbmUiQlfk t+PODMuZ+27xBTAS1jfXGGMBBjVDJhXC4hq8rcmd9uK+efb/RTe6qtcFD9kBVm90mnMe xegCdFNIEpLrQbV57UOZ46Gogh0c5NlBKel4PDz4sL9WvaW/ojsB1ag9I8t68/JS7jHr TLNGskVu//G4Fp4swz5g+IFhGNzKmAmyDNyClimrrqsNoJxwuBrKorgIPhNS3+qUjNks U71yERCdMOpWwlkRRA3E/zFg14MglfqQgHDnpGe4XAtGtYPBAtuQjfqDW5YP/bbzOfOP /rXg== X-Gm-Message-State: APjAAAUfksc5iyNyzmMyr6DMKwClf5dJgFqb5ulHQU7OMtv7I7Z3FcvS w0MaJ6+evlrkK94vpPWswpzJO9/t38Y= X-Google-Smtp-Source: APXvYqyA/W15TV1mfgSmkzwep+WA/7d+Ke3faDyoeg2O/erPw5c6hpSxClJ5vBVFB/A1ukzSjz+arw== X-Received: by 2002:aa7:9145:: with SMTP id 5mr16861193pfi.74.1580585361384; Sat, 01 Feb 2020 11:29:21 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 03/41] target/arm: Add CONTEXTIDR_EL2 Date: Sat, 1 Feb 2020 11:28:38 -0800 Message-Id: <20200201192916.31796-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200201192916.31796-1-richard.henderson@linaro.org> References: <20200201192916.31796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Not all of the breakpoint types are supported, but those that only examine contextidr are extended to support the new register. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- v6: Move reginfo to file scope. --- target/arm/debug_helper.c | 50 +++++++++++++++++++++++++++++---------- target/arm/helper.c | 12 ++++++++++ 2 files changed, 50 insertions(+), 12 deletions(-) diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index dde80273ff..2e3e90c6a5 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -20,6 +20,7 @@ static bool linked_bp_matches(ARMCPU *cpu, int lbn) int ctx_cmps =3D extract32(cpu->dbgdidr, 20, 4); int bt; uint32_t contextidr; + uint64_t hcr_el2; =20 /* * Links to unimplemented or non-context aware breakpoints are @@ -40,24 +41,44 @@ static bool linked_bp_matches(ARMCPU *cpu, int lbn) } =20 bt =3D extract64(bcr, 20, 4); - - /* - * We match the whole register even if this is AArch32 using the - * short descriptor format (in which case it holds both PROCID and ASI= D), - * since we don't implement the optional v7 context ID masking. - */ - contextidr =3D extract64(env->cp15.contextidr_el[1], 0, 32); + hcr_el2 =3D arm_hcr_el2_eff(env); =20 switch (bt) { case 3: /* linked context ID match */ - if (arm_current_el(env) > 1) { - /* Context matches never fire in EL2 or (AArch64) EL3 */ + switch (arm_current_el(env)) { + default: + /* Context matches never fire in AArch64 EL3 */ return false; + case 2: + if (!(hcr_el2 & HCR_E2H)) { + /* Context matches never fire in EL2 without E2H enabled. = */ + return false; + } + contextidr =3D env->cp15.contextidr_el[2]; + break; + case 1: + contextidr =3D env->cp15.contextidr_el[1]; + break; + case 0: + if ((hcr_el2 & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)= ) { + contextidr =3D env->cp15.contextidr_el[2]; + } else { + contextidr =3D env->cp15.contextidr_el[1]; + } + break; } - return (contextidr =3D=3D extract64(env->cp15.dbgbvr[lbn], 0, 32)); - case 5: /* linked address mismatch (reserved in AArch64) */ + break; + + case 7: /* linked contextidr_el1 match */ + contextidr =3D env->cp15.contextidr_el[1]; + break; + case 13: /* linked contextidr_el2 match */ + contextidr =3D env->cp15.contextidr_el[2]; + break; + case 9: /* linked VMID match (reserved if no EL2) */ case 11: /* linked context ID and VMID match (reserved if no EL2) */ + case 15: /* linked full context ID match */ default: /* * Links to Unlinked context breakpoints must generate no @@ -66,7 +87,12 @@ static bool linked_bp_matches(ARMCPU *cpu, int lbn) return false; } =20 - return false; + /* + * We match the whole register even if this is AArch32 using the + * short descriptor format (in which case it holds both PROCID and ASI= D), + * since we don't implement the optional v7 context ID masking. + */ + return contextidr =3D=3D (uint32_t)env->cp15.dbgbvr[lbn]; } =20 static bool bp_wp_matches(ARMCPU *cpu, int n, bool is_wp) diff --git a/target/arm/helper.c b/target/arm/helper.c index f5ce05fdf3..fe7991864a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6126,6 +6126,14 @@ static const ARMCPRegInfo jazelle_regs[] =3D { REGINFO_SENTINEL }; =20 +static const ARMCPRegInfo vhe_reginfo[] =3D { + { .name =3D "CONTEXTIDR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 13, .crm =3D 0, .opc2 =3D 1, + .access =3D PL2_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.contextidr_el[2]) }, + REGINFO_SENTINEL +}; + void register_cp_regs_for_features(ARMCPU *cpu) { /* Register all the coprocessor registers based on feature bits */ @@ -7089,6 +7097,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, lor_reginfo); } =20 + if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu= )) { + define_arm_cp_regs(cpu, vhe_reginfo); + } + if (cpu_isar_feature(aa64_sve, cpu)) { define_one_arm_cp_reg(cpu, &zcr_el1_reginfo); if (arm_feature(env, ARM_FEATURE_EL2)) { --=20 2.20.1 From nobody Mon Feb 9 12:19:52 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580585635168358.0746083417441; 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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id l7sm3668509pga.27.2020.02.01.11.29.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Feb 2020 11:29:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NRIyxc7vWfkpiQTZE4LZxFudoV8Un+UW9c4R2EG99Mo=; b=RdrCtHqhyXLoNV8lhd1fezwRgu+MSYzV606AGW1HhpxIx1kqTBXs+EDCXWc0FnDeFl YdG5cFnjPJnWLpHTQH5Q6BOphZbkWGyv8dJoumgORbRnPSXZkkpnGk3UukiU0asM1NN7 OhQZgvytEfu9E+dJ1p3JBlF8vZhQhqOKiQyBCdif7RWe5e5S2yOmW13/MDppNI/YCedP gH/2m5WmtDPjvDlOZnkG7UJ/qfJRtwvNf8rxCBlJ8bTYDNmdZc5yVWwGhJBGjYne59S8 0kcdc4ly2p0Ei3WoFRntc+GwwsXMirMlgTb5TgqNkfaCpftFTWppEsjSY9i4OGlvsvCj vN/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NRIyxc7vWfkpiQTZE4LZxFudoV8Un+UW9c4R2EG99Mo=; b=Y8wtJH80m6h9oFgX5ZlWUPMQ5Qa0DhSH7lT8CEItscOr+jH9V2VXDavr7S4X7tY27W 0Kc1VWy/hAxYcN7AxZS4mo4gEEc+F34bwN+HaYI1N9NSeEoLdPYf+nN9mbu7DJaO4I9p LLk6HZEWK3MgELN2RgsrLjKaS5qXNcBVF9Wq4ohTswVrzMtqCMBc4Cl1iwsQtyAAaKyk EnSi5D+54FhA2YtZdYConMKAy68EtqsJdWPpaKLrG+an1b/NZsq2O0xTzrJQDWfKfL0y 8luNBifvqWZmVFlQZbfpOrIRdnRKTzQJCFfiy+RR74NUf8Q2/90WTD58hP+sCSKDVS1O ikSw== X-Gm-Message-State: APjAAAVmd3lXszAlga5dkSmku9bseL+VpsmtfA1ri5cKeJVJ0UPsKdAE 1mqMvW75J6XLT6/fQDb85Gcm+jISEBY= X-Google-Smtp-Source: APXvYqye7hjN7Wf7OPUC93WbL5ZeNC2MSQPvbEd/jWp3CFkyXIfCa6rrwXKejoGsO0ymftPCNRcOyQ== X-Received: by 2002:aa7:8502:: with SMTP id v2mr16165481pfn.232.1580585362568; Sat, 01 Feb 2020 11:29:22 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 04/41] target/arm: Add TTBR1_EL2 Date: Sat, 1 Feb 2020 11:28:39 -0800 Message-Id: <20200201192916.31796-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200201192916.31796-1-richard.henderson@linaro.org> References: <20200201192916.31796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) At the same time, add writefn to TTBR0_EL2 and TCR_EL2. A later patch will update any ASID therein. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- v5: Do not update TCR_EL2 yet; delay that til we handle ASIDs. --- target/arm/helper.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index fe7991864a..c7ee0d603f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3533,6 +3533,13 @@ static void vmsa_ttbr_write(CPUARMState *env, const = ARMCPRegInfo *ri, raw_write(env, ri, value); } =20 +static void vmsa_tcr_ttbr_el2_write(CPUARMState *env, const ARMCPRegInfo *= ri, + uint64_t value) +{ + /* TODO: There are ASID fields in here with HCR_EL2.E2H */ + raw_write(env, ri, value); +} + static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -4979,7 +4986,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.tpidr_el[2]) }, { .name =3D "TTBR0_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 0, - .access =3D PL2_RW, .resetvalue =3D 0, + .access =3D PL2_RW, .resetvalue =3D 0, .writefn =3D vmsa_tcr_ttbr_el= 2_write, .fieldoffset =3D offsetof(CPUARMState, cp15.ttbr0_el[2]) }, { .name =3D "HTTBR", .cp =3D 15, .opc1 =3D 4, .crm =3D 2, .access =3D PL2_RW, .type =3D ARM_CP_64BIT | ARM_CP_ALIAS, @@ -6131,6 +6138,10 @@ static const ARMCPRegInfo vhe_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 4, .crn =3D 13, .crm =3D 0, .opc2 =3D 1, .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.contextidr_el[2]) }, + { .name =3D "TTBR1_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 1, + .access =3D PL2_RW, .writefn =3D vmsa_tcr_ttbr_el2_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.ttbr1_el[2]) }, REGINFO_SENTINEL }; =20 --=20 2.20.1 From nobody Mon Feb 9 12:19:52 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580585461986146.65798591465705; Sat, 1 Feb 2020 11:31:01 -0800 (PST) Received: from localhost ([::1]:49244 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixyTs-0000U3-83 for importer@patchew.org; Sat, 01 Feb 2020 14:31:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58564) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixySM-00073W-FQ for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:27 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ixySL-0006Rj-CM for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:26 -0500 Received: from mail-pj1-x1041.google.com ([2607:f8b0:4864:20::1041]:50477) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ixySL-0006RH-6X for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:25 -0500 Received: by mail-pj1-x1041.google.com with SMTP id r67so4474282pjb.0 for ; Sat, 01 Feb 2020 11:29:25 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id l7sm3668509pga.27.2020.02.01.11.29.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Feb 2020 11:29:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=H1scrHoRFHkW8V/qxPSJeuSDB15CpU5xa7Qviebbre4=; b=ee2CS1UHNBC+W3OSWJyMlRrSmG/GlP6pp0vgOnBrIFgNFnsZa9GIsRFkPQeZQGGxaM /JF3b0YpdViTZ1GZo2nl0NbOq5sfbteu7K2XB55LNYgKdPrKvxx30+/skOkhjw64Ht6H Lr/V/qJnqaYK4CVUydfVzpX0E+ju2a4jXLJkHZgtP3P23RsNBC8bwAShZj2iP1+DwxhG iRYMPjAWUhunx01lQEOF/tIgtY/3p4iNE6yjr9WJeaRYW897d9VHySMGtU1h1wcaW/G+ Cje5OJzGY3jSUGy/ef4zdRZDlrVuyleCZm65wNTkESq6OGaKWkF9eiyCHH9HJN01gvMi 36TA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=H1scrHoRFHkW8V/qxPSJeuSDB15CpU5xa7Qviebbre4=; b=Y0TE7/UrZ5u1fr/xcZWRzeRojg31NE99cnyxeEB7jv7gHaSBTh2Nsr/sg5ZZdRDJ8q wfxRDYD+jELtWK+JJReYTUUlw+UjXw6N6PVLYJ2iG4PiFaT8UY3pKUJmd/s+TXxD65kw 6FmQcq6aONdrRWH8WQkpPbotjaz+rRiJuYSJFEg4JwURfQG8bwPwFB23zmqP+HCCIrt4 06TIzn7dJidrhtLxk0hcupQgUSpdIfWb2Cvk7g18Sn1zKa59EqOKuBN9/JASfCqbVbJ2 mnWjvbEQpw3s+KnhBP6iaO+SEUWXl5/kKGuzH0+lx/NoTr2oPLuD0io4loW1NAf8V3E1 D0MA== X-Gm-Message-State: APjAAAVo2LTTby/T+krNNoU8lJH/VVabxEs5cNNrJmFEfoqFZKj6teBx lEMDEIyzUsKhna0bIOsSp2H4fuXNF6U= X-Google-Smtp-Source: APXvYqzYpd0NU1Ep7XtXp/s/I69rIXM7/Ws1l/iIdxCo109qvBOWuhcIw/81AWPYMrUdh6lFSD1Q7Q== X-Received: by 2002:a17:90a:2223:: with SMTP id c32mr20883169pje.15.1580585363794; Sat, 01 Feb 2020 11:29:23 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 05/41] target/arm: Update CNTVCT_EL0 for VHE Date: Sat, 1 Feb 2020 11:28:40 -0800 Message-Id: <20200201192916.31796-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200201192916.31796-1-richard.henderson@linaro.org> References: <20200201192916.31796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1041 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) The virtual offset may be 0 depending on EL, E2H and TGE. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- target/arm/helper.c | 40 +++++++++++++++++++++++++++++++++++++--- 1 file changed, 37 insertions(+), 3 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index c7ee0d603f..dbfdf2324b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2515,9 +2515,31 @@ static uint64_t gt_cnt_read(CPUARMState *env, const = ARMCPRegInfo *ri) return gt_get_countervalue(env); } =20 +static uint64_t gt_virt_cnt_offset(CPUARMState *env) +{ + uint64_t hcr; + + switch (arm_current_el(env)) { + case 2: + hcr =3D arm_hcr_el2_eff(env); + if (hcr & HCR_E2H) { + return 0; + } + break; + case 0: + hcr =3D arm_hcr_el2_eff(env); + if ((hcr & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)) { + return 0; + } + break; + } + + return env->cp15.cntvoff_el2; +} + static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) { - return gt_get_countervalue(env) - env->cp15.cntvoff_el2; + return gt_get_countervalue(env) - gt_virt_cnt_offset(env); } =20 static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -2532,7 +2554,13 @@ static void gt_cval_write(CPUARMState *env, const AR= MCPRegInfo *ri, static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri, int timeridx) { - uint64_t offset =3D timeridx =3D=3D GTIMER_VIRT ? env->cp15.cntvoff_el= 2 : 0; + uint64_t offset =3D 0; + + switch (timeridx) { + case GTIMER_VIRT: + offset =3D gt_virt_cnt_offset(env); + break; + } =20 return (uint32_t)(env->cp15.c14_timer[timeridx].cval - (gt_get_countervalue(env) - offset)); @@ -2542,7 +2570,13 @@ static void gt_tval_write(CPUARMState *env, const AR= MCPRegInfo *ri, int timeridx, uint64_t value) { - uint64_t offset =3D timeridx =3D=3D GTIMER_VIRT ? env->cp15.cntvoff_el= 2 : 0; + uint64_t offset =3D 0; + + switch (timeridx) { + case GTIMER_VIRT: + offset =3D gt_virt_cnt_offset(env); + break; + } =20 trace_arm_gt_tval_write(timeridx, value); env->cp15.c14_timer[timeridx].cval =3D gt_get_countervalue(env) - offs= et + --=20 2.20.1 From nobody Mon Feb 9 12:19:52 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580585748920979.7168841954266; Sat, 1 Feb 2020 11:35:48 -0800 (PST) Received: from localhost ([::1]:49342 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixyYV-00074h-G5 for importer@patchew.org; Sat, 01 Feb 2020 14:35:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58573) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixySN-00075J-DF for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:28 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ixySM-0006TB-DB for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:27 -0500 Received: from mail-pj1-x1042.google.com ([2607:f8b0:4864:20::1042]:56270) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ixySM-0006Rx-7b for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:26 -0500 Received: by mail-pj1-x1042.google.com with SMTP id d5so4462698pjz.5 for ; Sat, 01 Feb 2020 11:29:26 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id l7sm3668509pga.27.2020.02.01.11.29.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Feb 2020 11:29:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rwV4ZNAYmUhb3kMWrkN08M3nDN8bK4HgsQpKFnhrwoc=; b=wW/zK8OVMUMtda4NULAhEDzzWPnwaZPhxm+z8HDOwOuin10C1NGqOl2ZbD6A+f1ZFb VaW3OyynAaoZ1/RNEctsKG/0cEqQtkD1tu86i8I2pdg9NFxEsBmQFzOL/n3Sm1+is6a8 IVd2+4UXoVURfgUTtFORSJf4utiEgYflIkqGYdNLVDFpfCMGqZmzYMAxJ4z2XGiQSdoH fWhZMmbRABE+UJaso74hJCiLZVp+keUqfJTztV9qXDP4jJw8JWnds+Qq0wBR2fD8i87d xfFPNA5vh7seALhteTPYCvma3f5DllVUuCcF+jR9mqkzT3Akm6DqN3VBFBpH8Op6u90d SQhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rwV4ZNAYmUhb3kMWrkN08M3nDN8bK4HgsQpKFnhrwoc=; b=OjxutocFxA2yXa9FZw3daMVXFOTn5VfLFVK29iYqYLPD7geowb21SvsSn0PZ8/ruPk dCa20DN9g1QSu2bMBONONR8qEviuVbtDb0ntqL29PaDGI943+lVopgTKSrZp/cdU9JTt whKdRq+BHGMFqEZKJa6iqEgNXyfn7wabud9viIBZPZmCWPTKKa8sZjK9aI+7fsmFyxAM 28ZmaJtFcwWSopU6Xzhc99JRNPFpgmPrUIqCVlCk/Nxo/ypw/SYjQsn+OWGODVO529BJ i0ar+StoryL2zNE8ABdEC+UKUJe2VMuMX4tfULkWVLecvXOtCsif13kxWIXNPs45FAgT q0HA== X-Gm-Message-State: APjAAAUEcZxTjVQPJR7pqSE5IUM9dVLf//BcmxZ7ELIUyvNHqMIJYAqb 9DItXiQ2BLYMDt/APaAqXodWaciYRnA= X-Google-Smtp-Source: APXvYqz1paFPS8A+Pvv7qgRglu2dv5La2/nYhbCgV9y/jQzIVuPTUZnUIDABGkcTMVOarIo5llhiFg== X-Received: by 2002:a17:90a:af81:: with SMTP id w1mr20467865pjq.14.1580585364892; Sat, 01 Feb 2020 11:29:24 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 06/41] target/arm: Split out vae1_tlbmask Date: Sat, 1 Feb 2020 11:28:41 -0800 Message-Id: <20200201192916.31796-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200201192916.31796-1-richard.henderson@linaro.org> References: <20200201192916.31796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1042 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) No functional change, but unify code sequences. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- target/arm/helper.c | 32 +++++++++++++------------------- 1 file changed, 13 insertions(+), 19 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index dbfdf2324b..8b3bb51dee 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3940,42 +3940,36 @@ static CPAccessResult aa64_cacheop_access(CPUARMSta= te *env, * Page D4-1736 (DDI0487A.b) */ =20 +static int vae1_tlbmask(CPUARMState *env) +{ + if (arm_is_secure_below_el3(env)) { + return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0; + } else { + return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0; + } +} + static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo= *ri, uint64_t value) { CPUState *cs =3D env_cpu(env); - bool sec =3D arm_is_secure_below_el3(env); + int mask =3D vae1_tlbmask(env); =20 - if (sec) { - tlb_flush_by_mmuidx_all_cpus_synced(cs, - ARMMMUIdxBit_S1SE1 | - ARMMMUIdxBit_S1SE0); - } else { - tlb_flush_by_mmuidx_all_cpus_synced(cs, - ARMMMUIdxBit_S12NSE1 | - ARMMMUIdxBit_S12NSE0); - } + tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); } =20 static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *= ri, uint64_t value) { CPUState *cs =3D env_cpu(env); + int mask =3D vae1_tlbmask(env); =20 if (tlb_force_broadcast(env)) { tlbi_aa64_vmalle1is_write(env, NULL, value); return; } =20 - if (arm_is_secure_below_el3(env)) { - tlb_flush_by_mmuidx(cs, - ARMMMUIdxBit_S1SE1 | - ARMMMUIdxBit_S1SE0); - } else { - tlb_flush_by_mmuidx(cs, - ARMMMUIdxBit_S12NSE1 | - ARMMMUIdxBit_S12NSE0); - } + tlb_flush_by_mmuidx(cs, mask); } =20 static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri, --=20 2.20.1 From nobody Mon Feb 9 12:19:52 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580585645615550.1689078463022; Sat, 1 Feb 2020 11:34:05 -0800 (PST) Received: from localhost ([::1]:49298 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixyWp-00040k-Hn for importer@patchew.org; Sat, 01 Feb 2020 14:34:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58591) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixySP-00078D-0B for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:30 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ixySN-0006Ty-Hs for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:28 -0500 Received: from mail-pj1-x1044.google.com ([2607:f8b0:4864:20::1044]:37521) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ixySN-0006TV-BU for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:27 -0500 Received: by mail-pj1-x1044.google.com with SMTP id m13so4554706pjb.2 for ; Sat, 01 Feb 2020 11:29:27 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id l7sm3668509pga.27.2020.02.01.11.29.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Feb 2020 11:29:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AzUgx7DiOJUVOhHsXEg+a5uyrj7Y3CYUNGvWrWhC2pQ=; b=Fd2l8S6u2H6nuK2xezUT/wp2vaX8Wo7w3oDxHdjOLlN0zDddQzaGqT9l963XM5J7Ac yqwmluCe9RCYuHCN+Qg9csudTd9Yt/fRMfZeYh42ng4ZfZG6BYgEvv05EZ/el6WkiQhb 0xXuBP9hyKTPlJIqWXsIKHTgT1oI+PatrQhyEAcJnbp0NowyNcByk67wKIYiZFvuhfit RyNYzxkPuiiAYS+dkJmSXmH/OW+HNmcjcfeGGR6b5xYL7lVJiT5/GZwuq+uk2Qa4HGCY 4tCVIT4CRJuAgCWcKAmovk46biYgg3gIoY1TNzIrC9DVtMNXVTpxm5PB/nsti3fpCJOC zGxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AzUgx7DiOJUVOhHsXEg+a5uyrj7Y3CYUNGvWrWhC2pQ=; b=Ylm7dr/mUnaSl6MO8b8K94U7rHGwrSdIYQR3IymkfO91vsSUgP/6RuTnRDbZY/4vv1 uIVRgqoaI3MT61j8U69ogSJdBCDYF/vw1oDAqogdqk46z5PRcB32A4m3YNGrYDKb2QL1 0g2mil+SDEM1K6rZFcoCIJuC+0zKSJcjZ9yv3UlqJbnn+iCtoFcDer2yMvzDx4M7UQKO 0d6cLuI45+60HapiKRV6iNUdnNAgmKL8ZuIs6iwWSKsi8GHxqLLB5C+yanwkM2GpmbS9 mmjS6ZYFu63dwRtnQqlGaCrugLZg6hLWiQFn/3XhoGBT7fBKbOEJvyFRuwzUeQfoZRrZ iqyw== X-Gm-Message-State: APjAAAWEQ5rMZuBGsSKDiGLxWn27l1SJsqBdaDjhG/uap9GtEm/Qs3QN eMxR+5bhrtYdARdYZ7BKMX3kKZLiwTM= X-Google-Smtp-Source: APXvYqwqOw7KzmGWjm+ugRuLr2sX6KrfdJcpOatGlkpcoXVdpoMICsq0hnEdBaGa+zNKO4cybvh2dQ== X-Received: by 2002:a17:90b:1256:: with SMTP id gx22mr19967229pjb.94.1580585366037; Sat, 01 Feb 2020 11:29:26 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 07/41] target/arm: Split out alle1_tlbmask Date: Sat, 1 Feb 2020 11:28:42 -0800 Message-Id: <20200201192916.31796-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200201192916.31796-1-richard.henderson@linaro.org> References: <20200201192916.31796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1044 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) No functional change, but unify code sequences. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- v5: Do not confuse things by prefixing "vm". --- target/arm/helper.c | 86 +++++++++++++-------------------------------- 1 file changed, 24 insertions(+), 62 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 8b3bb51dee..49da685b29 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3972,34 +3972,31 @@ static void tlbi_aa64_vmalle1_write(CPUARMState *en= v, const ARMCPRegInfo *ri, tlb_flush_by_mmuidx(cs, mask); } =20 -static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) +static int alle1_tlbmask(CPUARMState *env) { - /* Note that the 'ALL' scope must invalidate both stage 1 and + /* + * Note that the 'ALL' scope must invalidate both stage 1 and * stage 2 translations, whereas most other scopes only invalidate * stage 1 translations. */ - ARMCPU *cpu =3D env_archcpu(env); - CPUState *cs =3D CPU(cpu); - if (arm_is_secure_below_el3(env)) { - tlb_flush_by_mmuidx(cs, - ARMMMUIdxBit_S1SE1 | - ARMMMUIdxBit_S1SE0); + return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0; + } else if (arm_feature(env, ARM_FEATURE_EL2)) { + return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0 | ARMMMUIdxBit_= S2NS; } else { - if (arm_feature(env, ARM_FEATURE_EL2)) { - tlb_flush_by_mmuidx(cs, - ARMMMUIdxBit_S12NSE1 | - ARMMMUIdxBit_S12NSE0 | - ARMMMUIdxBit_S2NS); - } else { - tlb_flush_by_mmuidx(cs, - ARMMMUIdxBit_S12NSE1 | - ARMMMUIdxBit_S12NSE0); - } + return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0; } } =20 +static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + CPUState *cs =3D env_cpu(env); + int mask =3D alle1_tlbmask(env); + + tlb_flush_by_mmuidx(cs, mask); +} + static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -4021,28 +4018,10 @@ static void tlbi_aa64_alle3_write(CPUARMState *env,= const ARMCPRegInfo *ri, static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *= ri, uint64_t value) { - /* Note that the 'ALL' scope must invalidate both stage 1 and - * stage 2 translations, whereas most other scopes only invalidate - * stage 1 translations. - */ CPUState *cs =3D env_cpu(env); - bool sec =3D arm_is_secure_below_el3(env); - bool has_el2 =3D arm_feature(env, ARM_FEATURE_EL2); + int mask =3D alle1_tlbmask(env); =20 - if (sec) { - tlb_flush_by_mmuidx_all_cpus_synced(cs, - ARMMMUIdxBit_S1SE1 | - ARMMMUIdxBit_S1SE0); - } else if (has_el2) { - tlb_flush_by_mmuidx_all_cpus_synced(cs, - ARMMMUIdxBit_S12NSE1 | - ARMMMUIdxBit_S12NSE0 | - ARMMMUIdxBit_S2NS); - } else { - tlb_flush_by_mmuidx_all_cpus_synced(cs, - ARMMMUIdxBit_S12NSE1 | - ARMMMUIdxBit_S12NSE0); - } + tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); } =20 static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *= ri, @@ -4092,20 +4071,11 @@ static void tlbi_aa64_vae3_write(CPUARMState *env, = const ARMCPRegInfo *ri, static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *r= i, uint64_t value) { - ARMCPU *cpu =3D env_archcpu(env); - CPUState *cs =3D CPU(cpu); - bool sec =3D arm_is_secure_below_el3(env); + CPUState *cs =3D env_cpu(env); + int mask =3D vae1_tlbmask(env); uint64_t pageaddr =3D sextract64(value << 12, 0, 56); =20 - if (sec) { - tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, - ARMMMUIdxBit_S1SE1 | - ARMMMUIdxBit_S1SE0); - } else { - tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, - ARMMMUIdxBit_S12NSE1 | - ARMMMUIdxBit_S12NSE0); - } + tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, mask); } =20 static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -4116,8 +4086,8 @@ static void tlbi_aa64_vae1_write(CPUARMState *env, co= nst ARMCPRegInfo *ri, * since we don't support flush-for-specific-ASID-only or * flush-last-level-only. */ - ARMCPU *cpu =3D env_archcpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); + int mask =3D vae1_tlbmask(env); uint64_t pageaddr =3D sextract64(value << 12, 0, 56); =20 if (tlb_force_broadcast(env)) { @@ -4125,15 +4095,7 @@ static void tlbi_aa64_vae1_write(CPUARMState *env, c= onst ARMCPRegInfo *ri, return; } =20 - if (arm_is_secure_below_el3(env)) { - tlb_flush_page_by_mmuidx(cs, pageaddr, - ARMMMUIdxBit_S1SE1 | - ARMMMUIdxBit_S1SE0); - } else { - tlb_flush_page_by_mmuidx(cs, pageaddr, - ARMMMUIdxBit_S12NSE1 | - ARMMMUIdxBit_S12NSE0); - } + tlb_flush_page_by_mmuidx(cs, pageaddr, mask); } =20 static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *r= i, --=20 2.20.1 From nobody Mon Feb 9 12:19:52 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580585861986585.0539046169879; Sat, 1 Feb 2020 11:37:41 -0800 (PST) Received: from localhost ([::1]:49406 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixyaK-0002Ab-Ra for importer@patchew.org; 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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id l7sm3668509pga.27.2020.02.01.11.29.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Feb 2020 11:29:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=A62BKHsum52XJEWLW3Xhs8oGxaRzaiLid6BDgVa6hV8=; b=UGAx3YFqcbomPyR3FBmDMEKWkKdofPgypnE4thTQQVzOWGCpA1NuCStnGjVut8g/LF JzUWMA0iHGYx893to02G0PPTxd28m4PXkiPzoz7Z8OjyZ3OK+bbcjsJr+hi30Q8+Rmf1 2lvfZlZxLNsMrRux67Ka+1t3ezLxVcEAZfvhy83ksYLDUaV21hPcUzCH3tVzJWzMC/vq koYQnh2calhMRjufEW77f5ExKYtF2pAJ6T5H+7CDqORsX7I85nZljqahnrYC7RT1Hpjd KTXedRjbln0983/7E+mwj3FbyEzCpC3Phg08YyDHNVF30+t+28/6sz2FKLaKvWgTzviA 0NnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=A62BKHsum52XJEWLW3Xhs8oGxaRzaiLid6BDgVa6hV8=; b=d4aj16zqe8GlSZL56rJfqAR8uWHh/59lKN75TCRuVFZcWfjNmF43wXm44n5VkrCq5h IX8tYk9pvCGGMaT0tCvNkOUvSG28haQJAH4wgOo7gwW4C4xosreUqq32pGlK/yeKY9Ru 3LpcQGQfbERV2+yDccvL1FanGdN/NpknB+B9CqJzrnxdMs9pRKZ47E7azZeZyBEZLF8W H+P/vjmP3q57P+IZ6UwI9u2FJxwKex/gm8jktDti2+h7nQFZTu39V6eM8HswFgQurVh8 7QS8Dp+EgecOL7bJ0W20m1UD7rRcloqFdxS6Pamf+eoivcJxNYSZnCArcRw7sGS7r0lw wb5g== X-Gm-Message-State: APjAAAXR3lQeX3dIU1kHRi6C7goII9t1c8AMq518YdEK6v/8FVOdW/UQ JQuNN2qX6nOVW84TKcMzHYpgbhmwNxw= X-Google-Smtp-Source: APXvYqx45AqtRDRs49lCKAnHLYE+7mwbrweIHwKBxFRY+NGHI4xFKCzCEvzIeXQXXwz6NH8ngAeeYA== X-Received: by 2002:a17:90a:5d85:: with SMTP id t5mr19892507pji.126.1580585367087; Sat, 01 Feb 2020 11:29:27 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 08/41] target/arm: Simplify tlb_force_broadcast alternatives Date: Sat, 1 Feb 2020 11:28:43 -0800 Message-Id: <20200201192916.31796-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200201192916.31796-1-richard.henderson@linaro.org> References: <20200201192916.31796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1044 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Rather than call to a separate function and re-compute any parameters for the flush, simply use the correct flush function directly. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- target/arm/helper.c | 52 +++++++++++++++++++++------------------------ 1 file changed, 24 insertions(+), 28 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 49da685b29..bf69935550 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -614,56 +614,54 @@ static void tlbiall_write(CPUARMState *env, const ARM= CPRegInfo *ri, uint64_t value) { /* Invalidate all (TLBIALL) */ - ARMCPU *cpu =3D env_archcpu(env); + CPUState *cs =3D env_cpu(env); =20 if (tlb_force_broadcast(env)) { - tlbiall_is_write(env, NULL, value); - return; + tlb_flush_all_cpus_synced(cs); + } else { + tlb_flush(cs); } - - tlb_flush(CPU(cpu)); } =20 static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */ - ARMCPU *cpu =3D env_archcpu(env); + CPUState *cs =3D env_cpu(env); =20 + value &=3D TARGET_PAGE_MASK; if (tlb_force_broadcast(env)) { - tlbimva_is_write(env, NULL, value); - return; + tlb_flush_page_all_cpus_synced(cs, value); + } else { + tlb_flush_page(cs, value); } - - tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK); } =20 static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { /* Invalidate by ASID (TLBIASID) */ - ARMCPU *cpu =3D env_archcpu(env); + CPUState *cs =3D env_cpu(env); =20 if (tlb_force_broadcast(env)) { - tlbiasid_is_write(env, NULL, value); - return; + tlb_flush_all_cpus_synced(cs); + } else { + tlb_flush(cs); } - - tlb_flush(CPU(cpu)); } =20 static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */ - ARMCPU *cpu =3D env_archcpu(env); + CPUState *cs =3D env_cpu(env); =20 + value &=3D TARGET_PAGE_MASK; if (tlb_force_broadcast(env)) { - tlbimvaa_is_write(env, NULL, value); - return; + tlb_flush_page_all_cpus_synced(cs, value); + } else { + tlb_flush_page(cs, value); } - - tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK); } =20 static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -3965,11 +3963,10 @@ static void tlbi_aa64_vmalle1_write(CPUARMState *en= v, const ARMCPRegInfo *ri, int mask =3D vae1_tlbmask(env); =20 if (tlb_force_broadcast(env)) { - tlbi_aa64_vmalle1is_write(env, NULL, value); - return; + tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); + } else { + tlb_flush_by_mmuidx(cs, mask); } - - tlb_flush_by_mmuidx(cs, mask); } =20 static int alle1_tlbmask(CPUARMState *env) @@ -4091,11 +4088,10 @@ static void tlbi_aa64_vae1_write(CPUARMState *env, = const ARMCPRegInfo *ri, uint64_t pageaddr =3D sextract64(value << 12, 0, 56); =20 if (tlb_force_broadcast(env)) { - tlbi_aa64_vae1is_write(env, NULL, value); - return; + tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, mask); + } else { + tlb_flush_page_by_mmuidx(cs, pageaddr, mask); } - - tlb_flush_page_by_mmuidx(cs, pageaddr, mask); } =20 static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *r= i, --=20 2.20.1 From nobody Mon Feb 9 12:19:52 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580585860128855.5214940859357; Sat, 1 Feb 2020 11:37:40 -0800 (PST) Received: from localhost ([::1]:49402 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixyaI-00026G-RK for importer@patchew.org; Sat, 01 Feb 2020 14:37:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58616) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixySR-0007Dj-MR for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:33 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ixySQ-0006Xt-0b for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:31 -0500 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:42678) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ixySP-0006VS-Oz for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:29 -0500 Received: by mail-pg1-x543.google.com with SMTP id s64so5454175pgb.9 for ; Sat, 01 Feb 2020 11:29:29 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id l7sm3668509pga.27.2020.02.01.11.29.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Feb 2020 11:29:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cmYB5V5YPztxH/SIIbnRuYH/94mVqTzVwTSBflgE5dM=; b=Ab2ObkZjV3NS979IgZVNKuKLFjmLZXlwWP/fWjLk4B6LDmPoUidWEq8OYhDL9lPEvZ 9Q/nSOJdB+yMVR7910PIoz7xVXIwZ/SWpFvQYMb7vS9GebLG8AzqgKbu0ofKVicwowSE N92zXYsKj3kh95Bj87EpcZiN3H7T7YJLDG2TgyHP8AKLmREgLOsWeWjNDzbfUp35E6N0 MYlSq3KX3Ctbx8yzH+Pk1BAqKOUsh4ym6YGzkEl4EaFpHMU3bgDQ5R63qYhN3s2feNHl dwKH58mmVkUzGfw3xeCj/H4U9TpLlIGiPDzbZjCRLWkwZtStKUCUd5r1zzX0LdqDobOU SmyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cmYB5V5YPztxH/SIIbnRuYH/94mVqTzVwTSBflgE5dM=; b=Dl25K7fACiqIpXZ4HbfNO8mLRjncYG/kede315VuFPfWJUiLT6wo81Zp4bs33SW2pv GdXqoY1MkA/Jt3qw4frflK2kDeJRBv0NalDe03cABUkrrHnv0JDKUmFGHtjLvZ5AxNkn l2efrJQIWBLYD/pK2QIQ8y7Ig/GRzqPpb5mx8Up9DstdVo5FpFILHfL79cW21weM0pHB WcCehyGDlZI0nblZ9LRv/5nJ0cZgFhCT3hrBmVqWVNY8o0CweHZUbxAAuAd6U2+kaFrA cVilFnASV2pzeT4Yo8OnWTuzqqHL2GGTFN2S3ew9iX40PuUuEARqKR7krGKcZijXVrIS 0XOg== X-Gm-Message-State: APjAAAXqbsBJv0qH88n4RcpilNZDznE0TtONykw6ZaP3xM0iYl+0Jy3j dprMhYPDw/yslfHMMDD+Wk4UEVTWgGk= X-Google-Smtp-Source: APXvYqy4FVtKaCriS2ZapeLCk2Qh/gzTP3V8Cgc6R8C/iijJ8FRV85EIeePyhq/m+Uv8B+TxyVAPWw== X-Received: by 2002:a63:3e8f:: with SMTP id l137mr2492547pga.360.1580585368462; Sat, 01 Feb 2020 11:29:28 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 09/41] target/arm: Rename ARMMMUIdx*_S12NSE* to ARMMMUIdx*_E10_* Date: Sat, 1 Feb 2020 11:28:44 -0800 Message-Id: <20200201192916.31796-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200201192916.31796-1-richard.henderson@linaro.org> References: <20200201192916.31796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) This is part of a reorganization to the set of mmu_idx. This emphasizes that they apply to the EL1&0 regime. The ultimate goal is -- Non-secure regimes: ARMMMUIdx_E10_0, ARMMMUIdx_E20_0, ARMMMUIdx_E10_1, ARMMMUIdx_E2, ARMMMUIdx_E20_2, -- Secure regimes: ARMMMUIdx_SE10_0, ARMMMUIdx_SE10_1, ARMMMUIdx_SE3, -- Helper mmu_idx for non-secure EL1&0 stage1 and stage2 ARMMMUIdx_Stage2, ARMMMUIdx_Stage1_E0, ARMMMUIdx_Stage1_E1, The 'S' prefix is reserved for "Secure". Unless otherwise specified, each mmu_idx represents all stages of translation. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- target/arm/cpu.h | 8 ++++---- target/arm/internals.h | 4 ++-- target/arm/helper.c | 40 +++++++++++++++++++------------------- target/arm/translate-a64.c | 4 ++-- target/arm/translate.c | 6 +++--- 5 files changed, 31 insertions(+), 31 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0e68704a90..272104afbb 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2905,8 +2905,8 @@ static inline bool arm_excp_unmasked(CPUState *cs, un= signed int excp_idx, #define ARM_MMU_IDX_COREIDX_MASK 0x7 =20 typedef enum ARMMMUIdx { - ARMMMUIdx_S12NSE0 =3D 0 | ARM_MMU_IDX_A, - ARMMMUIdx_S12NSE1 =3D 1 | ARM_MMU_IDX_A, + ARMMMUIdx_E10_0 =3D 0 | ARM_MMU_IDX_A, + ARMMMUIdx_E10_1 =3D 1 | ARM_MMU_IDX_A, ARMMMUIdx_S1E2 =3D 2 | ARM_MMU_IDX_A, ARMMMUIdx_S1E3 =3D 3 | ARM_MMU_IDX_A, ARMMMUIdx_S1SE0 =3D 4 | ARM_MMU_IDX_A, @@ -2931,8 +2931,8 @@ typedef enum ARMMMUIdx { * for use when calling tlb_flush_by_mmuidx() and friends. */ typedef enum ARMMMUIdxBit { - ARMMMUIdxBit_S12NSE0 =3D 1 << 0, - ARMMMUIdxBit_S12NSE1 =3D 1 << 1, + ARMMMUIdxBit_E10_0 =3D 1 << 0, + ARMMMUIdxBit_E10_1 =3D 1 << 1, ARMMMUIdxBit_S1E2 =3D 1 << 2, ARMMMUIdxBit_S1E3 =3D 1 << 3, ARMMMUIdxBit_S1SE0 =3D 1 << 4, diff --git a/target/arm/internals.h b/target/arm/internals.h index f5313dd3d4..d4ea6cfe9d 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -808,8 +808,8 @@ static inline void arm_call_el_change_hook(ARMCPU *cpu) static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) { switch (mmu_idx) { - case ARMMMUIdx_S12NSE0: - case ARMMMUIdx_S12NSE1: + case ARMMMUIdx_E10_0: + case ARMMMUIdx_E10_1: case ARMMMUIdx_S1NSE0: case ARMMMUIdx_S1NSE1: case ARMMMUIdx_S1E2: diff --git a/target/arm/helper.c b/target/arm/helper.c index bf69935550..95b67ba6c5 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -670,8 +670,8 @@ static void tlbiall_nsnh_write(CPUARMState *env, const = ARMCPRegInfo *ri, CPUState *cs =3D env_cpu(env); =20 tlb_flush_by_mmuidx(cs, - ARMMMUIdxBit_S12NSE1 | - ARMMMUIdxBit_S12NSE0 | + ARMMMUIdxBit_E10_1 | + ARMMMUIdxBit_E10_0 | ARMMMUIdxBit_S2NS); } =20 @@ -681,8 +681,8 @@ static void tlbiall_nsnh_is_write(CPUARMState *env, con= st ARMCPRegInfo *ri, CPUState *cs =3D env_cpu(env); =20 tlb_flush_by_mmuidx_all_cpus_synced(cs, - ARMMMUIdxBit_S12NSE1 | - ARMMMUIdxBit_S12NSE0 | + ARMMMUIdxBit_E10_1 | + ARMMMUIdxBit_E10_0 | ARMMMUIdxBit_S2NS); } =20 @@ -3117,7 +3117,7 @@ static uint64_t do_ats_write(CPUARMState *env, uint64= _t value, format64 =3D arm_s1_regime_using_lpae_format(env, mmu_idx); =20 if (arm_feature(env, ARM_FEATURE_EL2)) { - if (mmu_idx =3D=3D ARMMMUIdx_S12NSE0 || mmu_idx =3D=3D ARMMMUI= dx_S12NSE1) { + if (mmu_idx =3D=3D ARMMMUIdx_E10_0 || mmu_idx =3D=3D ARMMMUIdx= _E10_1) { format64 |=3D env->cp15.hcr_el2 & (HCR_VM | HCR_DC); } else { format64 |=3D arm_current_el(env) =3D=3D 2; @@ -3216,11 +3216,11 @@ static void ats_write(CPUARMState *env, const ARMCP= RegInfo *ri, uint64_t value) break; case 4: /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */ - mmu_idx =3D ARMMMUIdx_S12NSE1; + mmu_idx =3D ARMMMUIdx_E10_1; break; case 6: /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */ - mmu_idx =3D ARMMMUIdx_S12NSE0; + mmu_idx =3D ARMMMUIdx_E10_0; break; default: g_assert_not_reached(); @@ -3278,10 +3278,10 @@ static void ats_write64(CPUARMState *env, const ARM= CPRegInfo *ri, mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0; break; case 4: /* AT S12E1R, AT S12E1W */ - mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S12NSE1; + mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_E10_1; break; case 6: /* AT S12E0R, AT S12E0W */ - mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S12NSE0; + mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_E10_0; break; default: g_assert_not_reached(); @@ -3581,8 +3581,8 @@ static void vttbr_write(CPUARMState *env, const ARMCP= RegInfo *ri, /* Accesses to VTTBR may change the VMID so we must flush the TLB. */ if (raw_read(env, ri) !=3D value) { tlb_flush_by_mmuidx(cs, - ARMMMUIdxBit_S12NSE1 | - ARMMMUIdxBit_S12NSE0 | + ARMMMUIdxBit_E10_1 | + ARMMMUIdxBit_E10_0 | ARMMMUIdxBit_S2NS); raw_write(env, ri, value); } @@ -3943,7 +3943,7 @@ static int vae1_tlbmask(CPUARMState *env) if (arm_is_secure_below_el3(env)) { return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0; } else { - return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0; + return ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_0; } } =20 @@ -3979,9 +3979,9 @@ static int alle1_tlbmask(CPUARMState *env) if (arm_is_secure_below_el3(env)) { return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0; } else if (arm_feature(env, ARM_FEATURE_EL2)) { - return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0 | ARMMMUIdxBit_= S2NS; + return ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_0 | ARMMMUIdxBit_S2NS; } else { - return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0; + return ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_0; } } =20 @@ -8817,8 +8817,8 @@ static inline TCR *regime_tcr(CPUARMState *env, ARMMM= UIdx mmu_idx) */ static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) { - if (mmu_idx =3D=3D ARMMMUIdx_S12NSE0 || mmu_idx =3D=3D ARMMMUIdx_S12NS= E1) { - mmu_idx +=3D (ARMMMUIdx_S1NSE0 - ARMMMUIdx_S12NSE0); + if (mmu_idx =3D=3D ARMMMUIdx_E10_0 || mmu_idx =3D=3D ARMMMUIdx_E10_1) { + mmu_idx +=3D (ARMMMUIdx_S1NSE0 - ARMMMUIdx_E10_0); } return mmu_idx; } @@ -8861,8 +8861,8 @@ static inline bool regime_is_user(CPUARMState *env, A= RMMMUIdx mmu_idx) return true; default: return false; - case ARMMMUIdx_S12NSE0: - case ARMMMUIdx_S12NSE1: + case ARMMMUIdx_E10_0: + case ARMMMUIdx_E10_1: g_assert_not_reached(); } } @@ -10766,7 +10766,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong a= ddress, target_ulong *page_size, ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) { - if (mmu_idx =3D=3D ARMMMUIdx_S12NSE0 || mmu_idx =3D=3D ARMMMUIdx_S12NS= E1) { + if (mmu_idx =3D=3D ARMMMUIdx_E10_0 || mmu_idx =3D=3D ARMMMUIdx_E10_1) { /* Call ourselves recursively to do the stage 1 and then stage 2 * translations. */ @@ -11294,7 +11294,7 @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el) if (el < 2 && arm_is_secure_below_el3(env)) { return ARMMMUIdx_S1SE0 + el; } else { - return ARMMMUIdx_S12NSE0 + el; + return ARMMMUIdx_E10_0 + el; } } =20 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 766a03335b..cb539b1eff 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -113,8 +113,8 @@ static inline int get_a64_user_mem_index(DisasContext *= s) ARMMMUIdx useridx; =20 switch (s->mmu_idx) { - case ARMMMUIdx_S12NSE1: - useridx =3D ARMMMUIdx_S12NSE0; + case ARMMMUIdx_E10_1: + useridx =3D ARMMMUIdx_E10_0; break; case ARMMMUIdx_S1SE1: useridx =3D ARMMMUIdx_S1SE0; diff --git a/target/arm/translate.c b/target/arm/translate.c index 2f4aea927f..f90f22ef90 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -153,9 +153,9 @@ static inline int get_a32_user_mem_index(DisasContext *= s) */ switch (s->mmu_idx) { case ARMMMUIdx_S1E2: /* this one is UNPREDICTABLE */ - case ARMMMUIdx_S12NSE0: - case ARMMMUIdx_S12NSE1: - return arm_to_core_mmu_idx(ARMMMUIdx_S12NSE0); + case ARMMMUIdx_E10_0: + case ARMMMUIdx_E10_1: + return arm_to_core_mmu_idx(ARMMMUIdx_E10_0); case ARMMMUIdx_S1E3: case ARMMMUIdx_S1SE0: case ARMMMUIdx_S1SE1: --=20 2.20.1 From nobody Mon Feb 9 12:19:52 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580586109796977.5782214242544; Sat, 1 Feb 2020 11:41:49 -0800 (PST) Received: from localhost ([::1]:49618 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixyeK-0000bP-4Q for importer@patchew.org; Sat, 01 Feb 2020 14:41:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58633) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixyST-0007Ik-Pd for qemu-devel@nongnu.org; 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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id l7sm3668509pga.27.2020.02.01.11.29.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Feb 2020 11:29:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ULe0d2VDtFQcq1SrU8CPt7ivI/nd9Yo9n6DCKCJtbsg=; b=R7Q6R/KhU0/29yUkUVrdp0hviHkuYMXHQ0sgyA22/yrgH6h81hNrFRLa/CwG6to5Yp lTMwdPqy3HHeydCcvP0TDLBhxhRK8bqhLd2UQQrcWgLzshMoRdNGjb2Ze2VCWDNyS+pD NVTWqbty96Lpj7UIAHzm9EX300uRGUJQltHpwBRW0F5sQ+E7Q3PVtG+8Pb7/A/LGl5xl k6uic43FzWNez8/Zv3RklxVvlkT1EmaBPAkIWg8JWvPa6JFLDiJEZli9tcoYp2PqTd/1 rxHgdkePJ08qUYDUIE7cluqwFYmtFNdWm9cJynArSESndsd7eG6iczwep3LaQSBmcPVH M7OA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ULe0d2VDtFQcq1SrU8CPt7ivI/nd9Yo9n6DCKCJtbsg=; b=WUlqeVdDcJuKuxMzVzVUhMI7aWn3O+3R1+1xn2glgEhuZ52ZyVZXjzTC8WX37ihe4W Eg9nalJPMVIwCjJWX2otzd+e3th7tjO3A5t/pqEBKwXhhK+d96Y/szinhPGP01w+tryW X3rI3emSLgG0pZiuY1l58+W7/lRWfZFjZh2OI6iDcgeQ1Tn6GqL8WWIVaq7/t9XuMcge pMc9eYQCpXB+9oLvSHkA1BWAy3K1peSw368szqvWMWqSGaDb/yysOY0nJWYRgr5E5s2v ufh57dSZ8aI7ezq6SgdW1wIPKY8D4H2k1ELvkxtABwJiMCWSe++s1+PjsktcEFQr8agx JSYg== X-Gm-Message-State: APjAAAVaU+Gg46GXRume0ziSAjGGPzrKdVPzdsNZwiYmVGp4+EryQb2p rXmpvsjpX0UsspLq9m3KHZepa+2V3ME= X-Google-Smtp-Source: APXvYqyMfy37pzEPL8PSOprkrQW9R3LWAaFFwiSaIux89gnu4lbSwWoaETYPP2zHxggSfLiRU6nBog== X-Received: by 2002:a62:cd8f:: with SMTP id o137mr17642547pfg.254.1580585370065; Sat, 01 Feb 2020 11:29:30 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 10/41] target/arm: Rename ARMMMUIdx_S2NS to ARMMMUIdx_Stage2 Date: Sat, 1 Feb 2020 11:28:45 -0800 Message-Id: <20200201192916.31796-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200201192916.31796-1-richard.henderson@linaro.org> References: <20200201192916.31796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) The EL1&0 regime is the only one that uses 2-stage translation. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- target/arm/cpu.h | 4 +-- target/arm/internals.h | 2 +- target/arm/helper.c | 57 ++++++++++++++++++++------------------ target/arm/translate-a64.c | 2 +- target/arm/translate.c | 2 +- 5 files changed, 35 insertions(+), 32 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 272104afbb..c6da3d3043 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2911,7 +2911,7 @@ typedef enum ARMMMUIdx { ARMMMUIdx_S1E3 =3D 3 | ARM_MMU_IDX_A, ARMMMUIdx_S1SE0 =3D 4 | ARM_MMU_IDX_A, ARMMMUIdx_S1SE1 =3D 5 | ARM_MMU_IDX_A, - ARMMMUIdx_S2NS =3D 6 | ARM_MMU_IDX_A, + ARMMMUIdx_Stage2 =3D 6 | ARM_MMU_IDX_A, ARMMMUIdx_MUser =3D 0 | ARM_MMU_IDX_M, ARMMMUIdx_MPriv =3D 1 | ARM_MMU_IDX_M, ARMMMUIdx_MUserNegPri =3D 2 | ARM_MMU_IDX_M, @@ -2937,7 +2937,7 @@ typedef enum ARMMMUIdxBit { ARMMMUIdxBit_S1E3 =3D 1 << 3, ARMMMUIdxBit_S1SE0 =3D 1 << 4, ARMMMUIdxBit_S1SE1 =3D 1 << 5, - ARMMMUIdxBit_S2NS =3D 1 << 6, + ARMMMUIdxBit_Stage2 =3D 1 << 6, ARMMMUIdxBit_MUser =3D 1 << 0, ARMMMUIdxBit_MPriv =3D 1 << 1, ARMMMUIdxBit_MUserNegPri =3D 1 << 2, diff --git a/target/arm/internals.h b/target/arm/internals.h index d4ea6cfe9d..1509e45e98 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -813,7 +813,7 @@ static inline bool regime_is_secure(CPUARMState *env, A= RMMMUIdx mmu_idx) case ARMMMUIdx_S1NSE0: case ARMMMUIdx_S1NSE1: case ARMMMUIdx_S1E2: - case ARMMMUIdx_S2NS: + case ARMMMUIdx_Stage2: case ARMMMUIdx_MPrivNegPri: case ARMMMUIdx_MUserNegPri: case ARMMMUIdx_MPriv: diff --git a/target/arm/helper.c b/target/arm/helper.c index 95b67ba6c5..a6d4f449cc 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -672,7 +672,7 @@ static void tlbiall_nsnh_write(CPUARMState *env, const = ARMCPRegInfo *ri, tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_0 | - ARMMMUIdxBit_S2NS); + ARMMMUIdxBit_Stage2); } =20 static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -683,7 +683,7 @@ static void tlbiall_nsnh_is_write(CPUARMState *env, con= st ARMCPRegInfo *ri, tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_0 | - ARMMMUIdxBit_S2NS); + ARMMMUIdxBit_Stage2); } =20 static void tlbiipas2_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -704,7 +704,7 @@ static void tlbiipas2_write(CPUARMState *env, const ARM= CPRegInfo *ri, =20 pageaddr =3D sextract64(value << 12, 0, 40); =20 - tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S2NS); + tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_Stage2); } =20 static void tlbiipas2_is_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -720,7 +720,7 @@ static void tlbiipas2_is_write(CPUARMState *env, const = ARMCPRegInfo *ri, pageaddr =3D sextract64(value << 12, 0, 40); =20 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, - ARMMMUIdxBit_S2NS); + ARMMMUIdxBit_Stage2); } =20 static void tlbiall_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -3578,12 +3578,15 @@ static void vttbr_write(CPUARMState *env, const ARM= CPRegInfo *ri, ARMCPU *cpu =3D env_archcpu(env); CPUState *cs =3D CPU(cpu); =20 - /* Accesses to VTTBR may change the VMID so we must flush the TLB. */ + /* + * A change in VMID to the stage2 page table (Stage2) invalidates + * the combined stage 1&2 tlbs (EL10_1 and EL10_0). + */ if (raw_read(env, ri) !=3D value) { tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_0 | - ARMMMUIdxBit_S2NS); + ARMMMUIdxBit_Stage2); raw_write(env, ri, value); } } @@ -3979,7 +3982,7 @@ static int alle1_tlbmask(CPUARMState *env) if (arm_is_secure_below_el3(env)) { return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0; } else if (arm_feature(env, ARM_FEATURE_EL2)) { - return ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_0 | ARMMMUIdxBit_S2NS; + return ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_0 | ARMMMUIdxBit_Stag= e2; } else { return ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_0; } @@ -4133,7 +4136,7 @@ static void tlbi_aa64_ipas2e1_write(CPUARMState *env,= const ARMCPRegInfo *ri, =20 pageaddr =3D sextract64(value << 12, 0, 48); =20 - tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S2NS); + tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_Stage2); } =20 static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo= *ri, @@ -4149,7 +4152,7 @@ static void tlbi_aa64_ipas2e1is_write(CPUARMState *en= v, const ARMCPRegInfo *ri, pageaddr =3D sextract64(value << 12, 0, 48); =20 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, - ARMMMUIdxBit_S2NS); + ARMMMUIdxBit_Stage2); } =20 static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo= *ri, @@ -8706,7 +8709,7 @@ void arm_cpu_do_interrupt(CPUState *cs) static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) { switch (mmu_idx) { - case ARMMMUIdx_S2NS: + case ARMMMUIdx_Stage2: case ARMMMUIdx_S1E2: return 2; case ARMMMUIdx_S1E3: @@ -8760,7 +8763,7 @@ static inline bool regime_translation_disabled(CPUARM= State *env, } } =20 - if (mmu_idx =3D=3D ARMMMUIdx_S2NS) { + if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { /* HCR.DC means HCR.VM behaves as 1 */ return (env->cp15.hcr_el2 & (HCR_DC | HCR_VM)) =3D=3D 0; } @@ -8791,7 +8794,7 @@ static inline bool regime_translation_big_endian(CPUA= RMState *env, static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, int ttbrn) { - if (mmu_idx =3D=3D ARMMMUIdx_S2NS) { + if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { return env->cp15.vttbr_el2; } if (ttbrn =3D=3D 0) { @@ -8806,7 +8809,7 @@ static inline uint64_t regime_ttbr(CPUARMState *env, = ARMMMUIdx mmu_idx, /* Return the TCR controlling this translation regime */ static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) { - if (mmu_idx =3D=3D ARMMMUIdx_S2NS) { + if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { return &env->cp15.vtcr_el2; } return &env->cp15.tcr_el[regime_el(env, mmu_idx)]; @@ -8993,7 +8996,7 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu= _idx, bool is_aa64, bool have_wxn; int wxn =3D 0; =20 - assert(mmu_idx !=3D ARMMMUIdx_S2NS); + assert(mmu_idx !=3D ARMMMUIdx_Stage2); =20 user_rw =3D simple_ap_to_rw_prot_is_user(ap, true); if (is_user) { @@ -9085,7 +9088,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMM= MUIdx mmu_idx, ARMMMUFaultInfo *fi) { if ((mmu_idx =3D=3D ARMMMUIdx_S1NSE0 || mmu_idx =3D=3D ARMMMUIdx_S1NSE= 1) && - !regime_translation_disabled(env, ARMMMUIdx_S2NS)) { + !regime_translation_disabled(env, ARMMMUIdx_Stage2)) { target_ulong s2size; hwaddr s2pa; int s2prot; @@ -9102,7 +9105,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMM= MUIdx mmu_idx, pcacheattrs =3D &cacheattrs; } =20 - ret =3D get_phys_addr_lpae(env, addr, 0, ARMMMUIdx_S2NS, &s2pa, + ret =3D get_phys_addr_lpae(env, addr, 0, ARMMMUIdx_Stage2, &s2pa, &txattrs, &s2prot, &s2size, fi, pcacheatt= rs); if (ret) { assert(fi->type !=3D ARMFault_None); @@ -9574,7 +9577,7 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *= env, uint64_t va, tsz =3D extract32(tcr, 0, 6); using64k =3D extract32(tcr, 14, 1); using16k =3D extract32(tcr, 15, 1); - if (mmu_idx =3D=3D ARMMMUIdx_S2NS) { + if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { /* VTCR_EL2 */ tbi =3D tbid =3D hpd =3D false; } else { @@ -9635,7 +9638,7 @@ static ARMVAParameters aa32_va_parameters(CPUARMState= *env, uint32_t va, int select, tsz; bool epd, hpd; =20 - if (mmu_idx =3D=3D ARMMMUIdx_S2NS) { + if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { /* VTCR */ bool sext =3D extract32(tcr, 4, 1); bool sign =3D extract32(tcr, 3, 1); @@ -9737,7 +9740,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, targ= et_ulong address, level =3D 1; /* There is no TTBR1 for EL2 */ ttbr1_valid =3D (el !=3D 2); - addrsize =3D (mmu_idx =3D=3D ARMMMUIdx_S2NS ? 40 : 32); + addrsize =3D (mmu_idx =3D=3D ARMMMUIdx_Stage2 ? 40 : 32); inputsize =3D addrsize - param.tsz; } =20 @@ -9788,7 +9791,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, targ= et_ulong address, goto do_fault; } =20 - if (mmu_idx !=3D ARMMMUIdx_S2NS) { + if (mmu_idx !=3D ARMMMUIdx_Stage2) { /* The starting level depends on the virtual address size (which c= an * be up to 48 bits) and the translation granule size. It indicates * the number of strides (stride bits at a time) needed to @@ -9888,7 +9891,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, targ= et_ulong address, attrs =3D extract64(descriptor, 2, 10) | (extract64(descriptor, 52, 12) << 10); =20 - if (mmu_idx =3D=3D ARMMMUIdx_S2NS) { + if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { /* Stage 2 table descriptors do not include any attribute fiel= ds */ break; } @@ -9919,7 +9922,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, targ= et_ulong address, ap =3D extract32(attrs, 4, 2); xn =3D extract32(attrs, 12, 1); =20 - if (mmu_idx =3D=3D ARMMMUIdx_S2NS) { + if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { ns =3D true; *prot =3D get_S2prot(env, ap, xn); } else { @@ -9946,7 +9949,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, targ= et_ulong address, } =20 if (cacheattrs !=3D NULL) { - if (mmu_idx =3D=3D ARMMMUIdx_S2NS) { + if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { cacheattrs->attrs =3D convert_stage2_attrs(env, extract32(attrs, 0, 4= )); } else { @@ -9967,7 +9970,7 @@ do_fault: fi->type =3D fault_type; fi->level =3D level; /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */ - fi->stage2 =3D fi->s1ptw || (mmu_idx =3D=3D ARMMMUIdx_S2NS); + fi->stage2 =3D fi->s1ptw || (mmu_idx =3D=3D ARMMMUIdx_Stage2); return true; } =20 @@ -10781,13 +10784,13 @@ bool get_phys_addr(CPUARMState *env, target_ulong= address, prot, page_size, fi, cacheattrs); =20 /* If S1 fails or S2 is disabled, return early. */ - if (ret || regime_translation_disabled(env, ARMMMUIdx_S2NS)) { + if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2))= { *phys_ptr =3D ipa; return ret; } =20 /* S1 is done. Now do S2 translation. */ - ret =3D get_phys_addr_lpae(env, ipa, access_type, ARMMMUIdx_S2= NS, + ret =3D get_phys_addr_lpae(env, ipa, access_type, ARMMMUIdx_St= age2, phys_ptr, attrs, &s2_prot, page_size, fi, cacheattrs !=3D NULL ? &cacheattrs2 := NULL); @@ -10829,7 +10832,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong a= ddress, /* Fast Context Switch Extension. This doesn't exist at all in v8. * In v7 and earlier it affects all stage 1 translations. */ - if (address < 0x02000000 && mmu_idx !=3D ARMMMUIdx_S2NS + if (address < 0x02000000 && mmu_idx !=3D ARMMMUIdx_Stage2 && !arm_feature(env, ARM_FEATURE_V8)) { if (regime_el(env, mmu_idx) =3D=3D 3) { address +=3D env->cp15.fcseidr_s; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index cb539b1eff..d0d13e2175 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -119,7 +119,7 @@ static inline int get_a64_user_mem_index(DisasContext *= s) case ARMMMUIdx_S1SE1: useridx =3D ARMMMUIdx_S1SE0; break; - case ARMMMUIdx_S2NS: + case ARMMMUIdx_Stage2: g_assert_not_reached(); default: useridx =3D s->mmu_idx; diff --git a/target/arm/translate.c b/target/arm/translate.c index f90f22ef90..70b1fd3fe2 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -172,7 +172,7 @@ static inline int get_a32_user_mem_index(DisasContext *= s) case ARMMMUIdx_MSUserNegPri: case ARMMMUIdx_MSPrivNegPri: return arm_to_core_mmu_idx(ARMMMUIdx_MSUserNegPri); - case ARMMMUIdx_S2NS: + case ARMMMUIdx_Stage2: default: g_assert_not_reached(); } --=20 2.20.1 From nobody Mon Feb 9 12:19:52 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580585959171924.9762734767995; Sat, 1 Feb 2020 11:39:19 -0800 (PST) Received: from localhost ([::1]:49452 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixybs-0005Uu-K4 for importer@patchew.org; Sat, 01 Feb 2020 14:39:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58638) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixySU-0007Jf-70 for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:35 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ixySS-0006gn-NW for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:34 -0500 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:38465) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ixySS-0006ef-Gt for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:32 -0500 Received: by mail-pg1-x543.google.com with SMTP id a33so5482460pgm.5 for ; Sat, 01 Feb 2020 11:29:32 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id l7sm3668509pga.27.2020.02.01.11.29.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Feb 2020 11:29:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Y5by4nRmhNXf+xlMKpQf9OWkKPnfJWjLjLomV+oSrFM=; b=kK65EsrhjciXvmN7+4UrnhiLHhNmzssa2UibMLRcMNncn55X2Q9f0/RxCgNqVzg0AA y5LgSBy+xgmjR8eQ7382up4PycqP3uRakmbAxe1Exvw/F3i5LP1Ml32+lQMTmtBuJ61E eewf77S5rTBUmnMbdoeyDTw+KPPAmICE8JRochvuuhhVr4oqiBu3Ui565Uwd5WpD6NQW I0Yp9xSgvc4cCp/0be/ro4XT2pvMhVDGBV666LZYsvlFF00WLNu+wmvP6N/VgKjfM9dd LF0Hifdrg5DIXJ2Y8vYzXXmDoZp1va5haJ6vTCQ3Rj+KiF8fKA8SIlok+5xgeCjk+22d y4tg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Y5by4nRmhNXf+xlMKpQf9OWkKPnfJWjLjLomV+oSrFM=; b=BFdWn3n2kuv0v2KitF4UBB58eWJWG84nduylJ/x51mDCvgfM6KMFJmqd7p47o4mLUJ S0/AyEISQ7kJ6/c4/wD1CnCmFsoaGeTSnHd1170hrIh4s7M2xkhIAYp3LXHJknyJcf+5 69i8RtHEBqW4CKNaJfe/9g+SqzLqB6b6vfuE3B5MGNyGetsUUi6MIYREfF7ynwrM9lSS Eyex/1LVZ7iEF1cXCIp5aDsVRG0e4b2smSKl2EVPRR9xA8UrgU2cmCs+z4xwAQYLM94F ZZXpy07lwosmW+oBmnzhiIse94QiaKBbmPQSrDxmgiYVxQczO37Z/TkMLNdbFJvOI2Z8 K4zA== X-Gm-Message-State: APjAAAWPM1myOXWMbxhf8waLSAATkSIRVbihs/te9MSzJ0GRaJ9zJ3Gj NruEgahSJIJ9KG+5R4ZNuourwWVAmrw= X-Google-Smtp-Source: APXvYqx9QNDNiQje+GZ/xt+nmuwg/YfY8ebbzhCIhqB6a2n8axCwPh6onxVEVdbi20aQ4K+dnuYVJQ== X-Received: by 2002:a62:ee0f:: with SMTP id e15mr6613943pfi.256.1580585371277; Sat, 01 Feb 2020 11:29:31 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 11/41] target/arm: Rename ARMMMUIdx_S1NSE* to ARMMMUIdx_Stage1_E* Date: Sat, 1 Feb 2020 11:28:46 -0800 Message-Id: <20200201192916.31796-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200201192916.31796-1-richard.henderson@linaro.org> References: <20200201192916.31796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) This is part of a reorganization to the set of mmu_idx. The EL1&0 regime is the only one that uses 2-stage translation. Spelling out Stage avoids confusion with Secure. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- v5: Adjust || indentation (ajb) --- target/arm/cpu.h | 4 ++-- target/arm/internals.h | 6 +++--- target/arm/helper.c | 27 ++++++++++++++------------- 3 files changed, 19 insertions(+), 18 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c6da3d3043..afc3e76ce5 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2923,8 +2923,8 @@ typedef enum ARMMMUIdx { /* Indexes below here don't have TLBs and are used only for AT system * instructions or for the first stage of an S12 page table walk. */ - ARMMMUIdx_S1NSE0 =3D 0 | ARM_MMU_IDX_NOTLB, - ARMMMUIdx_S1NSE1 =3D 1 | ARM_MMU_IDX_NOTLB, + ARMMMUIdx_Stage1_E0 =3D 0 | ARM_MMU_IDX_NOTLB, + ARMMMUIdx_Stage1_E1 =3D 1 | ARM_MMU_IDX_NOTLB, } ARMMMUIdx; =20 /* Bit macros for the core-mmu-index values for each index, diff --git a/target/arm/internals.h b/target/arm/internals.h index 1509e45e98..280b5b0c82 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -810,8 +810,8 @@ static inline bool regime_is_secure(CPUARMState *env, A= RMMMUIdx mmu_idx) switch (mmu_idx) { case ARMMMUIdx_E10_0: case ARMMMUIdx_E10_1: - case ARMMMUIdx_S1NSE0: - case ARMMMUIdx_S1NSE1: + case ARMMMUIdx_Stage1_E0: + case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_S1E2: case ARMMMUIdx_Stage2: case ARMMMUIdx_MPrivNegPri: @@ -975,7 +975,7 @@ ARMMMUIdx arm_mmu_idx(CPUARMState *env); #ifdef CONFIG_USER_ONLY static inline ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) { - return ARMMMUIdx_S1NSE0; + return ARMMMUIdx_Stage1_E0; } #else ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env); diff --git a/target/arm/helper.c b/target/arm/helper.c index a6d4f449cc..2d87c3a2e5 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3041,7 +3041,8 @@ static uint64_t do_ats_write(CPUARMState *env, uint64= _t value, bool take_exc =3D false; =20 if (fi.s1ptw && current_el =3D=3D 1 && !arm_is_secure(env) - && (mmu_idx =3D=3D ARMMMUIdx_S1NSE1 || mmu_idx =3D=3D ARMMMUId= x_S1NSE0)) { + && (mmu_idx =3D=3D ARMMMUIdx_Stage1_E1 || + mmu_idx =3D=3D ARMMMUIdx_Stage1_E0)) { /* * Synchronous stage 2 fault on an access made as part of the * translation table walk for AT S1E0* or AT S1E1* insn @@ -3189,10 +3190,10 @@ static void ats_write(CPUARMState *env, const ARMCP= RegInfo *ri, uint64_t value) mmu_idx =3D ARMMMUIdx_S1E3; break; case 2: - mmu_idx =3D ARMMMUIdx_S1NSE1; + mmu_idx =3D ARMMMUIdx_Stage1_E1; break; case 1: - mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1; + mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_Stage1_E1; break; default: g_assert_not_reached(); @@ -3205,10 +3206,10 @@ static void ats_write(CPUARMState *env, const ARMCP= RegInfo *ri, uint64_t value) mmu_idx =3D ARMMMUIdx_S1SE0; break; case 2: - mmu_idx =3D ARMMMUIdx_S1NSE0; + mmu_idx =3D ARMMMUIdx_Stage1_E0; break; case 1: - mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0; + mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_Stage1_E0; break; default: g_assert_not_reached(); @@ -3262,7 +3263,7 @@ static void ats_write64(CPUARMState *env, const ARMCP= RegInfo *ri, case 0: switch (ri->opc1) { case 0: /* AT S1E1R, AT S1E1W */ - mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1; + mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_Stage1_E1; break; case 4: /* AT S1E2R, AT S1E2W */ mmu_idx =3D ARMMMUIdx_S1E2; @@ -3275,7 +3276,7 @@ static void ats_write64(CPUARMState *env, const ARMCP= RegInfo *ri, } break; case 2: /* AT S1E0R, AT S1E0W */ - mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0; + mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_Stage1_E0; break; case 4: /* AT S12E1R, AT S12E1W */ mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_E10_1; @@ -8717,8 +8718,8 @@ static inline uint32_t regime_el(CPUARMState *env, AR= MMMUIdx mmu_idx) case ARMMMUIdx_S1SE0: return arm_el_is_aa64(env, 3) ? 1 : 3; case ARMMMUIdx_S1SE1: - case ARMMMUIdx_S1NSE0: - case ARMMMUIdx_S1NSE1: + case ARMMMUIdx_Stage1_E0: + case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_MPrivNegPri: case ARMMMUIdx_MUserNegPri: case ARMMMUIdx_MPriv: @@ -8776,7 +8777,7 @@ static inline bool regime_translation_disabled(CPUARM= State *env, } =20 if ((env->cp15.hcr_el2 & HCR_DC) && - (mmu_idx =3D=3D ARMMMUIdx_S1NSE0 || mmu_idx =3D=3D ARMMMUIdx_S1NSE= 1)) { + (mmu_idx =3D=3D ARMMMUIdx_Stage1_E0 || mmu_idx =3D=3D ARMMMUIdx_St= age1_E1)) { /* HCR.DC means SCTLR_EL1.M behaves as 0 */ return true; } @@ -8821,7 +8822,7 @@ static inline TCR *regime_tcr(CPUARMState *env, ARMMM= UIdx mmu_idx) static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) { if (mmu_idx =3D=3D ARMMMUIdx_E10_0 || mmu_idx =3D=3D ARMMMUIdx_E10_1) { - mmu_idx +=3D (ARMMMUIdx_S1NSE0 - ARMMMUIdx_E10_0); + mmu_idx +=3D (ARMMMUIdx_Stage1_E0 - ARMMMUIdx_E10_0); } return mmu_idx; } @@ -8856,7 +8857,7 @@ static inline bool regime_is_user(CPUARMState *env, A= RMMMUIdx mmu_idx) { switch (mmu_idx) { case ARMMMUIdx_S1SE0: - case ARMMMUIdx_S1NSE0: + case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_MUser: case ARMMMUIdx_MSUser: case ARMMMUIdx_MUserNegPri: @@ -9087,7 +9088,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMM= MUIdx mmu_idx, hwaddr addr, MemTxAttrs txattrs, ARMMMUFaultInfo *fi) { - if ((mmu_idx =3D=3D ARMMMUIdx_S1NSE0 || mmu_idx =3D=3D ARMMMUIdx_S1NSE= 1) && + if ((mmu_idx =3D=3D ARMMMUIdx_Stage1_E0 || mmu_idx =3D=3D ARMMMUIdx_St= age1_E1) && !regime_translation_disabled(env, ARMMMUIdx_Stage2)) { target_ulong s2size; hwaddr s2pa; --=20 2.20.1 From nobody Mon Feb 9 12:19:52 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580585761227224.50575256008096; Sat, 1 Feb 2020 11:36:01 -0800 (PST) Received: from localhost ([::1]:49352 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixyYh-0007W3-L9 for importer@patchew.org; Sat, 01 Feb 2020 14:35:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58654) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixySV-0007Kq-KE for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:37 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ixySU-0006jv-5H for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:35 -0500 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:39201) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ixyST-0006j8-TP for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:34 -0500 Received: by mail-pg1-x543.google.com with SMTP id 4so5475056pgd.6 for ; Sat, 01 Feb 2020 11:29:33 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id l7sm3668509pga.27.2020.02.01.11.29.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Feb 2020 11:29:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8abGUoVu8LG8qwqLkIDSjwMugrxPoYzd4OHnIrb3Z3o=; b=WZaWiKOmi1ll8Z/Jo1ulQo89mihSP8Zak4f4vm+lxYeLnVMN4wC77JZftgHS0zUYZs rdYAmTyTXBuah92xT3q1ATBso6E7IMvPfuYBmZa1wDk35hpgMZlMTVVLyRJ+/QqfRjiP /PyjO6NBZqasLpIwLePCNZPRXN02XSwOfPAyca345PARzrtfndNWa7vysrQfQDUrFYC4 QI5idxD5S/h7j7LVSzKeXdmcij2cx21ba9lkaUEJYn5nkDVlr4yGdZVsK1yt9tSl6s79 p2UB2cJDw4CC7UyzYVmLFvmlr1/6JYdPQxtwAVg2pna+fr+ZZvpQXSnBHZewLljJFZBr bCNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8abGUoVu8LG8qwqLkIDSjwMugrxPoYzd4OHnIrb3Z3o=; b=lkzSvSeTza/RdctWZltWuqIan750522DgZcE2AK2GPCpBZWKZkf3XhmVng7SjgeO7e IOmmeTxhcDNFS74Xvf0JZwnafwBUeAQAgsLDbA3KwfS2t8trpSczAuWA7sdDJdJjrJCQ 26VR7Mh26bRyZAbTMyMLPgSlsY8omhwuvTcNCxV+AsRJSbay6KfpshiKrTaLLldKaq5G u2OcEjFR1UE1HtPAQy2Vxywh2e6b9ImJ2hamyX0LdlmhPgIWSRQB14hALygAdWuMb2xO MPuAZ6D1dPm5V+MrNkMKJge7i+kolFuStgMGEGmVOKzFP0pTK35gjCI7Ja6NOZ4ki61q IRvA== X-Gm-Message-State: APjAAAXjxdOyuSNDOiqHb+sA9JkcFnEygULAwtLifm4pvmA4wA2ckK8C 3xIjTMfQl3lc7kqaJEt/h+J0y9h7ah4= X-Google-Smtp-Source: APXvYqzJ+G6mVDcrhM1+MAG1VaeZ9rjimz+4HKE0JgoQ6+IVN2rq4bviLSxZIUVW3h81X6XdVk3Nsw== X-Received: by 2002:a63:6f0a:: with SMTP id k10mr17342773pgc.113.1580585372556; Sat, 01 Feb 2020 11:29:32 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 12/41] target/arm: Rename ARMMMUIdx_S1SE[01] to ARMMMUIdx_SE10_[01] Date: Sat, 1 Feb 2020 11:28:47 -0800 Message-Id: <20200201192916.31796-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200201192916.31796-1-richard.henderson@linaro.org> References: <20200201192916.31796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) This is part of a reorganization to the set of mmu_idx. This emphasizes that they apply to the Secure EL1&0 regime. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- target/arm/cpu.h | 8 ++++---- target/arm/internals.h | 4 ++-- target/arm/translate.h | 2 +- target/arm/helper.c | 26 +++++++++++++------------- target/arm/translate-a64.c | 4 ++-- target/arm/translate.c | 6 +++--- 6 files changed, 25 insertions(+), 25 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index afc3e76ce5..6cf2b3d6fd 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2909,8 +2909,8 @@ typedef enum ARMMMUIdx { ARMMMUIdx_E10_1 =3D 1 | ARM_MMU_IDX_A, ARMMMUIdx_S1E2 =3D 2 | ARM_MMU_IDX_A, ARMMMUIdx_S1E3 =3D 3 | ARM_MMU_IDX_A, - ARMMMUIdx_S1SE0 =3D 4 | ARM_MMU_IDX_A, - ARMMMUIdx_S1SE1 =3D 5 | ARM_MMU_IDX_A, + ARMMMUIdx_SE10_0 =3D 4 | ARM_MMU_IDX_A, + ARMMMUIdx_SE10_1 =3D 5 | ARM_MMU_IDX_A, ARMMMUIdx_Stage2 =3D 6 | ARM_MMU_IDX_A, ARMMMUIdx_MUser =3D 0 | ARM_MMU_IDX_M, ARMMMUIdx_MPriv =3D 1 | ARM_MMU_IDX_M, @@ -2935,8 +2935,8 @@ typedef enum ARMMMUIdxBit { ARMMMUIdxBit_E10_1 =3D 1 << 1, ARMMMUIdxBit_S1E2 =3D 1 << 2, ARMMMUIdxBit_S1E3 =3D 1 << 3, - ARMMMUIdxBit_S1SE0 =3D 1 << 4, - ARMMMUIdxBit_S1SE1 =3D 1 << 5, + ARMMMUIdxBit_SE10_0 =3D 1 << 4, + ARMMMUIdxBit_SE10_1 =3D 1 << 5, ARMMMUIdxBit_Stage2 =3D 1 << 6, ARMMMUIdxBit_MUser =3D 1 << 0, ARMMMUIdxBit_MPriv =3D 1 << 1, diff --git a/target/arm/internals.h b/target/arm/internals.h index 280b5b0c82..eafcd326e1 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -820,8 +820,8 @@ static inline bool regime_is_secure(CPUARMState *env, A= RMMMUIdx mmu_idx) case ARMMMUIdx_MUser: return false; case ARMMMUIdx_S1E3: - case ARMMMUIdx_S1SE0: - case ARMMMUIdx_S1SE1: + case ARMMMUIdx_SE10_0: + case ARMMMUIdx_SE10_1: case ARMMMUIdx_MSPrivNegPri: case ARMMMUIdx_MSUserNegPri: case ARMMMUIdx_MSPriv: diff --git a/target/arm/translate.h b/target/arm/translate.h index b837b7fcbf..a32b6b1b3a 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -126,7 +126,7 @@ static inline int default_exception_el(DisasContext *s) * exceptions can only be routed to ELs above 1, so we target the high= er of * 1 or the current EL. */ - return (s->mmu_idx =3D=3D ARMMMUIdx_S1SE0 && s->secure_routed_to_el3) + return (s->mmu_idx =3D=3D ARMMMUIdx_SE10_0 && s->secure_routed_to_el3) ? 3 : MAX(1, s->current_el); } =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index 2d87c3a2e5..bbceb7a38e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3193,7 +3193,7 @@ static void ats_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) mmu_idx =3D ARMMMUIdx_Stage1_E1; break; case 1: - mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_Stage1_E1; + mmu_idx =3D secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_Stage1_E1; break; default: g_assert_not_reached(); @@ -3203,13 +3203,13 @@ static void ats_write(CPUARMState *env, const ARMCP= RegInfo *ri, uint64_t value) /* stage 1 current state PL0: ATS1CUR, ATS1CUW */ switch (el) { case 3: - mmu_idx =3D ARMMMUIdx_S1SE0; + mmu_idx =3D ARMMMUIdx_SE10_0; break; case 2: mmu_idx =3D ARMMMUIdx_Stage1_E0; break; case 1: - mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_Stage1_E0; + mmu_idx =3D secure ? ARMMMUIdx_SE10_0 : ARMMMUIdx_Stage1_E0; break; default: g_assert_not_reached(); @@ -3263,7 +3263,7 @@ static void ats_write64(CPUARMState *env, const ARMCP= RegInfo *ri, case 0: switch (ri->opc1) { case 0: /* AT S1E1R, AT S1E1W */ - mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_Stage1_E1; + mmu_idx =3D secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_Stage1_E1; break; case 4: /* AT S1E2R, AT S1E2W */ mmu_idx =3D ARMMMUIdx_S1E2; @@ -3276,13 +3276,13 @@ static void ats_write64(CPUARMState *env, const ARM= CPRegInfo *ri, } break; case 2: /* AT S1E0R, AT S1E0W */ - mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_Stage1_E0; + mmu_idx =3D secure ? ARMMMUIdx_SE10_0 : ARMMMUIdx_Stage1_E0; break; case 4: /* AT S12E1R, AT S12E1W */ - mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_E10_1; + mmu_idx =3D secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_E10_1; break; case 6: /* AT S12E0R, AT S12E0W */ - mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_E10_0; + mmu_idx =3D secure ? ARMMMUIdx_SE10_0 : ARMMMUIdx_E10_0; break; default: g_assert_not_reached(); @@ -3945,7 +3945,7 @@ static CPAccessResult aa64_cacheop_access(CPUARMState= *env, static int vae1_tlbmask(CPUARMState *env) { if (arm_is_secure_below_el3(env)) { - return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0; + return ARMMMUIdxBit_SE10_1 | ARMMMUIdxBit_SE10_0; } else { return ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_0; } @@ -3981,7 +3981,7 @@ static int alle1_tlbmask(CPUARMState *env) * stage 1 translations. */ if (arm_is_secure_below_el3(env)) { - return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0; + return ARMMMUIdxBit_SE10_1 | ARMMMUIdxBit_SE10_0; } else if (arm_feature(env, ARM_FEATURE_EL2)) { return ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_0 | ARMMMUIdxBit_Stag= e2; } else { @@ -8715,9 +8715,9 @@ static inline uint32_t regime_el(CPUARMState *env, AR= MMMUIdx mmu_idx) return 2; case ARMMMUIdx_S1E3: return 3; - case ARMMMUIdx_S1SE0: + case ARMMMUIdx_SE10_0: return arm_el_is_aa64(env, 3) ? 1 : 3; - case ARMMMUIdx_S1SE1: + case ARMMMUIdx_SE10_1: case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_MPrivNegPri: @@ -8856,7 +8856,7 @@ bool arm_s1_regime_using_lpae_format(CPUARMState *env= , ARMMMUIdx mmu_idx) static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) { switch (mmu_idx) { - case ARMMMUIdx_S1SE0: + case ARMMMUIdx_SE10_0: case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_MUser: case ARMMMUIdx_MSUser: @@ -11296,7 +11296,7 @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el) } =20 if (el < 2 && arm_is_secure_below_el3(env)) { - return ARMMMUIdx_S1SE0 + el; + return ARMMMUIdx_SE10_0 + el; } else { return ARMMMUIdx_E10_0 + el; } diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index d0d13e2175..fcfb96ce1f 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -116,8 +116,8 @@ static inline int get_a64_user_mem_index(DisasContext *= s) case ARMMMUIdx_E10_1: useridx =3D ARMMMUIdx_E10_0; break; - case ARMMMUIdx_S1SE1: - useridx =3D ARMMMUIdx_S1SE0; + case ARMMMUIdx_SE10_1: + useridx =3D ARMMMUIdx_SE10_0; break; case ARMMMUIdx_Stage2: g_assert_not_reached(); diff --git a/target/arm/translate.c b/target/arm/translate.c index 70b1fd3fe2..a2019a9b2a 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -157,9 +157,9 @@ static inline int get_a32_user_mem_index(DisasContext *= s) case ARMMMUIdx_E10_1: return arm_to_core_mmu_idx(ARMMMUIdx_E10_0); case ARMMMUIdx_S1E3: - case ARMMMUIdx_S1SE0: - case ARMMMUIdx_S1SE1: - return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0); + case ARMMMUIdx_SE10_0: + case ARMMMUIdx_SE10_1: + return arm_to_core_mmu_idx(ARMMMUIdx_SE10_0); case ARMMMUIdx_MUser: case ARMMMUIdx_MPriv: return arm_to_core_mmu_idx(ARMMMUIdx_MUser); --=20 2.20.1 From nobody Mon Feb 9 12:19:52 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 158058587055514.14245959853497; Sat, 1 Feb 2020 11:37:50 -0800 (PST) Received: from localhost ([::1]:49410 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixyaT-0002X1-FY for importer@patchew.org; Sat, 01 Feb 2020 14:37:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58664) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixySW-0007NH-KO for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:37 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ixySV-0006kL-3y for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:36 -0500 Received: from mail-pj1-x1044.google.com ([2607:f8b0:4864:20::1044]:38992) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ixySU-0006k9-U9 for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:35 -0500 Received: by mail-pj1-x1044.google.com with SMTP id e9so4542689pjr.4 for ; Sat, 01 Feb 2020 11:29:34 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id l7sm3668509pga.27.2020.02.01.11.29.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Feb 2020 11:29:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hoJvzrX4f+0BJ6bLY7sMhUFjMJd/sGp1cni6mPQQjaA=; b=hnove9da/6OC8gH/xfeQD1V34x2EiZX3yku01mY7fjDUWPOV8h2W9ffHIc6jg6hQff AfxusK0w1esPxl4Q/BNgdA9g0WUaN2geiWJTjyEZ3E4lJo0uYn6Vo4cIX/gy4R9N0KHG +y4UAl7gTed1z/11uFX2LhnVYhPaUvzVRjbRDwhjedvSbyAwIewFqRFnimmQkP8iUyqH 7sCc+OLHsjAl1MrWiDNlmI2i4aqWjdIcWARSgtm+8gUOcYLZQmg8OwNCu6k11hNMOPTD t17+NXla2OgpiB+3FwFXQ9jhxRD52C2DkUsVrHhkD4OnUclmphXyvUsXrGCktFGwwtlg l/9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hoJvzrX4f+0BJ6bLY7sMhUFjMJd/sGp1cni6mPQQjaA=; b=jXF8Agr9NYQNsa88m/8rr/jRpueUTLOVFT2xkjwZ6xR1yWPnmSTF/e5RbX/oXrG0LN I7n5hQYGe6F6XOl2myuJn2YP91BpJPhv7EmSo8CCpw+nXnuONGFV+pe6Be3p89QXmthQ 8qIv/m5lHQ5b+b9255Pyn1fHkXf5DK0OXUmDaasXB2GP8xr2BZ2k+szpJ4PNTxKR8zH6 AYNUZ/4KmgOKZMREQrb55EnaSdw62pKFvgG4TmA8k6Wwnqj8emD4tB+eUFWSIZ1D/4SD qvClWC3t1HMM96GRwCucf783TfCx27dJHk/l3i9Glm+53jlkT+hSgXBjLLQS2jvAkdC6 8+2g== X-Gm-Message-State: APjAAAVQxWSw7yPS8CmBraKibt9gxvyIFWBVtMRf3xyGwhL1HQw5CN2I gO7A7B5O3hEtsLWUgyDdsZ7Wa8qmYeE= X-Google-Smtp-Source: APXvYqzyuSOzVpUvNx2dRgPQF9V09sdgwuOBFohc8f6qBSXL9l/WLLRj/CKg5m9oqL27hQ0x+Gz+fQ== X-Received: by 2002:a17:90a:5801:: with SMTP id h1mr7282315pji.121.1580585373712; Sat, 01 Feb 2020 11:29:33 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 13/41] target/arm: Rename ARMMMUIdx*_S1E3 to ARMMMUIdx*_SE3 Date: Sat, 1 Feb 2020 11:28:48 -0800 Message-Id: <20200201192916.31796-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200201192916.31796-1-richard.henderson@linaro.org> References: <20200201192916.31796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1044 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) This is part of a reorganization to the set of mmu_idx. The EL3 regime only has a single stage translation, and is always secure. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- target/arm/cpu.h | 4 ++-- target/arm/internals.h | 2 +- target/arm/helper.c | 14 +++++++------- target/arm/translate.c | 2 +- 4 files changed, 11 insertions(+), 11 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 6cf2b3d6fd..9f01ec8dd2 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2908,7 +2908,7 @@ typedef enum ARMMMUIdx { ARMMMUIdx_E10_0 =3D 0 | ARM_MMU_IDX_A, ARMMMUIdx_E10_1 =3D 1 | ARM_MMU_IDX_A, ARMMMUIdx_S1E2 =3D 2 | ARM_MMU_IDX_A, - ARMMMUIdx_S1E3 =3D 3 | ARM_MMU_IDX_A, + ARMMMUIdx_SE3 =3D 3 | ARM_MMU_IDX_A, ARMMMUIdx_SE10_0 =3D 4 | ARM_MMU_IDX_A, ARMMMUIdx_SE10_1 =3D 5 | ARM_MMU_IDX_A, ARMMMUIdx_Stage2 =3D 6 | ARM_MMU_IDX_A, @@ -2934,7 +2934,7 @@ typedef enum ARMMMUIdxBit { ARMMMUIdxBit_E10_0 =3D 1 << 0, ARMMMUIdxBit_E10_1 =3D 1 << 1, ARMMMUIdxBit_S1E2 =3D 1 << 2, - ARMMMUIdxBit_S1E3 =3D 1 << 3, + ARMMMUIdxBit_SE3 =3D 1 << 3, ARMMMUIdxBit_SE10_0 =3D 1 << 4, ARMMMUIdxBit_SE10_1 =3D 1 << 5, ARMMMUIdxBit_Stage2 =3D 1 << 6, diff --git a/target/arm/internals.h b/target/arm/internals.h index eafcd326e1..d8730fbbad 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -819,7 +819,7 @@ static inline bool regime_is_secure(CPUARMState *env, A= RMMMUIdx mmu_idx) case ARMMMUIdx_MPriv: case ARMMMUIdx_MUser: return false; - case ARMMMUIdx_S1E3: + case ARMMMUIdx_SE3: case ARMMMUIdx_SE10_0: case ARMMMUIdx_SE10_1: case ARMMMUIdx_MSPrivNegPri: diff --git a/target/arm/helper.c b/target/arm/helper.c index bbceb7a38e..f5d97da1c4 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3187,7 +3187,7 @@ static void ats_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) /* stage 1 current state PL1: ATS1CPR, ATS1CPW */ switch (el) { case 3: - mmu_idx =3D ARMMMUIdx_S1E3; + mmu_idx =3D ARMMMUIdx_SE3; break; case 2: mmu_idx =3D ARMMMUIdx_Stage1_E1; @@ -3269,7 +3269,7 @@ static void ats_write64(CPUARMState *env, const ARMCP= RegInfo *ri, mmu_idx =3D ARMMMUIdx_S1E2; break; case 6: /* AT S1E3R, AT S1E3W */ - mmu_idx =3D ARMMMUIdx_S1E3; + mmu_idx =3D ARMMMUIdx_SE3; break; default: g_assert_not_reached(); @@ -4013,7 +4013,7 @@ static void tlbi_aa64_alle3_write(CPUARMState *env, c= onst ARMCPRegInfo *ri, ARMCPU *cpu =3D env_archcpu(env); CPUState *cs =3D CPU(cpu); =20 - tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E3); + tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_SE3); } =20 static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *= ri, @@ -4038,7 +4038,7 @@ static void tlbi_aa64_alle3is_write(CPUARMState *env,= const ARMCPRegInfo *ri, { CPUState *cs =3D env_cpu(env); =20 - tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E3); + tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_SE3); } =20 static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -4066,7 +4066,7 @@ static void tlbi_aa64_vae3_write(CPUARMState *env, co= nst ARMCPRegInfo *ri, CPUState *cs =3D CPU(cpu); uint64_t pageaddr =3D sextract64(value << 12, 0, 56); =20 - tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E3); + tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_SE3); } =20 static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *r= i, @@ -4115,7 +4115,7 @@ static void tlbi_aa64_vae3is_write(CPUARMState *env, = const ARMCPRegInfo *ri, uint64_t pageaddr =3D sextract64(value << 12, 0, 56); =20 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, - ARMMMUIdxBit_S1E3); + ARMMMUIdxBit_SE3); } =20 static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *= ri, @@ -8713,7 +8713,7 @@ static inline uint32_t regime_el(CPUARMState *env, AR= MMMUIdx mmu_idx) case ARMMMUIdx_Stage2: case ARMMMUIdx_S1E2: return 2; - case ARMMMUIdx_S1E3: + case ARMMMUIdx_SE3: return 3; case ARMMMUIdx_SE10_0: return arm_el_is_aa64(env, 3) ? 1 : 3; diff --git a/target/arm/translate.c b/target/arm/translate.c index a2019a9b2a..75afcb03fb 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -156,7 +156,7 @@ static inline int get_a32_user_mem_index(DisasContext *= s) case ARMMMUIdx_E10_0: case ARMMMUIdx_E10_1: return arm_to_core_mmu_idx(ARMMMUIdx_E10_0); - case ARMMMUIdx_S1E3: + case ARMMMUIdx_SE3: case ARMMMUIdx_SE10_0: case ARMMMUIdx_SE10_1: return arm_to_core_mmu_idx(ARMMMUIdx_SE10_0); --=20 2.20.1 From nobody Mon Feb 9 12:19:52 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580585972008181.82847683163038; Sat, 1 Feb 2020 11:39:32 -0800 (PST) Received: from localhost ([::1]:49460 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixyc6-0005ub-W8 for importer@patchew.org; Sat, 01 Feb 2020 14:39:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58677) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixySX-0007Q8-R1 for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:39 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ixySW-0006l0-9g for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:37 -0500 Received: from mail-pl1-x643.google.com ([2607:f8b0:4864:20::643]:44864) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ixySW-0006ki-3W for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:36 -0500 Received: by mail-pl1-x643.google.com with SMTP id d9so4169174plo.11 for ; Sat, 01 Feb 2020 11:29:36 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id l7sm3668509pga.27.2020.02.01.11.29.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Feb 2020 11:29:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=O8mTB5ZTLlAyiYG1CKhwXybQCakJA5O2a1F6H3vw4Co=; b=uWK1zYQ1gXhPqoBy7gQaYh8haWq0glTiSEJ/Sq1jZ2NRu1Fx5e+0jXR7OU/M9eQmaS EWxAranXSonEhZx411kEpDgPdpkSoxhoE6aMgQ7U+dW/PngDt/JQUUHsxY4B5bu4V9eg uox7op3sGzdu9ohGO8/hirBsxYdI/wPnb4TFSIKDHBAL2T8ZvqgFqJIxzMN0CAAaXh61 9DwmpVUhvcfekYLplRfDwmSBSXQyrjgXPB6H11ppuZSe5nBbapZZKCvUams3d1dxhg0p tGL0Yd41aIlAR96JyU8h4+aHZOWwYrRftpYeuJmrkCJyPKkZqtf6g1BwhOFS6ahaBv9n b4TQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=O8mTB5ZTLlAyiYG1CKhwXybQCakJA5O2a1F6H3vw4Co=; b=nETU5TRTLyWHQSJVe1OrKA5KRnngJszqe4WES9bL9ORSDIThfOHinpu/niGqTF86Ep 3R8H8RF7l0SA59VRZBN0hOO3XcFpdFpQfAnPwXFtxjW/PBsVarBX0ToNYLc9FtjgKTCo KMIpef2tGM506/bbR68Ba0Qr8gMTmrF3nIt1PQqlF+XQGiyihH/Xo+rdIF87sxdbWVXv VNminPW0b1atO4MFcW/gmZM7FIgbEWksLCmy5K3/uwytShtGEImlVqcIwvSWYXtuOLu4 NqYXCQXUW72ucaTQpR6uSLrPyeFG7G8h69osggMvvCN/VVARsNkOx3fYogLBvcnKxAgG pmkQ== X-Gm-Message-State: APjAAAWgOZmwGSpOvmROsXyZusxe3ZOn0mn4e0n+6IaOAGZaIF4Uvlv2 IV4uMw9wQDIRe0dkcqvUkbK4c7HVTmk= X-Google-Smtp-Source: APXvYqzs1rhY9YPBskyISpl4uA3Er8suajrIUs7ox6Xt8P9oXLVPZeDAoUDoLUaI1SkQir8iw0oxnw== X-Received: by 2002:a17:90a:c20d:: with SMTP id e13mr19965136pjt.95.1580585374835; Sat, 01 Feb 2020 11:29:34 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 14/41] target/arm: Rename ARMMMUIdx_S1E2 to ARMMMUIdx_E2 Date: Sat, 1 Feb 2020 11:28:49 -0800 Message-Id: <20200201192916.31796-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200201192916.31796-1-richard.henderson@linaro.org> References: <20200201192916.31796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) This is part of a reorganization to the set of mmu_idx. The non-secure EL2 regime only has a single stage translation; there is no point in pointing out that the idx is for stage1. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- target/arm/cpu.h | 4 ++-- target/arm/internals.h | 2 +- target/arm/helper.c | 22 +++++++++++----------- target/arm/translate.c | 2 +- 4 files changed, 15 insertions(+), 15 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 9f01ec8dd2..a188398b03 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2907,7 +2907,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, un= signed int excp_idx, typedef enum ARMMMUIdx { ARMMMUIdx_E10_0 =3D 0 | ARM_MMU_IDX_A, ARMMMUIdx_E10_1 =3D 1 | ARM_MMU_IDX_A, - ARMMMUIdx_S1E2 =3D 2 | ARM_MMU_IDX_A, + ARMMMUIdx_E2 =3D 2 | ARM_MMU_IDX_A, ARMMMUIdx_SE3 =3D 3 | ARM_MMU_IDX_A, ARMMMUIdx_SE10_0 =3D 4 | ARM_MMU_IDX_A, ARMMMUIdx_SE10_1 =3D 5 | ARM_MMU_IDX_A, @@ -2933,7 +2933,7 @@ typedef enum ARMMMUIdx { typedef enum ARMMMUIdxBit { ARMMMUIdxBit_E10_0 =3D 1 << 0, ARMMMUIdxBit_E10_1 =3D 1 << 1, - ARMMMUIdxBit_S1E2 =3D 1 << 2, + ARMMMUIdxBit_E2 =3D 1 << 2, ARMMMUIdxBit_SE3 =3D 1 << 3, ARMMMUIdxBit_SE10_0 =3D 1 << 4, ARMMMUIdxBit_SE10_1 =3D 1 << 5, diff --git a/target/arm/internals.h b/target/arm/internals.h index d8730fbbad..5b8b9c233f 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -812,7 +812,7 @@ static inline bool regime_is_secure(CPUARMState *env, A= RMMMUIdx mmu_idx) case ARMMMUIdx_E10_1: case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_Stage1_E1: - case ARMMMUIdx_S1E2: + case ARMMMUIdx_E2: case ARMMMUIdx_Stage2: case ARMMMUIdx_MPrivNegPri: case ARMMMUIdx_MUserNegPri: diff --git a/target/arm/helper.c b/target/arm/helper.c index f5d97da1c4..7ee4197456 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -728,7 +728,7 @@ static void tlbiall_hyp_write(CPUARMState *env, const A= RMCPRegInfo *ri, { CPUState *cs =3D env_cpu(env); =20 - tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E2); + tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E2); } =20 static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -736,7 +736,7 @@ static void tlbiall_hyp_is_write(CPUARMState *env, cons= t ARMCPRegInfo *ri, { CPUState *cs =3D env_cpu(env); =20 - tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E2); + tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E2); } =20 static void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -745,7 +745,7 @@ static void tlbimva_hyp_write(CPUARMState *env, const A= RMCPRegInfo *ri, CPUState *cs =3D env_cpu(env); uint64_t pageaddr =3D value & ~MAKE_64BIT_MASK(0, 12); =20 - tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E2); + tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E2); } =20 static void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -755,7 +755,7 @@ static void tlbimva_hyp_is_write(CPUARMState *env, cons= t ARMCPRegInfo *ri, uint64_t pageaddr =3D value & ~MAKE_64BIT_MASK(0, 12); =20 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, - ARMMMUIdxBit_S1E2); + ARMMMUIdxBit_E2); } =20 static const ARMCPRegInfo cp_reginfo[] =3D { @@ -3238,7 +3238,7 @@ static void ats1h_write(CPUARMState *env, const ARMCP= RegInfo *ri, MMUAccessType access_type =3D ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA= _LOAD; uint64_t par64; =20 - par64 =3D do_ats_write(env, value, access_type, ARMMMUIdx_S1E2); + par64 =3D do_ats_write(env, value, access_type, ARMMMUIdx_E2); =20 A32_BANKED_CURRENT_REG_SET(env, par, par64); } @@ -3266,7 +3266,7 @@ static void ats_write64(CPUARMState *env, const ARMCP= RegInfo *ri, mmu_idx =3D secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_Stage1_E1; break; case 4: /* AT S1E2R, AT S1E2W */ - mmu_idx =3D ARMMMUIdx_S1E2; + mmu_idx =3D ARMMMUIdx_E2; break; case 6: /* AT S1E3R, AT S1E3W */ mmu_idx =3D ARMMMUIdx_SE3; @@ -4004,7 +4004,7 @@ static void tlbi_aa64_alle2_write(CPUARMState *env, c= onst ARMCPRegInfo *ri, ARMCPU *cpu =3D env_archcpu(env); CPUState *cs =3D CPU(cpu); =20 - tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E2); + tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E2); } =20 static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -4030,7 +4030,7 @@ static void tlbi_aa64_alle2is_write(CPUARMState *env,= const ARMCPRegInfo *ri, { CPUState *cs =3D env_cpu(env); =20 - tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E2); + tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E2); } =20 static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *= ri, @@ -4052,7 +4052,7 @@ static void tlbi_aa64_vae2_write(CPUARMState *env, co= nst ARMCPRegInfo *ri, CPUState *cs =3D CPU(cpu); uint64_t pageaddr =3D sextract64(value << 12, 0, 56); =20 - tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E2); + tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E2); } =20 static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -4105,7 +4105,7 @@ static void tlbi_aa64_vae2is_write(CPUARMState *env, = const ARMCPRegInfo *ri, uint64_t pageaddr =3D sextract64(value << 12, 0, 56); =20 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, - ARMMMUIdxBit_S1E2); + ARMMMUIdxBit_E2); } =20 static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *r= i, @@ -8711,7 +8711,7 @@ static inline uint32_t regime_el(CPUARMState *env, AR= MMMUIdx mmu_idx) { switch (mmu_idx) { case ARMMMUIdx_Stage2: - case ARMMMUIdx_S1E2: + case ARMMMUIdx_E2: return 2; case ARMMMUIdx_SE3: return 3; diff --git a/target/arm/translate.c b/target/arm/translate.c index 75afcb03fb..91e2ca5515 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -152,7 +152,7 @@ static inline int get_a32_user_mem_index(DisasContext *= s) * otherwise, access as if at PL0. */ switch (s->mmu_idx) { - case ARMMMUIdx_S1E2: /* this one is UNPREDICTABLE */ + case ARMMMUIdx_E2: /* this one is UNPREDICTABLE */ case ARMMMUIdx_E10_0: case ARMMMUIdx_E10_1: return arm_to_core_mmu_idx(ARMMMUIdx_E10_0); --=20 2.20.1 From nobody Mon Feb 9 12:19:52 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580585491366577.1143882668604; Sat, 1 Feb 2020 11:31:31 -0800 (PST) Received: from localhost ([::1]:49248 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixyUM-00010R-63 for importer@patchew.org; Sat, 01 Feb 2020 14:31:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58698) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixySZ-0007Uc-TW for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:42 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ixySX-0006m4-Rx for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:39 -0500 Received: from mail-pg1-x544.google.com ([2607:f8b0:4864:20::544]:39202) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ixySX-0006lT-JE for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:37 -0500 Received: by mail-pg1-x544.google.com with SMTP id 4so5475093pgd.6 for ; Sat, 01 Feb 2020 11:29:37 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id l7sm3668509pga.27.2020.02.01.11.29.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Feb 2020 11:29:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VRz2BZKpsUWePW+fecbsms1KuCSQ+HmpLGF2AEUeLmM=; b=LeqJc+WxFFjt6Xo14m6GZv3AornVhfDoCfUa9cJo3z7vIk511x9zDyyURMNN+ZNX7U 9O/E/utoVSuhsQA/NTH+IebhFkt9s8NrNdMfQIa+rgIrdDAMLBAM3C6p4semzu5WvcEh O2bH8T17qveIHUqtpUwrJSGclUbo+ZIAGbbvbJTeVP1e9/zphkSeXzK0G6WUD5sRNWMa JHX9ulgOhPEyiX0x7sLr3KgXtiVH8G/IuedF7p9HTqoXXLLxwqk3iLPW4/MgEYDO2XD3 McVweF+PImQmZWpNAAWqd3eyJLmO07fCUpfX2Y7slY8GQkVJ+lw1CLzDR6a29TWMLVmw rQkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VRz2BZKpsUWePW+fecbsms1KuCSQ+HmpLGF2AEUeLmM=; b=XQ93E643HtJhgcR786VwFZFjyfwvD5kP4cymbsgwVplQL7p/sgHy7enC8p5IzGii/z /je3QPqu11QHsNOsACGX6lBJ3BksPu4wULrrB1Rx13JfSAaD5jopfFR5Glz0hjN4t0jP 8z3yV8SQa9HI5JXwijmVc6bvjbPmeouLbZl5DTeU52Wkzqjqk2lEDJBKB4254QX867iH yBaoMXZKNssyzXH4yTfSafpiC9wtfNH17X+163iN1i4mxV5fAr0MVB0Lrm++VpbHKY5b PBBjYroN0MkrNTxUek14/JpIA6eFu1hWE3JaHlcdMVjfcuP12RgA9FzvyacdZxVb1pQP MCzA== X-Gm-Message-State: APjAAAUCGO9MXR+hRsf7cbnYTZFmvZlIcghdO+BVAJaSQBRIcIyCR+Mj TQ3kBISPexWug0TwDVPBG11m+r+T7RE= X-Google-Smtp-Source: APXvYqyys57UzAj0yInqqNnCjP0o9dQQeOpDeoh9pU+omgk+RpXBpe1+VZqNhz4nznyfm7iW5wiKkg== X-Received: by 2002:a63:78cf:: with SMTP id t198mr16434853pgc.287.1580585376073; Sat, 01 Feb 2020 11:29:36 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 15/41] target/arm: Recover 4 bits from TBFLAGs Date: Sat, 1 Feb 2020 11:28:50 -0800 Message-Id: <20200201192916.31796-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200201192916.31796-1-richard.henderson@linaro.org> References: <20200201192916.31796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) We had completely run out of TBFLAG bits. Split A- and M-profile bits into two overlapping buckets. This results in 4 free bits. We used to initialize all of the a32 and m32 fields in DisasContext by assignment, in arm_tr_init_disas_context. Now we only initialize either the a32 or m32 by assignment, because the bits overlap in tbflags. So zero the entire structure in gen_intermediate_code. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- target/arm/cpu.h | 68 ++++++++++++++++++++++++++---------------- target/arm/helper.c | 17 +++++------ target/arm/translate.c | 57 +++++++++++++++++++---------------- 3 files changed, 82 insertions(+), 60 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a188398b03..fce6a426c8 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3214,6 +3214,16 @@ typedef ARMCPU ArchCPU; * We put flags which are shared between 32 and 64 bit mode at the top * of the word, and flags which apply to only one mode at the bottom. * + * 31 21 18 14 9 0 + * +--------------+-----+-----+----------+--------------+ + * | | | TBFLAG_A32 | | + * | | +-----+----------+ TBFLAG_AM32 | + * | TBFLAG_ANY | |TBFLAG_M32| | + * | | +-------------------------| + * | | | TBFLAG_A64 | + * +--------------+-----------+-------------------------+ + * 31 21 14 0 + * * Unless otherwise noted, these bits are cached in env->hflags. */ FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1) @@ -3223,46 +3233,54 @@ FIELD(TBFLAG_ANY, PSTATE_SS, 26, 1) /* Not cach= ed. */ /* Target EL if we take a floating-point-disabled exception */ FIELD(TBFLAG_ANY, FPEXC_EL, 24, 2) FIELD(TBFLAG_ANY, BE_DATA, 23, 1) -/* - * For A-profile only, target EL for debug exceptions. - * Note that this overlaps with the M-profile-only HANDLER and STACKCHECK = bits. - */ +/* For A-profile only, target EL for debug exceptions. */ FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 21, 2) =20 -/* Bit usage when in AArch32 state: */ -FIELD(TBFLAG_A32, THUMB, 0, 1) /* Not cached. */ -FIELD(TBFLAG_A32, VECLEN, 1, 3) /* Not cached. */ -FIELD(TBFLAG_A32, VECSTRIDE, 4, 2) /* Not cached. */ +/* + * Bit usage when in AArch32 state, both A- and M-profile. + */ +FIELD(TBFLAG_AM32, CONDEXEC, 0, 8) /* Not cached. */ +FIELD(TBFLAG_AM32, THUMB, 8, 1) /* Not cached. */ + +/* + * Bit usage when in AArch32 state, for A-profile only. + */ +FIELD(TBFLAG_A32, VECLEN, 9, 3) /* Not cached. */ +FIELD(TBFLAG_A32, VECSTRIDE, 12, 2) /* Not cached. */ /* * We store the bottom two bits of the CPAR as TB flags and handle * checks on the other bits at runtime. This shares the same bits as * VECSTRIDE, which is OK as no XScale CPU has VFP. * Not cached, because VECLEN+VECSTRIDE are not cached. */ -FIELD(TBFLAG_A32, XSCALE_CPAR, 4, 2) +FIELD(TBFLAG_A32, XSCALE_CPAR, 12, 2) +FIELD(TBFLAG_A32, VFPEN, 14, 1) /* Partially cached, minus FPEXC. = */ +FIELD(TBFLAG_A32, SCTLR_B, 15, 1) +FIELD(TBFLAG_A32, HSTR_ACTIVE, 16, 1) /* * Indicates whether cp register reads and writes by guest code should acc= ess * the secure or nonsecure bank of banked registers; note that this is not * the same thing as the current security state of the processor! */ -FIELD(TBFLAG_A32, NS, 6, 1) -FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. = */ -FIELD(TBFLAG_A32, CONDEXEC, 8, 8) /* Not cached. */ -FIELD(TBFLAG_A32, SCTLR_B, 16, 1) -FIELD(TBFLAG_A32, HSTR_ACTIVE, 17, 1) +FIELD(TBFLAG_A32, NS, 17, 1) =20 -/* For M profile only, set if FPCCR.LSPACT is set */ -FIELD(TBFLAG_A32, LSPACT, 18, 1) /* Not cached. */ -/* For M profile only, set if we must create a new FP context */ -FIELD(TBFLAG_A32, NEW_FP_CTXT_NEEDED, 19, 1) /* Not cached. */ -/* For M profile only, set if FPCCR.S does not match current security stat= e */ -FIELD(TBFLAG_A32, FPCCR_S_WRONG, 20, 1) /* Not cached. */ -/* For M profile only, Handler (ie not Thread) mode */ -FIELD(TBFLAG_A32, HANDLER, 21, 1) -/* For M profile only, whether we should generate stack-limit checks */ -FIELD(TBFLAG_A32, STACKCHECK, 22, 1) +/* + * Bit usage when in AArch32 state, for M-profile only. + */ +/* Handler (ie not Thread) mode */ +FIELD(TBFLAG_M32, HANDLER, 9, 1) +/* Whether we should generate stack-limit checks */ +FIELD(TBFLAG_M32, STACKCHECK, 10, 1) +/* Set if FPCCR.LSPACT is set */ +FIELD(TBFLAG_M32, LSPACT, 11, 1) /* Not cached. */ +/* Set if we must create a new FP context */ +FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 12, 1) /* Not cached. */ +/* Set if FPCCR.S does not match current security state */ +FIELD(TBFLAG_M32, FPCCR_S_WRONG, 13, 1) /* Not cached. */ =20 -/* Bit usage when in AArch64 state */ +/* + * Bit usage when in AArch64 state + */ FIELD(TBFLAG_A64, TBII, 0, 2) FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) diff --git a/target/arm/helper.c b/target/arm/helper.c index 7ee4197456..5609bb18e8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11353,11 +11353,8 @@ static uint32_t rebuild_hflags_m32(CPUARMState *en= v, int fp_el, { uint32_t flags =3D 0; =20 - /* v8M always enables the fpu. */ - flags =3D FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); - if (arm_v7m_is_handler_mode(env)) { - flags =3D FIELD_DP32(flags, TBFLAG_A32, HANDLER, 1); + flags =3D FIELD_DP32(flags, TBFLAG_M32, HANDLER, 1); } =20 /* @@ -11368,7 +11365,7 @@ static uint32_t rebuild_hflags_m32(CPUARMState *env= , int fp_el, if (arm_feature(env, ARM_FEATURE_V8) && !((mmu_idx & ARM_MMU_IDX_M_NEGPRI) && (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_STKOFHFNMIGN_MASK))) { - flags =3D FIELD_DP32(flags, TBFLAG_A32, STACKCHECK, 1); + flags =3D FIELD_DP32(flags, TBFLAG_M32, STACKCHECK, 1); } =20 return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); @@ -11561,7 +11558,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_= ulong *pc, if (arm_feature(env, ARM_FEATURE_M_SECURITY) && FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S) !=3D env->v7m.secure) { - flags =3D FIELD_DP32(flags, TBFLAG_A32, FPCCR_S_WRONG, 1); + flags =3D FIELD_DP32(flags, TBFLAG_M32, FPCCR_S_WRONG, 1); } =20 if ((env->v7m.fpccr[env->v7m.secure] & R_V7M_FPCCR_ASPEN_MASK)= && @@ -11573,12 +11570,12 @@ void cpu_get_tb_cpu_state(CPUARMState *env, targe= t_ulong *pc, * active FP context; we must create a new FP context befo= re * executing any FP insn. */ - flags =3D FIELD_DP32(flags, TBFLAG_A32, NEW_FP_CTXT_NEEDED= , 1); + flags =3D FIELD_DP32(flags, TBFLAG_M32, NEW_FP_CTXT_NEEDED= , 1); } =20 bool is_secure =3D env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MAS= K; if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) { - flags =3D FIELD_DP32(flags, TBFLAG_A32, LSPACT, 1); + flags =3D FIELD_DP32(flags, TBFLAG_M32, LSPACT, 1); } } else { /* @@ -11599,8 +11596,8 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_= ulong *pc, } } =20 - flags =3D FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); - flags =3D FIELD_DP32(flags, TBFLAG_A32, CONDEXEC, env->condexec_bi= ts); + flags =3D FIELD_DP32(flags, TBFLAG_AM32, THUMB, env->thumb); + flags =3D FIELD_DP32(flags, TBFLAG_AM32, CONDEXEC, env->condexec_b= its); pstate_for_ss =3D env->uncached_cpsr; } =20 diff --git a/target/arm/translate.c b/target/arm/translate.c index 91e2ca5515..c169984374 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10848,38 +10848,48 @@ static void arm_tr_init_disas_context(DisasContex= tBase *dcbase, CPUState *cs) */ dc->secure_routed_to_el3 =3D arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3); - dc->thumb =3D FIELD_EX32(tb_flags, TBFLAG_A32, THUMB); - dc->sctlr_b =3D FIELD_EX32(tb_flags, TBFLAG_A32, SCTLR_B); - dc->hstr_active =3D FIELD_EX32(tb_flags, TBFLAG_A32, HSTR_ACTIVE); + dc->thumb =3D FIELD_EX32(tb_flags, TBFLAG_AM32, THUMB); dc->be_data =3D FIELD_EX32(tb_flags, TBFLAG_ANY, BE_DATA) ? MO_BE : MO= _LE; - condexec =3D FIELD_EX32(tb_flags, TBFLAG_A32, CONDEXEC); + condexec =3D FIELD_EX32(tb_flags, TBFLAG_AM32, CONDEXEC); dc->condexec_mask =3D (condexec & 0xf) << 1; dc->condexec_cond =3D condexec >> 4; + core_mmu_idx =3D FIELD_EX32(tb_flags, TBFLAG_ANY, MMUIDX); dc->mmu_idx =3D core_to_arm_mmu_idx(env, core_mmu_idx); dc->current_el =3D arm_mmu_idx_to_el(dc->mmu_idx); #if !defined(CONFIG_USER_ONLY) dc->user =3D (dc->current_el =3D=3D 0); #endif - dc->ns =3D FIELD_EX32(tb_flags, TBFLAG_A32, NS); dc->fp_excp_el =3D FIELD_EX32(tb_flags, TBFLAG_ANY, FPEXC_EL); - dc->vfp_enabled =3D FIELD_EX32(tb_flags, TBFLAG_A32, VFPEN); - dc->vec_len =3D FIELD_EX32(tb_flags, TBFLAG_A32, VECLEN); - if (arm_feature(env, ARM_FEATURE_XSCALE)) { - dc->c15_cpar =3D FIELD_EX32(tb_flags, TBFLAG_A32, XSCALE_CPAR); - dc->vec_stride =3D 0; + + if (arm_feature(env, ARM_FEATURE_M)) { + dc->vfp_enabled =3D 1; + dc->be_data =3D MO_TE; + dc->v7m_handler_mode =3D FIELD_EX32(tb_flags, TBFLAG_M32, HANDLER); + dc->v8m_secure =3D arm_feature(env, ARM_FEATURE_M_SECURITY) && + regime_is_secure(env, dc->mmu_idx); + dc->v8m_stackcheck =3D FIELD_EX32(tb_flags, TBFLAG_M32, STACKCHECK= ); + dc->v8m_fpccr_s_wrong =3D + FIELD_EX32(tb_flags, TBFLAG_M32, FPCCR_S_WRONG); + dc->v7m_new_fp_ctxt_needed =3D + FIELD_EX32(tb_flags, TBFLAG_M32, NEW_FP_CTXT_NEEDED); + dc->v7m_lspact =3D FIELD_EX32(tb_flags, TBFLAG_M32, LSPACT); } else { - dc->vec_stride =3D FIELD_EX32(tb_flags, TBFLAG_A32, VECSTRIDE); - dc->c15_cpar =3D 0; + dc->be_data =3D + FIELD_EX32(tb_flags, TBFLAG_ANY, BE_DATA) ? MO_BE : MO_LE; + dc->debug_target_el =3D + FIELD_EX32(tb_flags, TBFLAG_ANY, DEBUG_TARGET_EL); + dc->sctlr_b =3D FIELD_EX32(tb_flags, TBFLAG_A32, SCTLR_B); + dc->hstr_active =3D FIELD_EX32(tb_flags, TBFLAG_A32, HSTR_ACTIVE); + dc->ns =3D FIELD_EX32(tb_flags, TBFLAG_A32, NS); + dc->vfp_enabled =3D FIELD_EX32(tb_flags, TBFLAG_A32, VFPEN); + if (arm_feature(env, ARM_FEATURE_XSCALE)) { + dc->c15_cpar =3D FIELD_EX32(tb_flags, TBFLAG_A32, XSCALE_CPAR); + } else { + dc->vec_len =3D FIELD_EX32(tb_flags, TBFLAG_A32, VECLEN); + dc->vec_stride =3D FIELD_EX32(tb_flags, TBFLAG_A32, VECSTRIDE); + } } - dc->v7m_handler_mode =3D FIELD_EX32(tb_flags, TBFLAG_A32, HANDLER); - dc->v8m_secure =3D arm_feature(env, ARM_FEATURE_M_SECURITY) && - regime_is_secure(env, dc->mmu_idx); - dc->v8m_stackcheck =3D FIELD_EX32(tb_flags, TBFLAG_A32, STACKCHECK); - dc->v8m_fpccr_s_wrong =3D FIELD_EX32(tb_flags, TBFLAG_A32, FPCCR_S_WRO= NG); - dc->v7m_new_fp_ctxt_needed =3D - FIELD_EX32(tb_flags, TBFLAG_A32, NEW_FP_CTXT_NEEDED); - dc->v7m_lspact =3D FIELD_EX32(tb_flags, TBFLAG_A32, LSPACT); dc->cp_regs =3D cpu->cp_regs; dc->features =3D env->features; =20 @@ -10901,9 +10911,6 @@ static void arm_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) dc->ss_active =3D FIELD_EX32(tb_flags, TBFLAG_ANY, SS_ACTIVE); dc->pstate_ss =3D FIELD_EX32(tb_flags, TBFLAG_ANY, PSTATE_SS); dc->is_ldex =3D false; - if (!arm_feature(env, ARM_FEATURE_M)) { - dc->debug_target_el =3D FIELD_EX32(tb_flags, TBFLAG_ANY, DEBUG_TAR= GET_EL); - } =20 dc->page_start =3D dc->base.pc_first & TARGET_PAGE_MASK; =20 @@ -11340,10 +11347,10 @@ static const TranslatorOps thumb_translator_ops = =3D { /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_in= sns) { - DisasContext dc; + DisasContext dc =3D { }; const TranslatorOps *ops =3D &arm_translator_ops; =20 - if (FIELD_EX32(tb->flags, TBFLAG_A32, THUMB)) { + if (FIELD_EX32(tb->flags, TBFLAG_AM32, THUMB)) { ops =3D &thumb_translator_ops; } #ifdef TARGET_AARCH64 --=20 2.20.1 From nobody Mon Feb 9 12:19:52 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580586213807188.29215807442768; Sat, 1 Feb 2020 11:43:33 -0800 (PST) Received: from localhost ([::1]:49896 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixyg0-00049r-ND for importer@patchew.org; Sat, 01 Feb 2020 14:43:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58694) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixySZ-0007U5-Kh for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ixySY-0006ma-Kz for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:39 -0500 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:40135) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ixySY-0006mA-FW for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:38 -0500 Received: by mail-pg1-x541.google.com with SMTP id k25so5472920pgt.7 for ; Sat, 01 Feb 2020 11:29:38 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id l7sm3668509pga.27.2020.02.01.11.29.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Feb 2020 11:29:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tAUO3moP+hTFL+z2g2ynj8dsoHjP3s61tE4VX5hK15k=; b=C9OSSMFWGEv+aSsj5+cE4JNQhFKHzcssnQ/vjZaaUbfiAB1piErFrqV3EcV5o/guo8 ZL/OHi3yrmI/JNJpBJW7CJ07YTdc53l5VB9UkX1z/U/9YrbzAVes1cM1LsNz+CsCrJkK D4EqKILG3vw7qcr3qGTWHPFGvOUXnxh6uj95Kr9Q1m3m1sGIEKC/ptQOcSjTKNjPa/v2 rNuGxtveICmckOBn+Dmc8R3hYeiwJIDQlwUExwwWis6UPdfB2vTL1u/paUgs4HnxH0Go pAe2lLFjorWVspBvJtEQNXLkozJWvThsZFSU5GXBW8mZ3hA69tP92p6B6XM8+jWP2YWk aN2Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tAUO3moP+hTFL+z2g2ynj8dsoHjP3s61tE4VX5hK15k=; b=GJsXS5BJ+N5aX8ytrpmFeX+UEcQJiAVcLpHfo7GJPwfQD0Hqa8JXnUEnDfRYQ/j2K/ qZj7hmmJ/8D8DWrRmZNhhQZjPwSk0EArbuvRNX4h8qSUcBj5oHmIjuhjb0KnjnsafjmU 2qeNPtxUiHI1bMUMgakIw4BanJkH0VtJqtX8a42ANTG5K76zlhfoEiFcS2fWE6YhhxDh 0iYO4wt/9DVvcTeJKRDlPfw+z4LMikg+WgBqHQNf8q0YJFzAcR8jppXFmnYzgi6KQH3z GZj2WHF9FGeWHeYt//Cu4yMpMawmO0dI+4+WzRuxSzUr7aLzEIg4MDBnJdK2FYcyitzd e7Ow== X-Gm-Message-State: APjAAAU3a29mWzFRM9F4qCf3+mCkx12fJupomJzLx3d9n1/oHii43NNv pNledJorG1YRdhoh4kgsiyVNDOiPMrA= X-Google-Smtp-Source: APXvYqx7ryVCoWAJgjobtZq06vJ1SA2MCiomoFahBU7Bcs/Jz8zeS4M7qm6rSDVqDbIryRX6ZSAGfg== X-Received: by 2002:a63:5c10:: with SMTP id q16mr17172124pgb.35.1580585377263; Sat, 01 Feb 2020 11:29:37 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 16/41] target/arm: Expand TBFLAG_ANY.MMUIDX to 4 bits Date: Sat, 1 Feb 2020 11:28:51 -0800 Message-Id: <20200201192916.31796-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200201192916.31796-1-richard.henderson@linaro.org> References: <20200201192916.31796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) We are about to expand the number of mmuidx to 10, and so need 4 bits. For the benefit of reading the number out of -d exec, align it to the penultimate nibble. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- target/arm/cpu.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index fce6a426c8..aa9728cff6 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3214,7 +3214,7 @@ typedef ARMCPU ArchCPU; * We put flags which are shared between 32 and 64 bit mode at the top * of the word, and flags which apply to only one mode at the bottom. * - * 31 21 18 14 9 0 + * 31 20 18 14 9 0 * +--------------+-----+-----+----------+--------------+ * | | | TBFLAG_A32 | | * | | +-----+----------+ TBFLAG_AM32 | @@ -3222,19 +3222,19 @@ typedef ARMCPU ArchCPU; * | | +-------------------------| * | | | TBFLAG_A64 | * +--------------+-----------+-------------------------+ - * 31 21 14 0 + * 31 20 14 0 * * Unless otherwise noted, these bits are cached in env->hflags. */ FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1) -FIELD(TBFLAG_ANY, MMUIDX, 28, 3) -FIELD(TBFLAG_ANY, SS_ACTIVE, 27, 1) -FIELD(TBFLAG_ANY, PSTATE_SS, 26, 1) /* Not cached. */ +FIELD(TBFLAG_ANY, SS_ACTIVE, 30, 1) +FIELD(TBFLAG_ANY, PSTATE_SS, 29, 1) /* Not cached. */ +FIELD(TBFLAG_ANY, BE_DATA, 28, 1) +FIELD(TBFLAG_ANY, MMUIDX, 24, 4) /* Target EL if we take a floating-point-disabled exception */ -FIELD(TBFLAG_ANY, FPEXC_EL, 24, 2) -FIELD(TBFLAG_ANY, BE_DATA, 23, 1) +FIELD(TBFLAG_ANY, FPEXC_EL, 22, 2) /* For A-profile only, target EL for debug exceptions. */ -FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 21, 2) +FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 20, 2) =20 /* * Bit usage when in AArch32 state, both A- and M-profile. --=20 2.20.1 From nobody Mon Feb 9 12:19:52 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 158058631832871.29213905609083; Sat, 1 Feb 2020 11:45:18 -0800 (PST) Received: from localhost ([::1]:49976 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixyhh-0007Sk-3W for importer@patchew.org; Sat, 01 Feb 2020 14:45:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58708) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixySa-0007V7-R0 for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:41 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ixySZ-0006nH-MN for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:40 -0500 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:42680) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ixySZ-0006mm-G6 for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:39 -0500 Received: by mail-pg1-x543.google.com with SMTP id s64so5454303pgb.9 for ; Sat, 01 Feb 2020 11:29:39 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id l7sm3668509pga.27.2020.02.01.11.29.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Feb 2020 11:29:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zRgB8efNbAKyUVxLAqmxP7UnRJX0xqtjC+kQnc9eL3A=; b=TjhpUV38IcoklT+kDVx8Df7THMQ1ZAZHBH8D7V7t6OX/w+exsv7ZjwOF5Esd7v+YaL Fx4g7Gx5aWzySKakWeNlJHJOzdmLjlUGvsEYTy35UsyHCnDkAyaSfCoNiEX/vD1jwVXz YKz/feun0oT3C1b0oTzGdwagwOkNzBxOMC9CG6Wd6MvLTg9PdiDgo/e8OZx419pf3za8 UQdBg5KM/tC85G57tv+vw+PeouxV29bStVQk3chgFZ71gYjUc+JbuqB7w7XX44nem3oH wJZ/etaCxNQGTO/geHeuwAegG5I/Tb+oCMlvvdo/SRqFaujEY0NcsMg3O1WA5AznPa0R c9BQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zRgB8efNbAKyUVxLAqmxP7UnRJX0xqtjC+kQnc9eL3A=; b=FohNQCkaz1EwmumDryCcNrvOU9KE+rW9hWlw/SdeDoxfgoxxtoDFtVBjBYg4c8m/Gw lK6dlTraOyn2Wb73M8gl+O+d1lAYQkajhcKnFBrpraET72V/gXtv0NAybnRcHiZRSVDE NwCZnI7Pj+IMosbsq5fDC7wdzM9GDTpW+L75AHgDa9PwVdenHA8YiHw/Nmkbk5U6YTXQ ShPAfoPRoXwhFr3oSpaJ/fbTxWBB/fN7oHhbbtsFdG1uQ6UVbUxyLr8BKs+xwDplo36h EgGKETyXcCPPo3kTwjRnanMT27xSIxqKucYf4BzxAjoxDL61Z5zA+fciiSskqjYfcji0 dgQQ== X-Gm-Message-State: APjAAAV27hJWPaNtYKymMtPiHrQQTSuGNBqoXrwrhzcVhWMshNUHAFB2 es5b10m4rln3VXm8VfBIyiYAsqZnGJ0= X-Google-Smtp-Source: APXvYqyTd1wsJI9YzU+lpu3OrEm22x1rD6+PtoNwpdSL3AaB6liTXX8+G9UBM2UMOQhP9yIFHhJovg== X-Received: by 2002:a63:4503:: with SMTP id s3mr17154838pga.311.1580585378338; Sat, 01 Feb 2020 11:29:38 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 17/41] target/arm: Rearrange ARMMMUIdxBit Date: Sat, 1 Feb 2020 11:28:52 -0800 Message-Id: <20200201192916.31796-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200201192916.31796-1-richard.henderson@linaro.org> References: <20200201192916.31796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Define via macro expansion, so that renumbering of the base ARMMMUIdx symbols is automatically reflected in the bit definitions. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- target/arm/cpu.h | 39 +++++++++++++++++++++++---------------- 1 file changed, 23 insertions(+), 16 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index aa9728cff6..aa121cd9d0 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2927,27 +2927,34 @@ typedef enum ARMMMUIdx { ARMMMUIdx_Stage1_E1 =3D 1 | ARM_MMU_IDX_NOTLB, } ARMMMUIdx; =20 -/* Bit macros for the core-mmu-index values for each index, +/* + * Bit macros for the core-mmu-index values for each index, * for use when calling tlb_flush_by_mmuidx() and friends. */ +#define TO_CORE_BIT(NAME) \ + ARMMMUIdxBit_##NAME =3D 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_M= ASK) + typedef enum ARMMMUIdxBit { - ARMMMUIdxBit_E10_0 =3D 1 << 0, - ARMMMUIdxBit_E10_1 =3D 1 << 1, - ARMMMUIdxBit_E2 =3D 1 << 2, - ARMMMUIdxBit_SE3 =3D 1 << 3, - ARMMMUIdxBit_SE10_0 =3D 1 << 4, - ARMMMUIdxBit_SE10_1 =3D 1 << 5, - ARMMMUIdxBit_Stage2 =3D 1 << 6, - ARMMMUIdxBit_MUser =3D 1 << 0, - ARMMMUIdxBit_MPriv =3D 1 << 1, - ARMMMUIdxBit_MUserNegPri =3D 1 << 2, - ARMMMUIdxBit_MPrivNegPri =3D 1 << 3, - ARMMMUIdxBit_MSUser =3D 1 << 4, - ARMMMUIdxBit_MSPriv =3D 1 << 5, - ARMMMUIdxBit_MSUserNegPri =3D 1 << 6, - ARMMMUIdxBit_MSPrivNegPri =3D 1 << 7, + TO_CORE_BIT(E10_0), + TO_CORE_BIT(E10_1), + TO_CORE_BIT(E2), + TO_CORE_BIT(SE10_0), + TO_CORE_BIT(SE10_1), + TO_CORE_BIT(SE3), + TO_CORE_BIT(Stage2), + + TO_CORE_BIT(MUser), + TO_CORE_BIT(MPriv), + TO_CORE_BIT(MUserNegPri), + TO_CORE_BIT(MPrivNegPri), + TO_CORE_BIT(MSUser), + TO_CORE_BIT(MSPriv), + TO_CORE_BIT(MSUserNegPri), + TO_CORE_BIT(MSPrivNegPri), } ARMMMUIdxBit; =20 +#undef TO_CORE_BIT + #define MMU_USER_IDX 0 =20 static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx) --=20 2.20.1 From nobody Mon Feb 9 12:19:52 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580585659061908.9361909436336; Sat, 1 Feb 2020 11:34:19 -0800 (PST) Received: from localhost ([::1]:49302 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixyX3-0004TL-SB for importer@patchew.org; Sat, 01 Feb 2020 14:34:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58726) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixySd-0007Zk-93 for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ixySa-0006o5-Ur for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:43 -0500 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]:36603) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ixySa-0006nZ-Ph for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:40 -0500 Received: by mail-pg1-x542.google.com with SMTP id k3so5486125pgc.3 for ; Sat, 01 Feb 2020 11:29:40 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id l7sm3668509pga.27.2020.02.01.11.29.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Feb 2020 11:29:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZmLVKq5ZCR+ymmuOiYYpLo/dLKBJqCs80mPJBtIPf/g=; b=Qtb1YiIL7xV1wTeQvk6PsfbH2NCOGI6S9ZW0BI2Z7zPrFatoYfdhhMl+kZU0Dkeq4B 4GScZmf7JwkWMzVniCxJJc3LtviZJIM7ORT8KpWT7kWPI7HeHXe1hU7fJ4q7rYhdmIW8 rK3AiKUYBylRqkHKJl7VFrGVjgvPwp8MTC/44327wYuQ30/0QDIIqLoca0GTwvAAhSTy wn0TfGBc0QKvhVq/dArEf+xEZqWtNgf96YFRO1X3+OsUbfANi7O4bP3kT9U62l64LRtU Muu1nwq088UnBMlpWX0UYrNEWhtd/OIAOo7FbwF01AYi5yRN27OwOWubcDEQUP9x+PZl uQhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZmLVKq5ZCR+ymmuOiYYpLo/dLKBJqCs80mPJBtIPf/g=; b=FBCbLkGP367vHr/AiusqqZQZb0D1bPzDSBW75v1MNf2eQLZK0esJPkfcCrDs8ebtJw /wlcOttajRFztYqZ2eEQpNWV4UiAPbPJQTZoIKJPuYCQ5K+0mCAbfAThKrPhe1JGMhK4 0aVjGTrz+PMVoFrzmMVCvfyxK8oyG5JGJFvuCjDO4Xmi183Zr9pTlqKLnAjdMiBm3PST yLVQtCIjBuwDBh3qrAHhISw5yFwLvVLaIdBCqDdq1cKHLf1f4NtGwT3+L82uKlKJTQ9v 7WYm3B5FGBRuthpA2jfxVA20ywcqGaT7UMIQTOdlL6YDdVnTuu1VfMt1iXjhmQfsTD7u zr6g== X-Gm-Message-State: APjAAAXRR79jlqPi4B948sA3wmYTZ3+y8qQHFonW1eZibMN0dQxaKVFY YbT/BSkW7pRKeNV9Qdj9fIa3GhiGa2g= X-Google-Smtp-Source: APXvYqyJi8oxI62qCXSFxOMrnBMaXbcLO/saFJC0Ev+Rr+iPTAB3LI/oqbzbkB7aYeqKlfcwaGWZYg== X-Received: by 2002:a63:691:: with SMTP id 139mr1535022pgg.325.1580585379363; Sat, 01 Feb 2020 11:29:39 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 18/41] target/arm: Tidy ARMMMUIdx m-profile definitions Date: Sat, 1 Feb 2020 11:28:53 -0800 Message-Id: <20200201192916.31796-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200201192916.31796-1-richard.henderson@linaro.org> References: <20200201192916.31796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Replace the magic numbers with the relevant ARM_MMU_IDX_M_* constants. Keep the definitions short by referencing previous symbols. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- target/arm/cpu.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index aa121cd9d0..ad92873943 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2912,14 +2912,14 @@ typedef enum ARMMMUIdx { ARMMMUIdx_SE10_0 =3D 4 | ARM_MMU_IDX_A, ARMMMUIdx_SE10_1 =3D 5 | ARM_MMU_IDX_A, ARMMMUIdx_Stage2 =3D 6 | ARM_MMU_IDX_A, - ARMMMUIdx_MUser =3D 0 | ARM_MMU_IDX_M, - ARMMMUIdx_MPriv =3D 1 | ARM_MMU_IDX_M, - ARMMMUIdx_MUserNegPri =3D 2 | ARM_MMU_IDX_M, - ARMMMUIdx_MPrivNegPri =3D 3 | ARM_MMU_IDX_M, - ARMMMUIdx_MSUser =3D 4 | ARM_MMU_IDX_M, - ARMMMUIdx_MSPriv =3D 5 | ARM_MMU_IDX_M, - ARMMMUIdx_MSUserNegPri =3D 6 | ARM_MMU_IDX_M, - ARMMMUIdx_MSPrivNegPri =3D 7 | ARM_MMU_IDX_M, + ARMMMUIdx_MUser =3D ARM_MMU_IDX_M, + ARMMMUIdx_MPriv =3D ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV, + ARMMMUIdx_MUserNegPri =3D ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI, + ARMMMUIdx_MPrivNegPri =3D ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI, + ARMMMUIdx_MSUser =3D ARMMMUIdx_MUser | ARM_MMU_IDX_M_S, + ARMMMUIdx_MSPriv =3D ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S, + ARMMMUIdx_MSUserNegPri =3D ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S, + ARMMMUIdx_MSPrivNegPri =3D ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S, /* Indexes below here don't have TLBs and are used only for AT system * instructions or for the first stage of an S12 page table walk. */ --=20 2.20.1 From nobody Mon Feb 9 12:19:52 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580586108948107.95338182217449; Sat, 1 Feb 2020 11:41:48 -0800 (PST) Received: from localhost ([::1]:49614 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixyeJ-0000a1-Hg for importer@patchew.org; Sat, 01 Feb 2020 14:41:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58758) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixySf-0007ar-NX for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ixySd-0006pm-EP for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:45 -0500 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:43085) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ixySd-0006oO-5h for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:43 -0500 Received: by mail-pf1-x444.google.com with SMTP id s1so5255913pfh.10 for ; Sat, 01 Feb 2020 11:29:41 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id l7sm3668509pga.27.2020.02.01.11.29.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Feb 2020 11:29:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4eKOhQhI9UAZGAmBZgdAnv0eVhna38d5sXtKVrZb6rY=; b=RE/ZIsmPxd9pPlF0t9jEWQ12riiHFu8hxXveOFO7aRzTXBh2qsNlGm3ndL3IqjlGWr P6j3Qx4+pxUU0heV3sl/T1sK/ADdbyaesSw9QrruB8Z0MDcjflEPhvKxO4leEMPU/KoM BCGhuzXLQYOLSSXU4Zk53YljjQrngOjA+xSS6dPFhueVacxc/LmnA9geKx9RAD5NfGSP wvfXwxJcCx/8KzW/4nI3xfx+W6/VqOfgZrSd8JCxLvHUSxEqRu1ls/OKnD5Iu5UpKgKb tXAQD0l+vY2FK2fr2XcjdzsxpOHbSo9bkpUTcx5pJo1DmaOA6Eh2XW3e2p3YgsufBzqS NjwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4eKOhQhI9UAZGAmBZgdAnv0eVhna38d5sXtKVrZb6rY=; b=Tf+BkF4sovYxekL7x3Zce1u8HIXnFUmkyEpTmTIDXh0PX93kDseX0GvCOtfkB9mxC7 cQT7zST5K0UdXN8OnhOBoV5M8hu/vOm/sRPCEOAI2R7Pu0rmtci2Nv93QYC+tl3rYkED DT+qZ0e5Enh9FAj8LUYf5d2taASPhAuku+MikKjTzEhofBYnF5fGjg9vO8JpboV1iWDg C6PvUlU8kpB40xKxceR5Zip0mda5bY6HpA746Kg66qzEFQOwL2cIEo0LTOH9fENa4k49 fQ4/q32FYIUIVxiDSsdNLsx6ZFW9r8tvsZRHYkbNSFL4Cf/JDdprTWzt6Yu00H67NyE5 diqA== X-Gm-Message-State: APjAAAXmjNjUE713JAIo5GFv8QifvEayz17OAF9GBgSpG9eA0r0IfehR WWg2u6yVXgyC440G6QLkvwiJVaczMM8= X-Google-Smtp-Source: APXvYqwRzNRAII9NK0PhAARKAdORpLOWUhhULLuCOTIocBwn9Y24/iovBviZVOqyKQPLCu9ViT9KnQ== X-Received: by 2002:a63:5a23:: with SMTP id o35mr16711123pgb.4.1580585380410; Sat, 01 Feb 2020 11:29:40 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 19/41] target/arm: Reorganize ARMMMUIdx Date: Sat, 1 Feb 2020 11:28:54 -0800 Message-Id: <20200201192916.31796-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200201192916.31796-1-richard.henderson@linaro.org> References: <20200201192916.31796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Prepare for, but do not yet implement, the EL2&0 regime. This involves adding the new MMUIdx enumerators and adjusting some of the MMUIdx related predicates to match. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- target/arm/cpu-param.h | 2 +- target/arm/cpu.h | 134 ++++++++++++++++++----------------------- target/arm/internals.h | 35 +++++++++++ target/arm/helper.c | 66 +++++++++++++++++--- target/arm/translate.c | 1 - 5 files changed, 152 insertions(+), 86 deletions(-) diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 6e6948e960..18ac562346 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -29,6 +29,6 @@ # define TARGET_PAGE_BITS_MIN 10 #endif =20 -#define NB_MMU_MODES 8 +#define NB_MMU_MODES 9 =20 #endif diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ad92873943..3fc0e6e746 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2819,18 +2819,21 @@ static inline bool arm_excp_unmasked(CPUState *cs, = unsigned int excp_idx, * + NonSecure EL1 & 0 stage 1 * + NonSecure EL1 & 0 stage 2 * + NonSecure EL2 - * + Secure EL1 & EL0 + * + NonSecure EL2 & 0 (ARMv8.1-VHE) + * + Secure EL1 & 0 * + Secure EL3 * If EL3 is 32-bit: * + NonSecure PL1 & 0 stage 1 * + NonSecure PL1 & 0 stage 2 * + NonSecure PL2 - * + Secure PL0 & PL1 + * + Secure PL0 + * + Secure PL1 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) * * For QEMU, an mmu_idx is not quite the same as a translation regime beca= use: - * 1. we need to split the "EL1 & 0" regimes into two mmu_idxes, because = they - * may differ in access permissions even if the VA->PA map is the same + * 1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_i= dxes, + * because they may differ in access permissions even if the VA->PA ma= p is + * the same * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage= 1+2 * translation, which means that we have one mmu_idx that deals with t= wo * concatenated translation regimes [this sort of combined s1+2 TLB is @@ -2842,19 +2845,23 @@ static inline bool arm_excp_unmasked(CPUState *cs, = unsigned int excp_idx, * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" * translation regimes, because they map reasonably well to each other * and they can't both be active at the same time. - * This gives us the following list of mmu_idx values: + * 5. we want to be able to use the TLB for accesses done as part of a + * stage1 page table walk, rather than having to walk the stage2 page + * table over and over. * - * NS EL0 (aka NS PL0) stage 1+2 - * NS EL1 (aka NS PL1) stage 1+2 + * This gives us the following list of cases: + * + * NS EL0 EL1&0 stage 1+2 (aka NS PL0) + * NS EL1 EL1&0 stage 1+2 (aka NS PL1) + * NS EL0 EL2&0 + * NS EL2 EL2&0 * NS EL2 (aka NS PL2) + * S EL0 EL1&0 (aka S PL0) + * S EL1 EL1&0 (not used if EL3 is 32 bit) * S EL3 (aka S PL1) - * S EL0 (aka S PL0) - * S EL1 (not used if EL3 is 32 bit) - * NS EL0+1 stage 2 + * NS EL1&0 stage 2 * - * (The last of these is an mmu_idx because we want to be able to use the = TLB - * for the accesses done as part of a stage 1 page table walk, rather than - * having to walk the stage 2 page table over and over.) + * for a total of 9 different mmu_idx. * * R profile CPUs have an MPU, but can use the same set of MMU indexes * as A profile. They only need to distinguish NS EL0 and NS EL1 (and @@ -2892,26 +2899,47 @@ static inline bool arm_excp_unmasked(CPUState *cs, = unsigned int excp_idx, * For M profile we arrange them to have a bit for priv, a bit for negpri * and a bit for secure. */ -#define ARM_MMU_IDX_A 0x10 /* A profile */ -#define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ -#define ARM_MMU_IDX_M 0x40 /* M profile */ +#define ARM_MMU_IDX_A 0x10 /* A profile */ +#define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ +#define ARM_MMU_IDX_M 0x40 /* M profile */ =20 -/* meanings of the bits for M profile mmu idx values */ -#define ARM_MMU_IDX_M_PRIV 0x1 +/* Meanings of the bits for M profile mmu idx values */ +#define ARM_MMU_IDX_M_PRIV 0x1 #define ARM_MMU_IDX_M_NEGPRI 0x2 -#define ARM_MMU_IDX_M_S 0x4 +#define ARM_MMU_IDX_M_S 0x4 /* Secure */ =20 -#define ARM_MMU_IDX_TYPE_MASK (~0x7) -#define ARM_MMU_IDX_COREIDX_MASK 0x7 +#define ARM_MMU_IDX_TYPE_MASK \ + (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB) +#define ARM_MMU_IDX_COREIDX_MASK 0xf =20 typedef enum ARMMMUIdx { - ARMMMUIdx_E10_0 =3D 0 | ARM_MMU_IDX_A, - ARMMMUIdx_E10_1 =3D 1 | ARM_MMU_IDX_A, - ARMMMUIdx_E2 =3D 2 | ARM_MMU_IDX_A, - ARMMMUIdx_SE3 =3D 3 | ARM_MMU_IDX_A, - ARMMMUIdx_SE10_0 =3D 4 | ARM_MMU_IDX_A, - ARMMMUIdx_SE10_1 =3D 5 | ARM_MMU_IDX_A, - ARMMMUIdx_Stage2 =3D 6 | ARM_MMU_IDX_A, + /* + * A-profile. + */ + ARMMMUIdx_E10_0 =3D 0 | ARM_MMU_IDX_A, + ARMMMUIdx_E20_0 =3D 1 | ARM_MMU_IDX_A, + + ARMMMUIdx_E10_1 =3D 2 | ARM_MMU_IDX_A, + + ARMMMUIdx_E2 =3D 3 | ARM_MMU_IDX_A, + ARMMMUIdx_E20_2 =3D 4 | ARM_MMU_IDX_A, + + ARMMMUIdx_SE10_0 =3D 5 | ARM_MMU_IDX_A, + ARMMMUIdx_SE10_1 =3D 6 | ARM_MMU_IDX_A, + ARMMMUIdx_SE3 =3D 7 | ARM_MMU_IDX_A, + + ARMMMUIdx_Stage2 =3D 8 | ARM_MMU_IDX_A, + + /* + * These are not allocated TLBs and are used only for AT system + * instructions or for the first stage of an S12 page table walk. + */ + ARMMMUIdx_Stage1_E0 =3D 0 | ARM_MMU_IDX_NOTLB, + ARMMMUIdx_Stage1_E1 =3D 1 | ARM_MMU_IDX_NOTLB, + + /* + * M-profile. + */ ARMMMUIdx_MUser =3D ARM_MMU_IDX_M, ARMMMUIdx_MPriv =3D ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV, ARMMMUIdx_MUserNegPri =3D ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI, @@ -2920,11 +2948,6 @@ typedef enum ARMMMUIdx { ARMMMUIdx_MSPriv =3D ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S, ARMMMUIdx_MSUserNegPri =3D ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S, ARMMMUIdx_MSPrivNegPri =3D ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S, - /* Indexes below here don't have TLBs and are used only for AT system - * instructions or for the first stage of an S12 page table walk. - */ - ARMMMUIdx_Stage1_E0 =3D 0 | ARM_MMU_IDX_NOTLB, - ARMMMUIdx_Stage1_E1 =3D 1 | ARM_MMU_IDX_NOTLB, } ARMMMUIdx; =20 /* @@ -2936,8 +2959,10 @@ typedef enum ARMMMUIdx { =20 typedef enum ARMMMUIdxBit { TO_CORE_BIT(E10_0), + TO_CORE_BIT(E20_0), TO_CORE_BIT(E10_1), TO_CORE_BIT(E2), + TO_CORE_BIT(E20_2), TO_CORE_BIT(SE10_0), TO_CORE_BIT(SE10_1), TO_CORE_BIT(SE3), @@ -2957,49 +2982,6 @@ typedef enum ARMMMUIdxBit { =20 #define MMU_USER_IDX 0 =20 -static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx) -{ - return mmu_idx & ARM_MMU_IDX_COREIDX_MASK; -} - -static inline ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx) -{ - if (arm_feature(env, ARM_FEATURE_M)) { - return mmu_idx | ARM_MMU_IDX_M; - } else { - return mmu_idx | ARM_MMU_IDX_A; - } -} - -/* Return the exception level we're running at if this is our mmu_idx */ -static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) -{ - switch (mmu_idx & ARM_MMU_IDX_TYPE_MASK) { - case ARM_MMU_IDX_A: - return mmu_idx & 3; - case ARM_MMU_IDX_M: - return mmu_idx & ARM_MMU_IDX_M_PRIV; - default: - g_assert_not_reached(); - } -} - -/* - * Return the MMU index for a v7M CPU with all relevant information - * manually specified. - */ -ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env, - bool secstate, bool priv, bool negpri); - -/* Return the MMU index for a v7M CPU in the specified security and - * privilege state. - */ -ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, - bool secstate, bool priv); - -/* Return the MMU index for a v7M CPU in the specified security state */ -ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate); - /** * cpu_mmu_index: * @env: The cpu environment diff --git a/target/arm/internals.h b/target/arm/internals.h index 5b8b9c233f..0c4119a3a2 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -769,6 +769,39 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int= size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); =20 +static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx) +{ + return mmu_idx & ARM_MMU_IDX_COREIDX_MASK; +} + +static inline ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx) +{ + if (arm_feature(env, ARM_FEATURE_M)) { + return mmu_idx | ARM_MMU_IDX_M; + } else { + return mmu_idx | ARM_MMU_IDX_A; + } +} + +int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx); + +/* + * Return the MMU index for a v7M CPU with all relevant information + * manually specified. + */ +ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env, + bool secstate, bool priv, bool negpri); + +/* + * Return the MMU index for a v7M CPU in the specified security and + * privilege state. + */ +ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, + bool secstate, bool priv); + +/* Return the MMU index for a v7M CPU in the specified security state */ +ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate); + /* Return true if the stage 1 translation regime is using LPAE format page * tables */ bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx); @@ -810,6 +843,8 @@ static inline bool regime_is_secure(CPUARMState *env, A= RMMMUIdx mmu_idx) switch (mmu_idx) { case ARMMMUIdx_E10_0: case ARMMMUIdx_E10_1: + case ARMMMUIdx_E20_0: + case ARMMMUIdx_E20_2: case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_E2: diff --git a/target/arm/helper.c b/target/arm/helper.c index 5609bb18e8..3ce37c2c16 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8707,9 +8707,11 @@ void arm_cpu_do_interrupt(CPUState *cs) #endif /* !CONFIG_USER_ONLY */ =20 /* Return the exception level which controls this address translation regi= me */ -static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) +static uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) { switch (mmu_idx) { + case ARMMMUIdx_E20_0: + case ARMMMUIdx_E20_2: case ARMMMUIdx_Stage2: case ARMMMUIdx_E2: return 2; @@ -8720,6 +8722,8 @@ static inline uint32_t regime_el(CPUARMState *env, AR= MMMUIdx mmu_idx) case ARMMMUIdx_SE10_1: case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_Stage1_E1: + case ARMMMUIdx_E10_0: + case ARMMMUIdx_E10_1: case ARMMMUIdx_MPrivNegPri: case ARMMMUIdx_MUserNegPri: case ARMMMUIdx_MPriv: @@ -8821,10 +8825,14 @@ static inline TCR *regime_tcr(CPUARMState *env, ARM= MMUIdx mmu_idx) */ static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) { - if (mmu_idx =3D=3D ARMMMUIdx_E10_0 || mmu_idx =3D=3D ARMMMUIdx_E10_1) { - mmu_idx +=3D (ARMMMUIdx_Stage1_E0 - ARMMMUIdx_E10_0); + switch (mmu_idx) { + case ARMMMUIdx_E10_0: + return ARMMMUIdx_Stage1_E0; + case ARMMMUIdx_E10_1: + return ARMMMUIdx_Stage1_E1; + default: + return mmu_idx; } - return mmu_idx; } =20 /* Return true if the translation regime is using LPAE format page tables = */ @@ -8857,6 +8865,7 @@ static inline bool regime_is_user(CPUARMState *env, A= RMMMUIdx mmu_idx) { switch (mmu_idx) { case ARMMMUIdx_SE10_0: + case ARMMMUIdx_E20_0: case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_MUser: case ARMMMUIdx_MSUser: @@ -11282,6 +11291,31 @@ int fp_exception_el(CPUARMState *env, int cur_el) return 0; } =20 +/* Return the exception level we're running at if this is our mmu_idx */ +int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) +{ + if (mmu_idx & ARM_MMU_IDX_M) { + return mmu_idx & ARM_MMU_IDX_M_PRIV; + } + + switch (mmu_idx) { + case ARMMMUIdx_E10_0: + case ARMMMUIdx_E20_0: + case ARMMMUIdx_SE10_0: + return 0; + case ARMMMUIdx_E10_1: + case ARMMMUIdx_SE10_1: + return 1; + case ARMMMUIdx_E2: + case ARMMMUIdx_E20_2: + return 2; + case ARMMMUIdx_SE3: + return 3; + default: + g_assert_not_reached(); + } +} + #ifndef CONFIG_TCG ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) { @@ -11295,10 +11329,26 @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el) return arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure); } =20 - if (el < 2 && arm_is_secure_below_el3(env)) { - return ARMMMUIdx_SE10_0 + el; - } else { - return ARMMMUIdx_E10_0 + el; + switch (el) { + case 0: + /* TODO: ARMv8.1-VHE */ + if (arm_is_secure_below_el3(env)) { + return ARMMMUIdx_SE10_0; + } + return ARMMMUIdx_E10_0; + case 1: + if (arm_is_secure_below_el3(env)) { + return ARMMMUIdx_SE10_1; + } + return ARMMMUIdx_E10_1; + case 2: + /* TODO: ARMv8.1-VHE */ + /* TODO: ARMv8.4-SecEL2 */ + return ARMMMUIdx_E2; + case 3: + return ARMMMUIdx_SE3; + default: + g_assert_not_reached(); } } =20 diff --git a/target/arm/translate.c b/target/arm/translate.c index c169984374..e11a5871d0 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -172,7 +172,6 @@ static inline int get_a32_user_mem_index(DisasContext *= s) case ARMMMUIdx_MSUserNegPri: case ARMMMUIdx_MSPrivNegPri: return arm_to_core_mmu_idx(ARMMMUIdx_MSUserNegPri); - case ARMMMUIdx_Stage2: default: g_assert_not_reached(); } --=20 2.20.1 From nobody Mon Feb 9 12:19:52 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; 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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id l7sm3668509pga.27.2020.02.01.11.29.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Feb 2020 11:29:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NO5geiKU0WW+2TMAZFM42a5g80KJNqQfQbAvXgXj01c=; b=vC4VVw1UHHRcpzxx+9LlIgd8oDUrJgRh//niIJqliU6eO/QEGEqpxDnXeug+5cekeD HViOxz2IJN5U/09pWxmo0V9VhvbAI/PpsD3DkJ8s/pT1sHXqzgWGdvwf7f6ccIMmX5TF TpZI2PMLtueTLcsKbS9bF2cYqowHst+rgUiVsnPBIZ16XPGjSE3FiwRQhHWErlfNfg3z wXiXRh/WMnfqSJNdLMs10r3gAXlKajfd0/n6F+xOmWS6upmli0URHN/smbwWATfR6wX7 ArQxV4SIxGJgxPJIqgehHNPD2Lvwq2WisocwxKbEAisqvS/hwJoSf1XDeh5hdgIHtqjP ZT1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NO5geiKU0WW+2TMAZFM42a5g80KJNqQfQbAvXgXj01c=; b=UQtttYCQUkSgin6iFRXiWszcnOMyIc3rtqThTxWpfIBAX/ESCWwSbkJ7vOsDcxOZf7 rAG2B4GbI9YzeDuoX1nXcYlyQQrMEfe5b91HDDY/A2POe0tPKaBE48NEhLvkDLcBbNef 4p4sHKR1Fy/IsZ28hZfUvL4hJTvVyEibursrYQqUvihG/7xc3TmvBpq9z0blv/DLFgDR Ar249qDz3A9RLYXUqFr/8gTEzNholL683uhbfWK2uK9SIb+LvPVAI5ATMz9fociWeoTY MD2kBbs8GyQjtws6ubwVc7TN/awGm1Chqj7NYaTPmTcVRu+y+DTNXvLGQGLHZsHrz26l kqUA== X-Gm-Message-State: APjAAAX1Cw5K2uqvL9cyPy6eX7WVVl8+sVCE3N9wjvhIcuEFIBBvFZHw BmAXk+kBz6HcBBo6WXq27k/DbgPo5TU= X-Google-Smtp-Source: APXvYqysfZUsCvm1BYgUfM/LJvYyT1A4JOqsLPCkQQWffcqYM2DQxkX3OiZiINQUAyC87sPuxU5iQQ== X-Received: by 2002:aa7:914b:: with SMTP id 11mr17327522pfi.69.1580585381745; Sat, 01 Feb 2020 11:29:41 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 20/41] target/arm: Add regime_has_2_ranges Date: Sat, 1 Feb 2020 11:28:55 -0800 Message-Id: <20200201192916.31796-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200201192916.31796-1-richard.henderson@linaro.org> References: <20200201192916.31796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::436 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Create a predicate to indicate whether the regime has both positive and negative addresses. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- target/arm/internals.h | 18 ++++++++++++++++++ target/arm/helper.c | 23 ++++++----------------- target/arm/translate-a64.c | 3 +-- 3 files changed, 25 insertions(+), 19 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 0c4119a3a2..6d4a942bde 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -837,6 +837,24 @@ static inline void arm_call_el_change_hook(ARMCPU *cpu) } } =20 +/* Return true if this address translation regime has two ranges. */ +static inline bool regime_has_2_ranges(ARMMMUIdx mmu_idx) +{ + switch (mmu_idx) { + case ARMMMUIdx_Stage1_E0: + case ARMMMUIdx_Stage1_E1: + case ARMMMUIdx_E10_0: + case ARMMMUIdx_E10_1: + case ARMMMUIdx_E20_0: + case ARMMMUIdx_E20_2: + case ARMMMUIdx_SE10_0: + case ARMMMUIdx_SE10_1: + return true; + default: + return false; + } +} + /* Return true if this address translation regime is secure */ static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) { diff --git a/target/arm/helper.c b/target/arm/helper.c index 3ce37c2c16..f7bc7f1a8d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9031,15 +9031,8 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mm= u_idx, bool is_aa64, } =20 if (is_aa64) { - switch (regime_el(env, mmu_idx)) { - case 1: - if (!is_user) { - xn =3D pxn || (user_rw & PAGE_WRITE); - } - break; - case 2: - case 3: - break; + if (regime_has_2_ranges(mmu_idx) && !is_user) { + xn =3D pxn || (user_rw & PAGE_WRITE); } } else if (arm_feature(env, ARM_FEATURE_V7)) { switch (regime_el(env, mmu_idx)) { @@ -9573,7 +9566,6 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *= env, uint64_t va, ARMMMUIdx mmu_idx) { uint64_t tcr =3D regime_tcr(env, mmu_idx)->raw_tcr; - uint32_t el =3D regime_el(env, mmu_idx); bool tbi, tbid, epd, hpd, using16k, using64k; int select, tsz; =20 @@ -9583,7 +9575,7 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *= env, uint64_t va, */ select =3D extract64(va, 55, 1); =20 - if (el > 1) { + if (!regime_has_2_ranges(mmu_idx)) { tsz =3D extract32(tcr, 0, 6); using64k =3D extract32(tcr, 14, 1); using16k =3D extract32(tcr, 15, 1); @@ -9739,10 +9731,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, tar= get_ulong address, param =3D aa64_va_parameters(env, address, mmu_idx, access_type !=3D MMU_INST_FETCH); level =3D 0; - /* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mark = it - * invalid. - */ - ttbr1_valid =3D (el < 2); + ttbr1_valid =3D regime_has_2_ranges(mmu_idx); addrsize =3D 64 - 8 * param.tbi; inputsize =3D 64 - param.tsz; } else { @@ -11458,8 +11447,8 @@ static uint32_t rebuild_hflags_a64(CPUARMState *env= , int el, int fp_el, =20 flags =3D FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1); =20 - /* FIXME: ARMv8.1-VHE S2 translation regime. */ - if (regime_el(env, stage1) < 2) { + /* Get control bits for tagged addresses. */ + if (regime_has_2_ranges(mmu_idx)) { ARMVAParameters p1 =3D aa64_va_parameters_both(env, -1, stage1); tbid =3D (p1.tbi << 1) | p0.tbi; tbii =3D tbid & ~((p1.tbid << 1) | p0.tbid); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index fcfb96ce1f..3982e1988d 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -175,8 +175,7 @@ static void gen_top_byte_ignore(DisasContext *s, TCGv_i= 64 dst, if (tbi =3D=3D 0) { /* Load unmodified address */ tcg_gen_mov_i64(dst, src); - } else if (s->current_el >=3D 2) { - /* FIXME: ARMv8.1-VHE S2 translation regime. */ + } else if (!regime_has_2_ranges(s->mmu_idx)) { /* Force tag byte to all zero */ tcg_gen_extract_i64(dst, src, 0, 56); } else { --=20 2.20.1 From nobody Mon Feb 9 12:19:52 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580586454627732.4886332915473; Sat, 1 Feb 2020 11:47:34 -0800 (PST) Received: from localhost ([::1]:50030 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixyjt-0001gx-HP for importer@patchew.org; Sat, 01 Feb 2020 14:47:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58755) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixySf-0007am-GF for qemu-devel@nongnu.org; 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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id l7sm3668509pga.27.2020.02.01.11.29.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Feb 2020 11:29:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OKxQq943wt4uroP1gZYZ49QNE9fpaRpfrXYqhLFIHks=; b=T4Glt6esKqFhEf5eWsJCZ/SWx+H8jJOtN0e6mOd5SuC2gObiNffJO+dYha7h6xH+py 6vv+4XpIrNwYNS1GSO/AzDDSYQPeMVOjmxY4PmiuQRaNLylcWJOWNLy9SV9cw3iZ5PzD ESsLotjjT97BN/u3w1LBfgXjONxqran8dgmwwpgSGBtkHniYLdQMg8SBWgyJw35T8V/a 0dxW6kAOIcRoBtcyO+ZUPb3Po/cPbogkPN8No2H0/g2I0FV13SpGry+JIphmBsAlnoRj hf31NCxw2Iz1M9aT0apgkMDKi4hLOghL2WI1kW2vjcCjtYHbEC4rberTbmjs7CT8ACFY gvAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OKxQq943wt4uroP1gZYZ49QNE9fpaRpfrXYqhLFIHks=; b=Gb7/n/khuJ8wxOg2VA1D91h+BLeUHMNz9MTOSX+n3xEja+/KoyFFase1FtFlj7lfPZ YondyPcl+5Nm1MOA1Fi85NpzZtDpwcxNqcpWKyivjWybNLvPPuB+1rv8ad6XX+TKcxoG 1CMYMZNWJpbmQqyuoSz4zDHExbhBXofzK2ezF9e4t9yUQ9uo16Egyp233G3omgwaYCeY z/bIY88rA8JrFHAUtyBjKnFvMWLimLL+Ch2xhvMZ3xGTavouoPK+htJ7ECwvP6vmY8YR s9TXieiM7mgOr9oVZIfQLcgxj5//L9VpM0TFmusdrcRsC47Tse/Do3wnZNkclYX3Dnqs MN6w== X-Gm-Message-State: APjAAAWr5Lads3a2T7R6HD5MD+WxVb9wiDyoyAoGs+gXRjSAHr3zgJLQ 8//kfovHzKqTzGcitIlTCepjm3kvkn4= X-Google-Smtp-Source: APXvYqyjlACDbkuUhY5ZV0Y+vXweSM48RZP39HKel5NY7Q+2uDQbtRrcP2QFMqcf89mRtbSIaxvqfw== X-Received: by 2002:a63:7c4d:: with SMTP id l13mr1701626pgn.275.1580585383218; Sat, 01 Feb 2020 11:29:43 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 21/41] target/arm: Update arm_mmu_idx for VHE Date: Sat, 1 Feb 2020 11:28:56 -0800 Message-Id: <20200201192916.31796-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200201192916.31796-1-richard.henderson@linaro.org> References: <20200201192916.31796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Return the indexes for the EL2&0 regime when the appropriate bits are set within HCR_EL2. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- v4: Consistently check E2H & TGE & ELUsingAArch32(EL2). Do not apply TGE at EL2. --- target/arm/helper.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index f7bc7f1a8d..9f8d7ca1f3 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11318,12 +11318,16 @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el) return arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure); } =20 + /* See ARM pseudo-function ELIsInHost. */ switch (el) { case 0: - /* TODO: ARMv8.1-VHE */ if (arm_is_secure_below_el3(env)) { return ARMMMUIdx_SE10_0; } + if ((env->cp15.hcr_el2 & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HC= R_TGE) + && arm_el_is_aa64(env, 2)) { + return ARMMMUIdx_E20_0; + } return ARMMMUIdx_E10_0; case 1: if (arm_is_secure_below_el3(env)) { @@ -11331,8 +11335,11 @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el) } return ARMMMUIdx_E10_1; case 2: - /* TODO: ARMv8.1-VHE */ /* TODO: ARMv8.4-SecEL2 */ + /* Note that TGE does not apply at EL2. */ + if ((env->cp15.hcr_el2 & HCR_E2H) && arm_el_is_aa64(env, 2)) { + return ARMMMUIdx_E20_2; + } return ARMMMUIdx_E2; case 3: return ARMMMUIdx_SE3; --=20 2.20.1 From nobody Mon Feb 9 12:19:52 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580585775728655.9086408384793; Sat, 1 Feb 2020 11:36:15 -0800 (PST) Received: from localhost ([::1]:49364 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixyYw-0007zt-Jg for importer@patchew.org; Sat, 01 Feb 2020 14:36:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58775) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixySh-0007dS-71 for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ixySf-0006so-Rj for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:47 -0500 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:42681) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ixySf-0006ro-M4 for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:45 -0500 Received: by mail-pg1-x543.google.com with SMTP id s64so5454406pgb.9 for ; Sat, 01 Feb 2020 11:29:45 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id l7sm3668509pga.27.2020.02.01.11.29.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Feb 2020 11:29:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=juHwnM8Na/3KK56bRpT8cVui++cBSP96GHuLJj2xiMg=; b=xM+07iXq2u1pCuJQLVjYH2LdM7NScv5mVx7IwCuG9cOYZtcurx/GY65jw5+kKzaRGM Go5v69WTfHJi8izaOEBgTLmdiu8cGcvOZUe5m1Sb1KPsfHmUN3sAr4rfMBKiFchVmEtd sXBwv5oXxWg++eWj8O+5J2Oo0ktvmsx0V+6W/aZOYmE0GtziyPamyo7UwkWKw+aSlXtx oaO9W3i7+dny2yv5Nxj5MGEFjPEGONV6UyLSZn0p4AYzlemm3KJSGLY7cHaajOP1EAfI iTeZNP33Hx02yxxd1TinribELY0jVGCxpfi0MpKjaoL1KC5wISQMHhfZCk1X6w/NtwMW WJEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=juHwnM8Na/3KK56bRpT8cVui++cBSP96GHuLJj2xiMg=; b=G67mB2eNjJFbCoMxvQ0lzlFGGQqVQI4/5vfm7gst/HUBENzL3n7dN6ortzyRhOiEpS TTVWUdBD25ZmWbeEMJtjVDs7xAFQmiZsgcynRLcD66b9xr4dGOrvOzwVEm7ZgSEXvDO+ po3vQw/iQf3th6aUqrCoJLPVNM+BZGt9p0WQR36C1S0zCafsbo+BOxH5mlzpuSqy3kFT Njb5Naj4Dctc34+hgH51IaSZJrDTZOQ3V9qOQlhX3op1SLHQ0YrbBxfln6TvHNNYvfHb /G8ZPTf/+bhZHQkPMH8fMOcg7qaJlU6zPn94m6LxKCTo/rZsfkvINER1/Py4sYvzd1u9 1JEw== X-Gm-Message-State: APjAAAXFApS1pBrSlHcx7myAehHHHpIZt9/RDmSdHbVCHSOfV3RzcnDU 57yUie22+91/eQ7DsAMeI2PT8JMetoI= X-Google-Smtp-Source: APXvYqzg6UXnFuaoJm9RRMxc+WhIQvZBz6jIcXz3Vfad+Qr4JOIkZILmwaPTLaD5Wi5DTlkEu7zYdw== X-Received: by 2002:aa7:9a96:: with SMTP id w22mr16506404pfi.210.1580585384416; Sat, 01 Feb 2020 11:29:44 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 22/41] target/arm: Update arm_sctlr for VHE Date: Sat, 1 Feb 2020 11:28:57 -0800 Message-Id: <20200201192916.31796-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200201192916.31796-1-richard.henderson@linaro.org> References: <20200201192916.31796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Use the correct sctlr for EL2&0 regime. Due to header ordering, and where arm_mmu_idx_el is declared, we need to move the function out of line. Use the function in many more places in order to select the correct control. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- v3: Use arm_mmu_idx() to avoid incorrectly replicating the el2&0 condition therein. Drop the change to cpu_get_dump_info, as that needs a more significant rethink of hard-coded oddness. v4: Use arm_mmu_idx_el(). --- target/arm/cpu.h | 10 +--------- target/arm/helper-a64.c | 2 +- target/arm/helper.c | 20 +++++++++++++++----- target/arm/pauth_helper.c | 9 +-------- 4 files changed, 18 insertions(+), 23 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 3fc0e6e746..68e11f0eda 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3141,15 +3141,7 @@ static inline bool arm_sctlr_b(CPUARMState *env) (env->cp15.sctlr_el[1] & SCTLR_B) !=3D 0; } =20 -static inline uint64_t arm_sctlr(CPUARMState *env, int el) -{ - if (el =3D=3D 0) { - /* FIXME: ARMv8.1-VHE S2 translation regime. */ - return env->cp15.sctlr_el[1]; - } else { - return env->cp15.sctlr_el[el]; - } -} +uint64_t arm_sctlr(CPUARMState *env, int el); =20 static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env, bool sctlr_b) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 36aa6badfd..bf45f8a785 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -70,7 +70,7 @@ static void daif_check(CPUARMState *env, uint32_t op, uint32_t imm, uintptr_t ra) { /* DAIF update to PSTATE. This is OK from EL0 only if UMA is set. */ - if (arm_current_el(env) =3D=3D 0 && !(env->cp15.sctlr_el[1] & SCTLR_UM= A)) { + if (arm_current_el(env) =3D=3D 0 && !(arm_sctlr(env, 0) & SCTLR_UMA)) { raise_exception_ra(env, EXCP_UDEF, syn_aa64_sysregtrap(0, extract32(op, 0, 3), extract32(op, 3, 3), 4, diff --git a/target/arm/helper.c b/target/arm/helper.c index 9f8d7ca1f3..e4f368d96b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3913,7 +3913,7 @@ static void aa64_fpsr_write(CPUARMState *env, const A= RMCPRegInfo *ri, static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInf= o *ri, bool isread) { - if (arm_current_el(env) =3D=3D 0 && !(env->cp15.sctlr_el[1] & SCTLR_UM= A)) { + if (arm_current_el(env) =3D=3D 0 && !(arm_sctlr(env, 0) & SCTLR_UMA)) { return CP_ACCESS_TRAP; } return CP_ACCESS_OK; @@ -3932,7 +3932,7 @@ static CPAccessResult aa64_cacheop_access(CPUARMState= *env, /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless * SCTLR_EL1.UCI is set. */ - if (arm_current_el(env) =3D=3D 0 && !(env->cp15.sctlr_el[1] & SCTLR_UC= I)) { + if (arm_current_el(env) =3D=3D 0 && !(arm_sctlr(env, 0) & SCTLR_UCI)) { return CP_ACCESS_TRAP; } return CP_ACCESS_OK; @@ -8738,14 +8738,24 @@ static uint32_t regime_el(CPUARMState *env, ARMMMUI= dx mmu_idx) } } =20 -#ifndef CONFIG_USER_ONLY +uint64_t arm_sctlr(CPUARMState *env, int el) +{ + /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */ + if (el =3D=3D 0) { + ARMMMUIdx mmu_idx =3D arm_mmu_idx_el(env, 0); + el =3D (mmu_idx =3D=3D ARMMMUIdx_E20_0 ? 2 : 1); + } + return env->cp15.sctlr_el[el]; +} =20 /* Return the SCTLR value which controls this address translation regime */ -static inline uint32_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx) +static inline uint64_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx) { return env->cp15.sctlr_el[regime_el(env, mmu_idx)]; } =20 +#ifndef CONFIG_USER_ONLY + /* Return true if the specified stage of address translation is disabled */ static inline bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx) @@ -11484,7 +11494,7 @@ static uint32_t rebuild_hflags_a64(CPUARMState *env= , int el, int fp_el, flags =3D FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len); } =20 - sctlr =3D arm_sctlr(env, el); + sctlr =3D regime_sctlr(env, stage1); =20 if (arm_cpu_data_is_big_endian_a64(el, sctlr)) { flags =3D FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1); diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c index 0a5f41e10c..e0c401c4a9 100644 --- a/target/arm/pauth_helper.c +++ b/target/arm/pauth_helper.c @@ -386,14 +386,7 @@ static void pauth_check_trap(CPUARMState *env, int el,= uintptr_t ra) =20 static bool pauth_key_enabled(CPUARMState *env, int el, uint32_t bit) { - uint32_t sctlr; - if (el =3D=3D 0) { - /* FIXME: ARMv8.1-VHE S2 translation regime. */ - sctlr =3D env->cp15.sctlr_el[1]; - } else { - sctlr =3D env->cp15.sctlr_el[el]; - } - return (sctlr & bit) !=3D 0; + return (arm_sctlr(env, el) & bit) !=3D 0; } =20 uint64_t HELPER(pacia)(CPUARMState *env, uint64_t x, uint64_t y) --=20 2.20.1 From nobody Mon Feb 9 12:19:52 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580586535232258.75432266355403; Sat, 1 Feb 2020 11:48:55 -0800 (PST) Received: from localhost ([::1]:50066 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixylC-0004FD-7S for importer@patchew.org; Sat, 01 Feb 2020 14:48:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58787) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixySh-0007es-TO for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ixySg-0006tZ-RG for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:47 -0500 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:46579) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ixySg-0006t6-La for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:46 -0500 Received: by mail-pg1-x541.google.com with SMTP id z124so5463965pgb.13 for ; Sat, 01 Feb 2020 11:29:46 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id l7sm3668509pga.27.2020.02.01.11.29.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Feb 2020 11:29:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jMzpsQB0pS3SDomXtbYrmrRRLdb/Rnlv6gkmO2VOo+M=; b=Gla7s8qwMa3uLBHCzJuEPEIDR+33F2tawlP55oVkNWuwqdjEjHuLqEPv1K7u2fjNCe dpBcc4Dy2plQ1x++hiAW+g1X004gkWQbNyI3FtGxXOihw9n5Mx1wvGUAwKEQxrdwYh1W w9+A9871dDMHJh5g9g8hWQygPA8SIiw5gDtldACT9CM3jySKZcV1fQcs/JsAVkBBQUZO 5lYlJiIyML1/SWgjexpd3FkeosveY3i0nMeK/tl9SDlJf1yV2gTXv9yYlGcfOGzh4FjG nmGSyTrZJ7/o6i+gJbM8JUtFuCOqUKVaqz/mfj0pZ+E3z5khu4vEPwWiy+bpm9PRoxuX CmHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jMzpsQB0pS3SDomXtbYrmrRRLdb/Rnlv6gkmO2VOo+M=; b=a+4oSUGFkR8jpNt5SGiKDgSowgB3LWWwfT4pTHuSajie+p2eUBuqGtugq+FWQfwEgl haDQjHHSvWU8NmGWW3rgWXF4NlwnuqBHN2VG6lVou1qbXd4iem02mm2TyKwvmNgGVdrW Y1Gm6hjbhn5QVIERyGee5D2i1IYYJydjAKNlKNshZQSBqGn9KjH2CON5utizwku15The Vd7lSTVmkOLN+aBtCRcvCrpiCJaPSgwntVwaAFH9yPDkvrWRvwWOhbGcbOuvnTAq9rTM Ec1eyW/hn7g3d4SrhKljOvrEbQF+L0idaBzI3EH1AYG8FFoMEIpq3+nptUYTu8BzeYrZ YSYw== X-Gm-Message-State: APjAAAVlDkvazGJxKubglBXnphmAdDGSk0dR1KoF+qoQGp7vyiOmpxkt qAkhAJ5z0xKhNlH3AUErhMJ7cac+qf8= X-Google-Smtp-Source: APXvYqyV/GD3Htzc0T4c7ZZz+73G+lpKbPnGjqGeddCKtsMKdVpWd/fohy5IeqoikQqgRktxahxZ2w== X-Received: by 2002:a63:ce4b:: with SMTP id r11mr17524118pgi.419.1580585385487; Sat, 01 Feb 2020 11:29:45 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 23/41] target/arm: Update aa64_zva_access for EL2 Date: Sat, 1 Feb 2020 11:28:58 -0800 Message-Id: <20200201192916.31796-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200201192916.31796-1-richard.henderson@linaro.org> References: <20200201192916.31796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) The comment that we don't support EL2 is somewhat out of date. Update to include checks against HCR_EL2.TDZ. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- target/arm/helper.c | 26 +++++++++++++++++++++----- 1 file changed, 21 insertions(+), 5 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index e4f368d96b..e41bece6b5 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4159,11 +4159,27 @@ static void tlbi_aa64_ipas2e1is_write(CPUARMState *= env, const ARMCPRegInfo *ri, static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo= *ri, bool isread) { - /* We don't implement EL2, so the only control on DC ZVA is the - * bit in the SCTLR which can prohibit access for EL0. - */ - if (arm_current_el(env) =3D=3D 0 && !(env->cp15.sctlr_el[1] & SCTLR_DZ= E)) { - return CP_ACCESS_TRAP; + int cur_el =3D arm_current_el(env); + + if (cur_el < 2) { + uint64_t hcr =3D arm_hcr_el2_eff(env); + + if (cur_el =3D=3D 0) { + if ((hcr & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)) { + if (!(env->cp15.sctlr_el[2] & SCTLR_DZE)) { + return CP_ACCESS_TRAP_EL2; + } + } else { + if (!(env->cp15.sctlr_el[1] & SCTLR_DZE)) { + return CP_ACCESS_TRAP; + } + if (hcr & HCR_TDZ) { + return CP_ACCESS_TRAP_EL2; + } + } + } else if (hcr & HCR_TDZ) { + return CP_ACCESS_TRAP_EL2; + } } return CP_ACCESS_OK; } --=20 2.20.1 From nobody Mon Feb 9 12:19:52 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580585878989132.03801150459935; Sat, 1 Feb 2020 11:37:58 -0800 (PST) Received: from localhost ([::1]:49414 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixyab-0002si-TH for importer@patchew.org; Sat, 01 Feb 2020 14:37:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58800) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixySi-0007g3-QB for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ixySh-0006ub-S0 for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:48 -0500 Received: from mail-pf1-x441.google.com ([2607:f8b0:4864:20::441]:41584) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ixySh-0006tu-Lx for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:47 -0500 Received: by mail-pf1-x441.google.com with SMTP id j9so2187558pfa.8 for ; Sat, 01 Feb 2020 11:29:47 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id l7sm3668509pga.27.2020.02.01.11.29.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Feb 2020 11:29:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Norg9fPtXVkCxAbFxqHU+mKSGwd6dWrkKXpQEb83JIc=; b=o6riD22JdE0vtcQzXipfO5ZeBNdpHJVMwCDEYVec3QkaTID68o6Dd+hfP7sCkGD2Qk 8GCnYRBX7O5I/sMQhKzRuvZof7FqB0YVyRko+e5faQQJHG1dwMlbttP7d5p8mkZu0uIY 6OygE/TNOq/gOc5fnIE8SbaTtOmAZNavbgtlkM52NJxxG38/y9SSoYQVZD9wQgu+j3Zi DCx940eNNB3Fwv+oajNiKpZiAVGLxTw0SP8lmbZhg7s12im8h2Wd+IvPNnFzQVx4BY3t kFEIkkCsG+w2a1LYh9JnPsMtL60oXHXEzcUDYi9niIQfXaBCJCSatBkx9Ychw6As4xUt DPmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Norg9fPtXVkCxAbFxqHU+mKSGwd6dWrkKXpQEb83JIc=; b=Dmm3sgwYQzNlUniuV/FpXaht0zO0G9e9jJhJbCtzSDeEE6mtwW1qucBYKVpaKAUEZ3 JDQNL3mc/Qayh5RNXRK23FC5mYPM8vRFvN7NM5aALpiThVravy0zNBaNoy6Ab2etiEDr FTEbsgnD8H6C0FNwSrD09Rud+IPRoH5Trm5U0eLo9eMt2fLKCSFuU1tTYnZVn7WzUDVb dgriljBU1SSpxUk+ajxr57+N+r+EOab4aghBYxDvcCWYLj6XKnPiTn7pIKEQE1vaa0tr g+FWs1RHNoHSBSg2NRbUwuRQnAOVN5FY2qO8WXBfrk5h+KLvA7qanNUdxdUC+wt5zCyN LeFA== X-Gm-Message-State: APjAAAXOE5ikP7XLeNEKLxD8vJAHMxqiXZen4tOActbw+gW/6zc0vXvk B2xCqrQW7BVp1hiNzxcscePaPkx/950= X-Google-Smtp-Source: APXvYqxPTJkr1P8auMD8FJ7kRayioEO30jRFI9YRcKtOzMxb7DkN9eqZRlKhuaG39G2vakjd2CVpuw== X-Received: by 2002:a62:7a8a:: with SMTP id v132mr17567217pfc.111.1580585386460; Sat, 01 Feb 2020 11:29:46 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 24/41] target/arm: Update ctr_el0_access for EL2 Date: Sat, 1 Feb 2020 11:28:59 -0800 Message-Id: <20200201192916.31796-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200201192916.31796-1-richard.henderson@linaro.org> References: <20200201192916.31796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Update to include checks against HCR_EL2.TID2. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- target/arm/helper.c | 26 +++++++++++++++++++++----- 1 file changed, 21 insertions(+), 5 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index e41bece6b5..72b336e3b5 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5264,11 +5264,27 @@ static const ARMCPRegInfo el3_cp_reginfo[] =3D { static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo = *ri, bool isread) { - /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64, - * but the AArch32 CTR has its own reginfo struct) - */ - if (arm_current_el(env) =3D=3D 0 && !(env->cp15.sctlr_el[1] & SCTLR_UC= T)) { - return CP_ACCESS_TRAP; + int cur_el =3D arm_current_el(env); + + if (cur_el < 2) { + uint64_t hcr =3D arm_hcr_el2_eff(env); + + if (cur_el =3D=3D 0) { + if ((hcr & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)) { + if (!(env->cp15.sctlr_el[2] & SCTLR_UCT)) { + return CP_ACCESS_TRAP_EL2; + } + } else { + if (!(env->cp15.sctlr_el[1] & SCTLR_UCT)) { + return CP_ACCESS_TRAP; + } + if (hcr & HCR_TID2) { + return CP_ACCESS_TRAP_EL2; + } + } + } else if (hcr & HCR_TID2) { + return CP_ACCESS_TRAP_EL2; + } } =20 if (arm_current_el(env) < 2 && arm_hcr_el2_eff(env) & HCR_TID2) { --=20 2.20.1 From nobody Mon Feb 9 12:19:52 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580586211256426.3256813414738; Sat, 1 Feb 2020 11:43:31 -0800 (PST) Received: from localhost ([::1]:49834 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixyfy-00045U-6T for importer@patchew.org; Sat, 01 Feb 2020 14:43:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58818) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixySk-0007hm-Cw for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:51 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ixySj-0006vd-2T for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:50 -0500 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:32834) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ixySi-0006v1-SC for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:49 -0500 Received: by mail-pg1-x541.google.com with SMTP id 6so5497281pgk.0 for ; Sat, 01 Feb 2020 11:29:48 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id l7sm3668509pga.27.2020.02.01.11.29.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Feb 2020 11:29:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6fBYDBbBGzGCNAPDa08PxtCmB4d0j+1WV/uHW0dOHhc=; b=QvzshMOjxjCSBWhWmZCUNiXyko1+WoscNQpcmJoGxQ0bpvjlvnDmhhhlJNaUwe5Ywo x0GvCJGamy2EJDMqWfwc7En0eTPlo2w3vzj+GgRrNRK7K/UeHaHleZ/WbQjviis4Zubq DMKqfv133v3FKdENCV/qJtrBnTxEljdT4EsDhyprournUlSCpMjacOUKteYoBhB7HHgt 1V6K1wcWTtVtJis4Tca3OBo9+wpUceim5e6iiEKRKeDL+1KFEcVo22e/vxYuXuRuRTJR FRkxqzC8C6plnXQc//VtO9VFKRzGGtpq4tam4SEj9SI4ttuB60cU8CQ7W0bc1zpHxT3T /ycQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6fBYDBbBGzGCNAPDa08PxtCmB4d0j+1WV/uHW0dOHhc=; b=fXp+zdhUkM9UIn59RHIW+YJr3+ssBHPltDtnalzSNUBLoD1TwHm+U1+59TzzzJJzcS T60dVVEjWrwyRSpLengLJRSlrzCi+zxm5BUAIP+1bOz6Pz95r04CIZHODc+l1fAymbzQ seO3+INAuTokB+IRaqlc0RSoA3EkkpIb6iz8D50YsgJ17fFGL8JptYtxAaDilUfHNetG XL1TuN80vQcegt7sQO4noe9YEOPyJcLapYVFG5cmirFzrF/1sRHYaBm6oaPQ/HCouk5m KQkwT6j8Us2ydiAV8P6A92ABfyMU4BpHwvIuSB5o4aBpJbzN+6RjcYPw7lf7iKF4lsNy 80aQ== X-Gm-Message-State: APjAAAW+yqPi32Oj8bxCrGDI+TPypE4WewSknuw0p1tFyD7pDCP9HwR1 8P2NiW3oaAhKZ/UGLAZI5IS3qYdepkM= X-Google-Smtp-Source: APXvYqxArT+X0Y1EpG2gE/X1MOg+TszlqyUGl4+wX2BpdmtSjtMHxAKo0EQMrwINcfR2nDjrOY0kzA== X-Received: by 2002:a63:f70e:: with SMTP id x14mr4397266pgh.71.1580585387721; Sat, 01 Feb 2020 11:29:47 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 25/41] target/arm: Add the hypervisor virtual counter Date: Sat, 1 Feb 2020 11:29:00 -0800 Message-Id: <20200201192916.31796-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200201192916.31796-1-richard.henderson@linaro.org> References: <20200201192916.31796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- target/arm/cpu-qom.h | 1 + target/arm/cpu.h | 11 +++++---- target/arm/cpu.c | 3 ++- target/arm/helper.c | 56 ++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 65 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index 7f5b244bde..3a9d31ea9d 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -76,6 +76,7 @@ void arm_gt_ptimer_cb(void *opaque); void arm_gt_vtimer_cb(void *opaque); void arm_gt_htimer_cb(void *opaque); void arm_gt_stimer_cb(void *opaque); +void arm_gt_hvtimer_cb(void *opaque); =20 #define ARM_AFF0_SHIFT 0 #define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 68e11f0eda..ded1e8e0a8 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -144,11 +144,12 @@ typedef struct ARMGenericTimer { uint64_t ctl; /* Timer Control register */ } ARMGenericTimer; =20 -#define GTIMER_PHYS 0 -#define GTIMER_VIRT 1 -#define GTIMER_HYP 2 -#define GTIMER_SEC 3 -#define NUM_GTIMERS 4 +#define GTIMER_PHYS 0 +#define GTIMER_VIRT 1 +#define GTIMER_HYP 2 +#define GTIMER_SEC 3 +#define GTIMER_HYPVIRT 4 +#define NUM_GTIMERS 5 =20 typedef struct { uint64_t raw_tcr; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index f86e71a260..1ecf2adb6a 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1272,7 +1272,6 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) } } =20 - { uint64_t scale; =20 @@ -1295,6 +1294,8 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) arm_gt_htimer_cb, cpu); cpu->gt_timer[GTIMER_SEC] =3D timer_new(QEMU_CLOCK_VIRTUAL, scale, arm_gt_stimer_cb, cpu); + cpu->gt_timer[GTIMER_HYPVIRT] =3D timer_new(QEMU_CLOCK_VIRTUAL, sc= ale, + arm_gt_hvtimer_cb, cpu); } #endif =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index 72b336e3b5..996865a3a2 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2556,6 +2556,7 @@ static uint64_t gt_tval_read(CPUARMState *env, const = ARMCPRegInfo *ri, =20 switch (timeridx) { case GTIMER_VIRT: + case GTIMER_HYPVIRT: offset =3D gt_virt_cnt_offset(env); break; } @@ -2572,6 +2573,7 @@ static void gt_tval_write(CPUARMState *env, const ARM= CPRegInfo *ri, =20 switch (timeridx) { case GTIMER_VIRT: + case GTIMER_HYPVIRT: offset =3D gt_virt_cnt_offset(env); break; } @@ -2727,6 +2729,34 @@ static void gt_sec_ctl_write(CPUARMState *env, const= ARMCPRegInfo *ri, gt_ctl_write(env, ri, GTIMER_SEC, value); } =20 +static void gt_hv_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) +{ + gt_timer_reset(env, ri, GTIMER_HYPVIRT); +} + +static void gt_hv_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + gt_cval_write(env, ri, GTIMER_HYPVIRT, value); +} + +static uint64_t gt_hv_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return gt_tval_read(env, ri, GTIMER_HYPVIRT); +} + +static void gt_hv_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + gt_tval_write(env, ri, GTIMER_HYPVIRT, value); +} + +static void gt_hv_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + gt_ctl_write(env, ri, GTIMER_HYPVIRT, value); +} + void arm_gt_ptimer_cb(void *opaque) { ARMCPU *cpu =3D opaque; @@ -2755,6 +2785,13 @@ void arm_gt_stimer_cb(void *opaque) gt_recalc_timer(cpu, GTIMER_SEC); } =20 +void arm_gt_hvtimer_cb(void *opaque) +{ + ARMCPU *cpu =3D opaque; + + gt_recalc_timer(cpu, GTIMER_HYPVIRT); +} + static void arm_gt_cntfrq_reset(CPUARMState *env, const ARMCPRegInfo *opaq= ue) { ARMCPU *cpu =3D env_archcpu(env); @@ -6164,6 +6201,25 @@ static const ARMCPRegInfo vhe_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 1, .access =3D PL2_RW, .writefn =3D vmsa_tcr_ttbr_el2_write, .fieldoffset =3D offsetof(CPUARMState, cp15.ttbr1_el[2]) }, +#ifndef CONFIG_USER_ONLY + { .name =3D "CNTHV_CVAL_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 3, .opc2 =3D 2, + .fieldoffset =3D + offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYPVIRT].cval), + .type =3D ARM_CP_IO, .access =3D PL2_RW, + .writefn =3D gt_hv_cval_write, .raw_writefn =3D raw_write }, + { .name =3D "CNTHV_TVAL_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 3, .opc2 =3D 0, + .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL2_RW, + .resetfn =3D gt_hv_timer_reset, + .readfn =3D gt_hv_tval_read, .writefn =3D gt_hv_tval_write }, + { .name =3D "CNTHV_CTL_EL2", .state =3D ARM_CP_STATE_BOTH, + .type =3D ARM_CP_IO, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 3, .opc2 =3D 1, + .access =3D PL2_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYPVIRT= ].ctl), + .writefn =3D gt_hv_ctl_write, .raw_writefn =3D raw_write }, +#endif REGINFO_SENTINEL }; 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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id l7sm3668509pga.27.2020.02.01.11.29.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Feb 2020 11:29:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6jzMS+VeQu48tglWZQ9BQ5nKqto6PDtfoSP2XjIUF4U=; b=C7tVNXRdzpxxe6uIjEIy4SWZgRtMpiEhroGBvmWIsHPnO5LwvFoFUxzUhkO16xgf6j eZeh9ygCl1UjMEn32BeEMOgop2JjBeJ6RcA+jAzACK/rPCLvHjMeTpxSm1XNLnQrn2D/ gUQB/2BQo+9BSGSlOK+vmT2bym1WAdjy0lDvf5hWgm2/zYPKWmfD9lxLrl/ETHz5DyEm yt3a3VdETj/I8GmXq4dj670tPQoLEra18o4GlCJ8O227v+E25m1jCi6cRPALW3EH2jYo 2A9Dxe3KKVXDv1fRhT9nR+qvNYbJHo0XcT2ZkMCkqgWlrcZwB4YXZ/oIYH81EPfPgPST +Ybg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6jzMS+VeQu48tglWZQ9BQ5nKqto6PDtfoSP2XjIUF4U=; b=NPQSXaoHUY2oDH5yXV+bHkhsvWoo4sw6MSH+1aysQuXr6tUJXNis6sB0uRP5Qt/WGr AkPS/r/IyXTvNqLoWhQPNfHlW8CVZ+WyqwB8TOnSYOrqmHOHXZO8N8aWv860A0gIQFZE +CHV2GzJ6e6n5hkTfCOb3/T3YDfnl1L6aZQZw7SxHaJDgz8WylxSqRyonPOcy6XRYuoT Xq2bOTcsuba5BqfbK7XeZ2/LT9jpUUFrOQ5cTVHuSg8l9BHrqQdR73BGhS3iW5FC2pZa rPG1Blo3oGVmxR/0wQ26p7usFaOzR4lp6+vq1r7RVRg4Au7mkRggluRN3JoYpYxasqok lPgg== X-Gm-Message-State: APjAAAXCBD5ah6/EK6HlcYRJ+JSH0Ualxi2OgCSGtd5RmjGyovj0R22e eLMVS5YRwxwNhuVImCpr70pnljBiSlk= X-Google-Smtp-Source: APXvYqzt82klEZhvKobG2umKWhhVdIOIPdhk6/DtEIbdyDRwUFdepmjk072UynKw783VDWrHcqELmg== X-Received: by 2002:a17:90a:fd85:: with SMTP id cx5mr19848663pjb.80.1580585388902; Sat, 01 Feb 2020 11:29:48 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 26/41] target/arm: Update timer access for VHE Date: Sat, 1 Feb 2020 11:29:01 -0800 Message-Id: <20200201192916.31796-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200201192916.31796-1-richard.henderson@linaro.org> References: <20200201192916.31796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- target/arm/helper.c | 102 +++++++++++++++++++++++++++++++++++--------- 1 file changed, 81 insertions(+), 21 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 996865a3a2..992ab2a15f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2324,10 +2324,18 @@ static CPAccessResult gt_cntfrq_access(CPUARMState = *env, const ARMCPRegInfo *ri, * Writable only at the highest implemented exception level. */ int el =3D arm_current_el(env); + uint64_t hcr; + uint32_t cntkctl; =20 switch (el) { case 0: - if (!extract32(env->cp15.c14_cntkctl, 0, 2)) { + hcr =3D arm_hcr_el2_eff(env); + if ((hcr & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)) { + cntkctl =3D env->cp15.cnthctl_el2; + } else { + cntkctl =3D env->cp15.c14_cntkctl; + } + if (!extract32(cntkctl, 0, 2)) { return CP_ACCESS_TRAP; } break; @@ -2355,17 +2363,47 @@ static CPAccessResult gt_counter_access(CPUARMState= *env, int timeridx, { unsigned int cur_el =3D arm_current_el(env); bool secure =3D arm_is_secure(env); + uint64_t hcr =3D arm_hcr_el2_eff(env); =20 - /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */ - if (cur_el =3D=3D 0 && - !extract32(env->cp15.c14_cntkctl, timeridx, 1)) { - return CP_ACCESS_TRAP; - } + switch (cur_el) { + case 0: + /* If HCR_EL2. =3D=3D '11': check CNTHCTL_EL2.EL0[PV]CTEN= . */ + if ((hcr & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)) { + return (extract32(env->cp15.cnthctl_el2, timeridx, 1) + ? CP_ACCESS_OK : CP_ACCESS_TRAP_EL2); + } =20 - if (arm_feature(env, ARM_FEATURE_EL2) && - timeridx =3D=3D GTIMER_PHYS && !secure && cur_el < 2 && - !extract32(env->cp15.cnthctl_el2, 0, 1)) { - return CP_ACCESS_TRAP_EL2; + /* CNT[PV]CT: not visible from PL0 if EL0[PV]CTEN is zero */ + if (!extract32(env->cp15.c14_cntkctl, timeridx, 1)) { + return CP_ACCESS_TRAP; + } + + /* If HCR_EL2. =3D=3D '10': check CNTHCTL_EL2.EL1PCTEN. */ + if (hcr & HCR_E2H) { + if (timeridx =3D=3D GTIMER_PHYS && + !extract32(env->cp15.cnthctl_el2, 10, 1)) { + return CP_ACCESS_TRAP_EL2; + } + } else { + /* If HCR_EL2. =3D=3D 0: check CNTHCTL_EL2.EL1PCEN. */ + if (arm_feature(env, ARM_FEATURE_EL2) && + timeridx =3D=3D GTIMER_PHYS && !secure && + !extract32(env->cp15.cnthctl_el2, 1, 1)) { + return CP_ACCESS_TRAP_EL2; + } + } + break; + + case 1: + /* Check CNTHCTL_EL2.EL1PCTEN, which changes location based on E2H= . */ + if (arm_feature(env, ARM_FEATURE_EL2) && + timeridx =3D=3D GTIMER_PHYS && !secure && + (hcr & HCR_E2H + ? !extract32(env->cp15.cnthctl_el2, 10, 1) + : !extract32(env->cp15.cnthctl_el2, 0, 1))) { + return CP_ACCESS_TRAP_EL2; + } + break; } return CP_ACCESS_OK; } @@ -2375,19 +2413,41 @@ static CPAccessResult gt_timer_access(CPUARMState *= env, int timeridx, { unsigned int cur_el =3D arm_current_el(env); bool secure =3D arm_is_secure(env); + uint64_t hcr =3D arm_hcr_el2_eff(env); =20 - /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if - * EL0[PV]TEN is zero. - */ - if (cur_el =3D=3D 0 && - !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) { - return CP_ACCESS_TRAP; - } + switch (cur_el) { + case 0: + if ((hcr & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)) { + /* If HCR_EL2. =3D=3D '11': check CNTHCTL_EL2.EL0[PV]= TEN. */ + return (extract32(env->cp15.cnthctl_el2, 9 - timeridx, 1) + ? CP_ACCESS_OK : CP_ACCESS_TRAP_EL2); + } =20 - if (arm_feature(env, ARM_FEATURE_EL2) && - timeridx =3D=3D GTIMER_PHYS && !secure && cur_el < 2 && - !extract32(env->cp15.cnthctl_el2, 1, 1)) { - return CP_ACCESS_TRAP_EL2; + /* + * CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from + * EL0 if EL0[PV]TEN is zero. + */ + if (!extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) { + return CP_ACCESS_TRAP; + } + /* fall through */ + + case 1: + if (arm_feature(env, ARM_FEATURE_EL2) && + timeridx =3D=3D GTIMER_PHYS && !secure) { + if (hcr & HCR_E2H) { + /* If HCR_EL2. =3D=3D '10': check CNTHCTL_EL2.EL1= PTEN. */ + if (!extract32(env->cp15.cnthctl_el2, 11, 1)) { + return CP_ACCESS_TRAP_EL2; + } + } else { + /* If HCR_EL2. =3D=3D 0: check CNTHCTL_EL2.EL1PCEN. */ + if (!extract32(env->cp15.cnthctl_el2, 1, 1)) { + return CP_ACCESS_TRAP_EL2; + } + } + } + break; } return CP_ACCESS_OK; } --=20 2.20.1 From nobody Mon Feb 9 12:19:52 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580586449272812.0276517047411; Sat, 1 Feb 2020 11:47:29 -0800 (PST) Received: from localhost ([::1]:50026 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixyjo-0001eX-6K for importer@patchew.org; Sat, 01 Feb 2020 14:47:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58844) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixySn-0007lL-0j for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ixySm-0006yW-5Y for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:52 -0500 Received: from mail-pf1-x442.google.com ([2607:f8b0:4864:20::442]:45191) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ixySm-0006xM-0Q for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:52 -0500 Received: by mail-pf1-x442.google.com with SMTP id 2so5254483pfg.12 for ; Sat, 01 Feb 2020 11:29:51 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id l7sm3668509pga.27.2020.02.01.11.29.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Feb 2020 11:29:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=R5MdH0QSS5QR9LjDBIPxSmfGJkuxTedNapCxShIB2BQ=; b=BGM+maJ/M91rj6IrfmdQO8CxB3GZp1aw60k8UKn0K5aH/SNug0si/Eq6xyfz90mVDe bELX5qaUxMOwZh8WYPoD0dzjJLct0KbE7Io4IaqyKR16rYKrrR1stbr+zWSUP5abm8SH oz3k020J91SCx3wUEKF2NP0tvZbVlCDjK1o9hFY9zbpWkpN1Qo492ZOy7ZYCh42Zd7Oj /zvU8X0Cu5XJViDxhibwFGKWtgkHtVhNckgrIJpcemvHzmRSnaO6iT1DwTn0XLftr+lO ylct6TZ9bbikQegjyT3o1gTxBtnfPiOEzDkngJ4zJC/1G/bQt1hGCSBUqpnQnfS+6lfx HM1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=R5MdH0QSS5QR9LjDBIPxSmfGJkuxTedNapCxShIB2BQ=; b=CWKu2lIWz6OO4Sg8oE6SEltrODFlC8izGblac3NNrgFOobkQaLejzf1XZiXrA9qjtX cvC0f0jeu9fBBDh4sbEYBGU3GNHRKOn7P5RzhKreeguZvwLtj45t7F8zthl2VORJZisQ Cl14MenxMKtvwieF/B+q0ianqqM1kBlOvZI61Q54UuqYu6+NafvjPtRBnVc6Zah/zYMF RHHC2QiH361CET/5q/6QYpy8VziM9zDeHY53HJ58dNQ8JuPDIihQWkmhQUZxqR5R7nJb tpAcWjsNum6230WIao/A6j/7PlZdwT8r7Ppml8Nmu7o13FE+YpOSVe0SJ1rWufsKTTdb HPvA== X-Gm-Message-State: APjAAAWq4ANvz4uQaEOAyD+LKGw6TDrTX96ahf9u1fkdtY1gj1wIOugy KFGd3J1tPiUy5iJHa/Bitlql6CWzgYA= X-Google-Smtp-Source: APXvYqz1bQ83tJRmSVEDUgww5RNQTUnUsEkdoZCzM5iznaZjPIE1wWkd02RlFnUw6ZMyTdcJqqANUA== X-Received: by 2002:a63:ec49:: with SMTP id r9mr13361103pgj.445.1580585390120; Sat, 01 Feb 2020 11:29:50 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 27/41] target/arm: Update define_one_arm_cp_reg_with_opaque for VHE Date: Sat, 1 Feb 2020 11:29:02 -0800 Message-Id: <20200201192916.31796-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200201192916.31796-1-richard.henderson@linaro.org> References: <20200201192916.31796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" For ARMv8.1, op1 =3D=3D 5 is reserved for EL2 aliases of EL1 and EL0 registers. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- target/arm/helper.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 992ab2a15f..2aa04d0613 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7586,13 +7586,10 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, mask =3D PL0_RW; break; case 4: + case 5: /* min_EL EL2 */ mask =3D PL2_RW; break; - case 5: - /* unallocated encoding, so not possible */ - assert(false); - break; case 6: /* min_EL EL3 */ mask =3D PL3_RW; --=20 2.20.1 From nobody Mon Feb 9 12:19:52 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580586533519535.2526039957211; Sat, 1 Feb 2020 11:48:53 -0800 (PST) Received: from localhost ([::1]:50058 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixylA-0004AW-F4 for importer@patchew.org; Sat, 01 Feb 2020 14:48:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58861) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixySp-0007nE-1G for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ixySn-0006zV-85 for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:54 -0500 Received: from mail-pl1-x642.google.com ([2607:f8b0:4864:20::642]:32876) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ixySn-0006yq-0L for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:53 -0500 Received: by mail-pl1-x642.google.com with SMTP id ay11so4185563plb.0 for ; Sat, 01 Feb 2020 11:29:52 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id l7sm3668509pga.27.2020.02.01.11.29.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Feb 2020 11:29:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=D7t2ViJaEx2/xVLIPebZKCECTUtY8kzuVl1NGNJav/g=; b=OuWDXYKr3MOu4zrxtxMQ6LduS03zVJ45QLQgHq8Fd67uVq3guWSFLRFKRJi2eu561d ZD7ZriYtRFBLQAzwR6dHAbN0Dlqihgj/xmO522oVL1QxDMo4PPIUGB7WWEp+WSR0ibjO nWdk/u3C3v+E++tX/CwDjlzVNyaBFvs6ZzYOid9aFRAqrGMpkvw5FDwr9VaA9UpV76k5 cOLerm96Id1oc1RrWSwJj7EWCMTU/PjPTOWeqI/2+hIU3lCGr8oBofYvOUbIDZe89c/2 Qf22yKo0tamHBlfD7pSDNClRds92Jk1rdUD7AI+j5e3rs0c4vVqVmqmMNXrl6oNK1WrG 2yBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=D7t2ViJaEx2/xVLIPebZKCECTUtY8kzuVl1NGNJav/g=; b=Ujem6S/8GxkQYVffRrZlrWxi2dUkgvkyNMpfDn6dqCKonmAS56si+zo5sQDyMQNaNk BwvlTU41OzuUUci5Y9jUstuTAb4hUAuu3IP9sOQqSpjEYpBdUbGSGce+iAabebEzUYiN w0G+zGuSHwoyt1sOr6jun2XQsT0lBtWfGPmpbwY4CA4LWC7fNF6YWKI4HXSTV2E1Y3LC +OZ4iF+sRLVfCZFzPmP3Q7ByOAMAy5AAyKLz5foNLV7nY6ZZpj2E7RiFc2PtRbITqIw8 e7gDjkNlLmdNuESqXhtteYP7c4uW8vRedgFJV8r5YYr5ChV7+HlY3NE+ubjmHOy2S3I7 OUtg== X-Gm-Message-State: APjAAAVY81eTviqEo9bD7oWX4nsTjFFlT0/0RPeCuEWf7gRP5jH1o288 34nMLEV9DpW6m/Zgwjvj6I2HfWbmkAk= X-Google-Smtp-Source: APXvYqwpIixpXCY8OkGJbC1DZudYTqzpbN4iCYkEjvtQ78Q9EY/1WLi1Fh9liqnD4Z5ySSkzABLEpQ== X-Received: by 2002:a17:90a:d103:: with SMTP id l3mr20733093pju.116.1580585391411; Sat, 01 Feb 2020 11:29:51 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 28/41] target/arm: Add VHE system register redirection and aliasing Date: Sat, 1 Feb 2020 11:29:03 -0800 Message-Id: <20200201192916.31796-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200201192916.31796-1-richard.henderson@linaro.org> References: <20200201192916.31796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Several of the EL1/0 registers are redirected to the EL2 version when in EL2 and HCR_EL2.E2H is set. Many of these registers have side effects. Link together the two ARMCPRegInfo structures after they have been properly instantiated. Install common dispatch routines to all of the relevant registers. The same set of registers that are redirected also have additional EL12/EL02 aliases created to access the original register that was redirected. Omit the generic timer registers from redirection here, because we'll need multiple kinds of redirection from both EL0 and EL2. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- v5: Drop unioning in ARMCPRegInfo with bank_fieldoffsets[]. v6: Adjust spelling of new_reg access adjustment (pmm). --- target/arm/cpu.h | 13 ++++ target/arm/helper.c | 162 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 175 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ded1e8e0a8..d091a7e2e8 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2576,6 +2576,19 @@ struct ARMCPRegInfo { * fieldoffset is 0 then no reset will be done. */ CPResetFn *resetfn; + + /* + * "Original" writefn and readfn. + * For ARMv8.1-VHE register aliases, we overwrite the read/write + * accessor functions of various EL1/EL0 to perform the runtime + * check for which sysreg should actually be modified, and then + * forwards the operation. Before overwriting the accessors, + * the original function is copied here, so that accesses that + * really do go to the EL1/EL0 version proceed normally. + * (The corresponding EL2 register is linked via opaque.) + */ + CPReadFn *orig_readfn; + CPWriteFn *orig_writefn; }; =20 /* Macros which are lvalues for the field in CPUARMState for the diff --git a/target/arm/helper.c b/target/arm/helper.c index 2aa04d0613..8f7620f243 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5358,6 +5358,158 @@ static const ARMCPRegInfo el3_cp_reginfo[] =3D { REGINFO_SENTINEL }; =20 +#ifndef CONFIG_USER_ONLY +/* Test if system register redirection is to occur in the current state. = */ +static bool redirect_for_e2h(CPUARMState *env) +{ + return arm_current_el(env) =3D=3D 2 && (arm_hcr_el2_eff(env) & HCR_E2H= ); +} + +static uint64_t el2_e2h_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + CPReadFn *readfn; + + if (redirect_for_e2h(env)) { + /* Switch to the saved EL2 version of the register. */ + ri =3D ri->opaque; + readfn =3D ri->readfn; + } else { + readfn =3D ri->orig_readfn; + } + if (readfn =3D=3D NULL) { + readfn =3D raw_read; + } + return readfn(env, ri); +} + +static void el2_e2h_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + CPWriteFn *writefn; + + if (redirect_for_e2h(env)) { + /* Switch to the saved EL2 version of the register. */ + ri =3D ri->opaque; + writefn =3D ri->writefn; + } else { + writefn =3D ri->orig_writefn; + } + if (writefn =3D=3D NULL) { + writefn =3D raw_write; + } + writefn(env, ri, value); +} + +static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu) +{ + struct E2HAlias { + uint32_t src_key, dst_key, new_key; + const char *src_name, *dst_name, *new_name; + bool (*feature)(const ARMISARegisters *id); + }; + +#define K(op0, op1, crn, crm, op2) \ + ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2) + + static const struct E2HAlias aliases[] =3D { + { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0), + "SCTLR", "SCTLR_EL2", "SCTLR_EL12" }, + { K(3, 0, 1, 0, 2), K(3, 4, 1, 1, 2), K(3, 5, 1, 0, 2), + "CPACR", "CPTR_EL2", "CPACR_EL12" }, + { K(3, 0, 2, 0, 0), K(3, 4, 2, 0, 0), K(3, 5, 2, 0, 0), + "TTBR0_EL1", "TTBR0_EL2", "TTBR0_EL12" }, + { K(3, 0, 2, 0, 1), K(3, 4, 2, 0, 1), K(3, 5, 2, 0, 1), + "TTBR1_EL1", "TTBR1_EL2", "TTBR1_EL12" }, + { K(3, 0, 2, 0, 2), K(3, 4, 2, 0, 2), K(3, 5, 2, 0, 2), + "TCR_EL1", "TCR_EL2", "TCR_EL12" }, + { K(3, 0, 4, 0, 0), K(3, 4, 4, 0, 0), K(3, 5, 4, 0, 0), + "SPSR_EL1", "SPSR_EL2", "SPSR_EL12" }, + { K(3, 0, 4, 0, 1), K(3, 4, 4, 0, 1), K(3, 5, 4, 0, 1), + "ELR_EL1", "ELR_EL2", "ELR_EL12" }, + { K(3, 0, 5, 1, 0), K(3, 4, 5, 1, 0), K(3, 5, 5, 1, 0), + "AFSR0_EL1", "AFSR0_EL2", "AFSR0_EL12" }, + { K(3, 0, 5, 1, 1), K(3, 4, 5, 1, 1), K(3, 5, 5, 1, 1), + "AFSR1_EL1", "AFSR1_EL2", "AFSR1_EL12" }, + { K(3, 0, 5, 2, 0), K(3, 4, 5, 2, 0), K(3, 5, 5, 2, 0), + "ESR_EL1", "ESR_EL2", "ESR_EL12" }, + { K(3, 0, 6, 0, 0), K(3, 4, 6, 0, 0), K(3, 5, 6, 0, 0), + "FAR_EL1", "FAR_EL2", "FAR_EL12" }, + { K(3, 0, 10, 2, 0), K(3, 4, 10, 2, 0), K(3, 5, 10, 2, 0), + "MAIR_EL1", "MAIR_EL2", "MAIR_EL12" }, + { K(3, 0, 10, 3, 0), K(3, 4, 10, 3, 0), K(3, 5, 10, 3, 0), + "AMAIR0", "AMAIR_EL2", "AMAIR_EL12" }, + { K(3, 0, 12, 0, 0), K(3, 4, 12, 0, 0), K(3, 5, 12, 0, 0), + "VBAR", "VBAR_EL2", "VBAR_EL12" }, + { K(3, 0, 13, 0, 1), K(3, 4, 13, 0, 1), K(3, 5, 13, 0, 1), + "CONTEXTIDR_EL1", "CONTEXTIDR_EL2", "CONTEXTIDR_EL12" }, + { K(3, 0, 14, 1, 0), K(3, 4, 14, 1, 0), K(3, 5, 14, 1, 0), + "CNTKCTL", "CNTHCTL_EL2", "CNTKCTL_EL12" }, + + /* + * Note that redirection of ZCR is mentioned in the description + * of ZCR_EL2, and aliasing in the description of ZCR_EL1, but + * not in the summary table. + */ + { K(3, 0, 1, 2, 0), K(3, 4, 1, 2, 0), K(3, 5, 1, 2, 0), + "ZCR_EL1", "ZCR_EL2", "ZCR_EL12", isar_feature_aa64_sve }, + + /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */ + /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */ + }; +#undef K + + size_t i; + + for (i =3D 0; i < ARRAY_SIZE(aliases); i++) { + const struct E2HAlias *a =3D &aliases[i]; + ARMCPRegInfo *src_reg, *dst_reg; + + if (a->feature && !a->feature(&cpu->isar)) { + continue; + } + + src_reg =3D g_hash_table_lookup(cpu->cp_regs, &a->src_key); + dst_reg =3D g_hash_table_lookup(cpu->cp_regs, &a->dst_key); + g_assert(src_reg !=3D NULL); + g_assert(dst_reg !=3D NULL); + + /* Cross-compare names to detect typos in the keys. */ + g_assert(strcmp(src_reg->name, a->src_name) =3D=3D 0); + g_assert(strcmp(dst_reg->name, a->dst_name) =3D=3D 0); + + /* None of the core system registers use opaque; we will. */ + g_assert(src_reg->opaque =3D=3D NULL); + + /* Create alias before redirection so we dup the right data. */ + if (a->new_key) { + ARMCPRegInfo *new_reg =3D g_memdup(src_reg, sizeof(ARMCPRegInf= o)); + uint32_t *new_key =3D g_memdup(&a->new_key, sizeof(uint32_t)); + bool ok; + + new_reg->name =3D a->new_name; + new_reg->type |=3D ARM_CP_ALIAS; + /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */ + new_reg->access &=3D PL2_RW | PL3_RW; + + ok =3D g_hash_table_insert(cpu->cp_regs, new_key, new_reg); + g_assert(ok); + } + + src_reg->opaque =3D dst_reg; + src_reg->orig_readfn =3D src_reg->readfn ?: raw_read; + src_reg->orig_writefn =3D src_reg->writefn ?: raw_write; + if (!src_reg->raw_readfn) { + src_reg->raw_readfn =3D raw_read; + } + if (!src_reg->raw_writefn) { + src_reg->raw_writefn =3D raw_write; + } + src_reg->readfn =3D el2_e2h_read; + src_reg->writefn =3D el2_e2h_write; + } +} +#endif + static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo = *ri, bool isread) { @@ -7291,6 +7443,16 @@ void register_cp_regs_for_features(ARMCPU *cpu) : cpu_isar_feature(aa32_predinv, cpu)) { define_arm_cp_regs(cpu, predinv_reginfo); } + +#ifndef CONFIG_USER_ONLY + /* + * Register redirections and aliases must be done last, + * after the registers from the other extensions have been defined. + */ + if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu= )) { + define_arm_vh_e2h_redirects_aliases(cpu); + } +#endif } =20 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) --=20 2.20.1 From nobody Mon Feb 9 12:19:52 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580586605532121.96045470177387; Sat, 1 Feb 2020 11:50:05 -0800 (PST) Received: from localhost ([::1]:50098 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixymJ-0006sm-Eu for importer@patchew.org; Sat, 01 Feb 2020 14:50:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58875) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixySq-0007oe-7q for qemu-devel@nongnu.org; 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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id l7sm3668509pga.27.2020.02.01.11.29.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Feb 2020 11:29:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xEp3G9Z4tlD+VkbVR4maUsZfgEKKo0OJRi7NU/oKVGc=; b=sfjR5ArqaUWU4Oo7vqphMbxmvemjrYJyRNA5KhT2jsO97U/KTDUv+vJ3TwpBg2uVuq 3s+AqUghlH41UAEkUjzj8mzQ97NDOBxZ/awxhnrMiSKLUfQEPb6IIl6h9IPdEfSk/8Gt YguTMuqx6nbT9yvpcNBBd4T59gukKaldVJfzQJNTNYVoakyKhQz6qCjF5U6O2mTal3gx fyt7wAktcOyXXMktuMXKXa7sQbROWRpTR0XCxPbtby0W6NiVhUUbu2pvErbDcR5UfKfB YS6vYk/Ajwg35e6CBH0iNhBDU45l4yEk4HcqVf2wzNIA8jiwbd4dGfKwS7TFIknwXv+L h+rQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xEp3G9Z4tlD+VkbVR4maUsZfgEKKo0OJRi7NU/oKVGc=; b=FpC1jRNruC7pFR0wxbroxxNLatM9kUl50ciNxTRqQpFJvlrEB+EUIGxKE1SPchVMgj /6omKkWAg9AMSsBXyyNXCCgeZTwOMJbgjSUVXF/6/6cAo4MdXJ6O3vKptGfJ8Atz49PP aq8h+iUU1WUp5FOMAt/Q6zL+wkLPmkgQVXKLG/JkIKlrxve5rcJCbQaxmKRdJQd2AusM o5lVnlxvsVB0B3TOE8aLv3OSQGGN+ob/UcZ08RMJZZA2Ljy34tdH5EfELo1TjfLPu/PG 6JMGJ/2CtstC7tLjoiRejM1XQySznGMB5J1kfp0S5/HpyDYKhkE6XzKUzIl47mJAiaJ1 3w8Q== X-Gm-Message-State: APjAAAVFem3Tj3TgBZb8qPL6ZpA+Swe5a3n0V4fqj3DAkIECprasI1K5 eC5G2Mtd5l2jnRywZ9EYhyXBGjquFsI= X-Google-Smtp-Source: APXvYqyZ0oU5yiuhxnDD8y3ljOxTWgvvuiTU5Ei2euEVNSuorAC4VJIiC5vuBMtvH8h74Ni1g+vnJA== X-Received: by 2002:a17:90a:332e:: with SMTP id m43mr19937404pjb.107.1580585392376; Sat, 01 Feb 2020 11:29:52 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 29/41] target/arm: Add VHE timer register redirection and aliasing Date: Sat, 1 Feb 2020 11:29:04 -0800 Message-Id: <20200201192916.31796-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200201192916.31796-1-richard.henderson@linaro.org> References: <20200201192916.31796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1043 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Apart from the wholesale redirection that HCR_EL2.E2H performs for EL2, there's a separate redirection specific to the timers that happens for EL0 when running in the EL2&0 regime. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- target/arm/helper.c | 181 +++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 169 insertions(+), 12 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 8f7620f243..cfa6ce59dc 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2695,6 +2695,70 @@ static void gt_phys_ctl_write(CPUARMState *env, cons= t ARMCPRegInfo *ri, gt_ctl_write(env, ri, GTIMER_PHYS, value); } =20 +static int gt_phys_redir_timeridx(CPUARMState *env) +{ + switch (arm_mmu_idx(env)) { + case ARMMMUIdx_E20_0: + case ARMMMUIdx_E20_2: + return GTIMER_HYP; + default: + return GTIMER_PHYS; + } +} + +static int gt_virt_redir_timeridx(CPUARMState *env) +{ + switch (arm_mmu_idx(env)) { + case ARMMMUIdx_E20_0: + case ARMMMUIdx_E20_2: + return GTIMER_HYPVIRT; + default: + return GTIMER_VIRT; + } +} + +static uint64_t gt_phys_redir_cval_read(CPUARMState *env, + const ARMCPRegInfo *ri) +{ + int timeridx =3D gt_phys_redir_timeridx(env); + return env->cp15.c14_timer[timeridx].cval; +} + +static void gt_phys_redir_cval_write(CPUARMState *env, const ARMCPRegInfo = *ri, + uint64_t value) +{ + int timeridx =3D gt_phys_redir_timeridx(env); + gt_cval_write(env, ri, timeridx, value); +} + +static uint64_t gt_phys_redir_tval_read(CPUARMState *env, + const ARMCPRegInfo *ri) +{ + int timeridx =3D gt_phys_redir_timeridx(env); + return gt_tval_read(env, ri, timeridx); +} + +static void gt_phys_redir_tval_write(CPUARMState *env, const ARMCPRegInfo = *ri, + uint64_t value) +{ + int timeridx =3D gt_phys_redir_timeridx(env); + gt_tval_write(env, ri, timeridx, value); +} + +static uint64_t gt_phys_redir_ctl_read(CPUARMState *env, + const ARMCPRegInfo *ri) +{ + int timeridx =3D gt_phys_redir_timeridx(env); + return env->cp15.c14_timer[timeridx].ctl; +} + +static void gt_phys_redir_ctl_write(CPUARMState *env, const ARMCPRegInfo *= ri, + uint64_t value) +{ + int timeridx =3D gt_phys_redir_timeridx(env); + gt_ctl_write(env, ri, timeridx, value); +} + static void gt_virt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) { gt_timer_reset(env, ri, GTIMER_VIRT); @@ -2733,6 +2797,48 @@ static void gt_cntvoff_write(CPUARMState *env, const= ARMCPRegInfo *ri, gt_recalc_timer(cpu, GTIMER_VIRT); } =20 +static uint64_t gt_virt_redir_cval_read(CPUARMState *env, + const ARMCPRegInfo *ri) +{ + int timeridx =3D gt_virt_redir_timeridx(env); + return env->cp15.c14_timer[timeridx].cval; +} + +static void gt_virt_redir_cval_write(CPUARMState *env, const ARMCPRegInfo = *ri, + uint64_t value) +{ + int timeridx =3D gt_virt_redir_timeridx(env); + gt_cval_write(env, ri, timeridx, value); +} + +static uint64_t gt_virt_redir_tval_read(CPUARMState *env, + const ARMCPRegInfo *ri) +{ + int timeridx =3D gt_virt_redir_timeridx(env); + return gt_tval_read(env, ri, timeridx); +} + +static void gt_virt_redir_tval_write(CPUARMState *env, const ARMCPRegInfo = *ri, + uint64_t value) +{ + int timeridx =3D gt_virt_redir_timeridx(env); + gt_tval_write(env, ri, timeridx, value); +} + +static uint64_t gt_virt_redir_ctl_read(CPUARMState *env, + const ARMCPRegInfo *ri) +{ + int timeridx =3D gt_virt_redir_timeridx(env); + return env->cp15.c14_timer[timeridx].ctl; +} + +static void gt_virt_redir_ctl_write(CPUARMState *env, const ARMCPRegInfo *= ri, + uint64_t value) +{ + int timeridx =3D gt_virt_redir_timeridx(env); + gt_ctl_write(env, ri, timeridx, value); +} + static void gt_hyp_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) { gt_timer_reset(env, ri, GTIMER_HYP); @@ -2889,7 +2995,8 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = =3D { .accessfn =3D gt_ptimer_access, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl), - .writefn =3D gt_phys_ctl_write, .raw_writefn =3D raw_write, + .readfn =3D gt_phys_redir_ctl_read, .raw_readfn =3D raw_read, + .writefn =3D gt_phys_redir_ctl_write, .raw_writefn =3D raw_write, }, { .name =3D "CNTP_CTL_S", .cp =3D 15, .crn =3D 14, .crm =3D 2, .opc1 =3D 0, .opc2 =3D 1, @@ -2906,14 +3013,16 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[= ] =3D { .accessfn =3D gt_ptimer_access, .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].c= tl), .resetvalue =3D 0, - .writefn =3D gt_phys_ctl_write, .raw_writefn =3D raw_write, + .readfn =3D gt_phys_redir_ctl_read, .raw_readfn =3D raw_read, + .writefn =3D gt_phys_redir_ctl_write, .raw_writefn =3D raw_write, }, { .name =3D "CNTV_CTL", .cp =3D 15, .crn =3D 14, .crm =3D 3, .opc1 =3D= 0, .opc2 =3D 1, .type =3D ARM_CP_IO | ARM_CP_ALIAS, .access =3D PL0_RW, .accessfn =3D gt_vtimer_access, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl), - .writefn =3D gt_virt_ctl_write, .raw_writefn =3D raw_write, + .readfn =3D gt_virt_redir_ctl_read, .raw_readfn =3D raw_read, + .writefn =3D gt_virt_redir_ctl_write, .raw_writefn =3D raw_write, }, { .name =3D "CNTV_CTL_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 3, .opc2 =3D 1, @@ -2921,14 +3030,15 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[= ] =3D { .accessfn =3D gt_vtimer_access, .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].c= tl), .resetvalue =3D 0, - .writefn =3D gt_virt_ctl_write, .raw_writefn =3D raw_write, + .readfn =3D gt_virt_redir_ctl_read, .raw_readfn =3D raw_read, + .writefn =3D gt_virt_redir_ctl_write, .raw_writefn =3D raw_write, }, /* TimerValue views: a 32 bit downcounting view of the underlying stat= e */ { .name =3D "CNTP_TVAL", .cp =3D 15, .crn =3D 14, .crm =3D 2, .opc1 = =3D 0, .opc2 =3D 0, .secure =3D ARM_CP_SECSTATE_NS, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL0_RW, .accessfn =3D gt_ptimer_access, - .readfn =3D gt_phys_tval_read, .writefn =3D gt_phys_tval_write, + .readfn =3D gt_phys_redir_tval_read, .writefn =3D gt_phys_redir_tval= _write, }, { .name =3D "CNTP_TVAL_S", .cp =3D 15, .crn =3D 14, .crm =3D 2, .opc1 =3D 0, .opc2 =3D 0, @@ -2941,18 +3051,18 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[= ] =3D { .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 2, .opc2 =3D 0, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL0_RW, .accessfn =3D gt_ptimer_access, .resetfn =3D gt_phys_timer_reset, - .readfn =3D gt_phys_tval_read, .writefn =3D gt_phys_tval_write, + .readfn =3D gt_phys_redir_tval_read, .writefn =3D gt_phys_redir_tval= _write, }, { .name =3D "CNTV_TVAL", .cp =3D 15, .crn =3D 14, .crm =3D 3, .opc1 = =3D 0, .opc2 =3D 0, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL0_RW, .accessfn =3D gt_vtimer_access, - .readfn =3D gt_virt_tval_read, .writefn =3D gt_virt_tval_write, + .readfn =3D gt_virt_redir_tval_read, .writefn =3D gt_virt_redir_tval= _write, }, { .name =3D "CNTV_TVAL_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 3, .opc2 =3D 0, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL0_RW, .accessfn =3D gt_vtimer_access, .resetfn =3D gt_virt_timer_reset, - .readfn =3D gt_virt_tval_read, .writefn =3D gt_virt_tval_write, + .readfn =3D gt_virt_redir_tval_read, .writefn =3D gt_virt_redir_tval= _write, }, /* The counter itself */ { .name =3D "CNTPCT", .cp =3D 15, .crm =3D 14, .opc1 =3D 0, @@ -2982,7 +3092,8 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = =3D { .type =3D ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].c= val), .accessfn =3D gt_ptimer_access, - .writefn =3D gt_phys_cval_write, .raw_writefn =3D raw_write, + .readfn =3D gt_phys_redir_cval_read, .raw_readfn =3D raw_read, + .writefn =3D gt_phys_redir_cval_write, .raw_writefn =3D raw_write, }, { .name =3D "CNTP_CVAL_S", .cp =3D 15, .crm =3D 14, .opc1 =3D 2, .secure =3D ARM_CP_SECSTATE_S, @@ -2998,14 +3109,16 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[= ] =3D { .type =3D ARM_CP_IO, .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].c= val), .resetvalue =3D 0, .accessfn =3D gt_ptimer_access, - .writefn =3D gt_phys_cval_write, .raw_writefn =3D raw_write, + .readfn =3D gt_phys_redir_cval_read, .raw_readfn =3D raw_read, + .writefn =3D gt_phys_redir_cval_write, .raw_writefn =3D raw_write, }, { .name =3D "CNTV_CVAL", .cp =3D 15, .crm =3D 14, .opc1 =3D 3, .access =3D PL0_RW, .type =3D ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].c= val), .accessfn =3D gt_vtimer_access, - .writefn =3D gt_virt_cval_write, .raw_writefn =3D raw_write, + .readfn =3D gt_virt_redir_cval_read, .raw_readfn =3D raw_read, + .writefn =3D gt_virt_redir_cval_write, .raw_writefn =3D raw_write, }, { .name =3D "CNTV_CVAL_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 3, .opc2 =3D 2, @@ -3013,7 +3126,8 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = =3D { .type =3D ARM_CP_IO, .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].c= val), .resetvalue =3D 0, .accessfn =3D gt_vtimer_access, - .writefn =3D gt_virt_cval_write, .raw_writefn =3D raw_write, + .readfn =3D gt_virt_redir_cval_read, .raw_readfn =3D raw_read, + .writefn =3D gt_virt_redir_cval_write, .raw_writefn =3D raw_write, }, /* Secure timer -- this is actually restricted to only EL3 * and configurably Secure-EL1 via the accessfn. @@ -3044,6 +3158,15 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[]= =3D { REGINFO_SENTINEL }; =20 +static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + if (!(arm_hcr_el2_eff(env) & HCR_E2H)) { + return CP_ACCESS_TRAP; + } + return CP_ACCESS_OK; +} + #else =20 /* In user-mode most of the generic timer registers are inaccessible @@ -6431,6 +6554,40 @@ static const ARMCPRegInfo vhe_reginfo[] =3D { .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYPVIRT= ].ctl), .writefn =3D gt_hv_ctl_write, .raw_writefn =3D raw_write }, + { .name =3D "CNTP_CTL_EL02", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 5, .crn =3D 14, .crm =3D 2, .opc2 =3D 1, + .type =3D ARM_CP_IO | ARM_CP_ALIAS, + .access =3D PL2_RW, .accessfn =3D e2h_access, + .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].c= tl), + .writefn =3D gt_phys_ctl_write, .raw_writefn =3D raw_write }, + { .name =3D "CNTV_CTL_EL02", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 5, .crn =3D 14, .crm =3D 3, .opc2 =3D 1, + .type =3D ARM_CP_IO | ARM_CP_ALIAS, + .access =3D PL2_RW, .accessfn =3D e2h_access, + .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].c= tl), + .writefn =3D gt_virt_ctl_write, .raw_writefn =3D raw_write }, + { .name =3D "CNTP_TVAL_EL02", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 5, .crn =3D 14, .crm =3D 2, .opc2 =3D 0, + .type =3D ARM_CP_NO_RAW | ARM_CP_IO | ARM_CP_ALIAS, + .access =3D PL2_RW, .accessfn =3D e2h_access, + .readfn =3D gt_phys_tval_read, .writefn =3D gt_phys_tval_write }, + { .name =3D "CNTV_TVAL_EL02", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 5, .crn =3D 14, .crm =3D 3, .opc2 =3D 0, + .type =3D ARM_CP_NO_RAW | ARM_CP_IO | ARM_CP_ALIAS, + .access =3D PL2_RW, .accessfn =3D e2h_access, + .readfn =3D gt_virt_tval_read, .writefn =3D gt_virt_tval_write }, + { .name =3D "CNTP_CVAL_EL02", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 5, .crn =3D 14, .crm =3D 2, .opc2 =3D 2, + .type =3D ARM_CP_IO | ARM_CP_ALIAS, + .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].c= val), + .access =3D PL2_RW, .accessfn =3D e2h_access, + .writefn =3D gt_phys_cval_write, .raw_writefn =3D raw_write }, + { .name =3D "CNTV_CVAL_EL02", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 5, .crn =3D 14, .crm =3D 3, .opc2 =3D 2, + .type =3D ARM_CP_IO | ARM_CP_ALIAS, + .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].c= val), + .access =3D PL2_RW, .accessfn =3D e2h_access, + .writefn =3D gt_virt_cval_write, .raw_writefn =3D raw_write }, #endif REGINFO_SENTINEL }; --=20 2.20.1 From nobody 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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id l7sm3668509pga.27.2020.02.01.11.29.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Feb 2020 11:29:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MOQeWRomrPDFg8FXKVWMJui75ucXzLZW3uSDCABTB9c=; b=A64BgSml2Rn8pLxcwWWoSNTnJiW3VCCBWG8V0j6DFe4gqEoVQ0VY9hhCyKHHylr/bL 5v15q7X7rsg97iU3wIunOjW3WdME6qHK9ftk2xo66VVvV9mvOnfS7h+YOmuab0DT3Nsl lzPuCZ8mOhvJGEH9yiH8yPBwEKksAI9AjyMEhksTFXrNt3Jff6ZMRO9YjY2vOvwxrO7S weXEU69MEyOpz8f7iOYYmF6aehkDzpupXOPIx7fbrMhTeCxHJ3eY4cJjcs+olKowQQqY PdcrmLnduiNGsOJSVyWna2gpl3ihkKxuaCO5Yh9R53IVZK/0NzZM9oqBc4jFMFS2RuVn Bn2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MOQeWRomrPDFg8FXKVWMJui75ucXzLZW3uSDCABTB9c=; b=Yjw5lXmfYF+HxoVjsPqnfBuzL8YM1Pa6aFLFSxfmU/vmM6maTOHGUuVvqd1/A4NQEi 7Rlid8bWBxZbG5BGm65bsu6yRPHnqzIAxfJFmiOTvQSm9mEHjq3bYw0lATllrDo5dhHg wM3gSqymWN2xe8VDaXJSaCNnIWUjJDQ9QZhjT+F32fc7AR2YkqO2qeeMHUXcqsZUgr7U TFfLh1fIA2hc9rsBJE1odCaTACoV/s8iveQbna5xmKY3+korYesl3ETPBwTweAmB6qi5 RHuU4V86LtP7atpESXTT9UdrqSRknR1qfSlu/RJOL9u0lsIQNXREaBbuI02gH1U0ChMt 26Ow== X-Gm-Message-State: APjAAAUuQ0YCYazko4+KmID4rUqdMFe1aqz43x6BN9FXz75Be4DZ7vWf OFNnvG5yzzbEl/qh0246FwdFAe3n4/4= X-Google-Smtp-Source: APXvYqyPGYzv5A1wRvu7n2HJQWcXwB42A0vFb0HUpvH7eMi0serrCQWidCkHdIvwP2nf2xOzz/Ertg== X-Received: by 2002:a17:90a:a881:: with SMTP id h1mr19904912pjq.50.1580585393274; Sat, 01 Feb 2020 11:29:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 30/41] target/arm: Flush tlb for ASID changes in EL2&0 translation regime Date: Sat, 1 Feb 2020 11:29:05 -0800 Message-Id: <20200201192916.31796-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200201192916.31796-1-richard.henderson@linaro.org> References: <20200201192916.31796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Since we only support a single ASID, flush the tlb when it changes. Note that TCR_EL2, like TCR_EL1, has the A1 bit that chooses between the two TTBR* registers for the location of the ASID. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- target/arm/helper.c | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index cfa6ce59dc..f9be6b052f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3763,7 +3763,7 @@ static void vmsa_ttbcr_reset(CPUARMState *env, const = ARMCPRegInfo *ri) tcr->base_mask =3D 0xffffc000u; } =20 -static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, +static void vmsa_tcr_el12_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { ARMCPU *cpu =3D env_archcpu(env); @@ -3789,7 +3789,17 @@ static void vmsa_ttbr_write(CPUARMState *env, const = ARMCPRegInfo *ri, static void vmsa_tcr_ttbr_el2_write(CPUARMState *env, const ARMCPRegInfo *= ri, uint64_t value) { - /* TODO: There are ASID fields in here with HCR_EL2.E2H */ + /* + * If we are running with E2&0 regime, then an ASID is active. + * Flush if that might be changing. Note we're not checking + * TCR_EL2.A1 to know if this is really the TTBRx_EL2 that + * holds the active ASID, only checking the field that might. + */ + if (extract64(raw_read(env, ri) ^ value, 48, 16) && + (arm_hcr_el2_eff(env) & HCR_E2H)) { + tlb_flush_by_mmuidx(env_cpu(env), + ARMMMUIdxBit_E20_2 | ARMMMUIdxBit_E20_0); + } raw_write(env, ri, value); } =20 @@ -3849,7 +3859,7 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] =3D { offsetof(CPUARMState, cp15.ttbr1_ns) } }, { .name =3D "TCR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .crn =3D 2, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 2, - .access =3D PL1_RW, .writefn =3D vmsa_tcr_el1_write, + .access =3D PL1_RW, .writefn =3D vmsa_tcr_el12_write, .resetfn =3D vmsa_ttbcr_reset, .raw_writefn =3D raw_write, .fieldoffset =3D offsetof(CPUARMState, cp15.tcr_el[1]) }, { .name =3D "TTBCR", .cp =3D 15, .crn =3D 2, .crm =3D 0, .opc1 =3D 0, = .opc2 =3D 2, @@ -5175,10 +5185,8 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { .resetvalue =3D 0 }, { .name =3D "TCR_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 2, - .access =3D PL2_RW, - /* no .writefn needed as this can't cause an ASID change; - * no .raw_writefn or .resetfn needed as we never use mask/base_mask - */ + .access =3D PL2_RW, .writefn =3D vmsa_tcr_el12_write, + /* no .raw_writefn or .resetfn needed as we never use mask/base_mask= */ .fieldoffset =3D offsetof(CPUARMState, cp15.tcr_el[2]) }, { .name =3D "VTCR", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 4, .crn =3D 2, .crm =3D 1, .opc2 =3D 2, --=20 2.20.1 From nobody Mon Feb 9 12:19:52 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580586605557441.44238008005595; Sat, 1 Feb 2020 11:50:05 -0800 (PST) Received: from localhost ([::1]:50102 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixymJ-0006tg-H1 for importer@patchew.org; Sat, 01 Feb 2020 14:50:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58894) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixySr-0007qT-Gu for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ixySp-00071s-UN for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:57 -0500 Received: from mail-pl1-x641.google.com ([2607:f8b0:4864:20::641]:43533) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ixySp-00071D-OE for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:55 -0500 Received: by mail-pl1-x641.google.com with SMTP id p11so4173023plq.10 for ; Sat, 01 Feb 2020 11:29:55 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id l7sm3668509pga.27.2020.02.01.11.29.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Feb 2020 11:29:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Lx6/vKYYp72gTf4UzAbSPEaYbohru43Bb1YVjGxSPOk=; b=VTXjsKOXLLDWu/8fnM+GyNmzUeqOH2g+GM6CPoaywnMdCUnVIfGuLd65u3xaYez5kr FpKS+8oLi3frkPErtqgorMxAuUUea+OEdPdyzHLPOZ5NEo0SFKmfvlD1aCCX8ghzVQfL 4lhMbBuSfkhLm51PJqMIvcZS3fywxMwTQxL4AGVB3pK6fVrAvuevijYZKzKupXvDMxVK JngcWJgCZWiYy5Jl3qPbsMXqVJmPIUoXnvO/jRSoRKY1cQM6QOu+E1IXhcbUADpUZDLo 7K93pXS+t1VLEmFJtTigNPk480XRh0TdjsrYTurAeC67scUU3UWDA9eEsvaUwkrichAx LAuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Lx6/vKYYp72gTf4UzAbSPEaYbohru43Bb1YVjGxSPOk=; b=ZdKVppyhK3I2zZLfbz1VLohWlF2PhZk0M0tf7zOYkfMrp1j7AyeU6mQP4DL3d+2PU9 R29T3TZWWaX+6KmgwPuW2XwxAkvPMbVn1aDtAJTn4J3THdqeeQPzDvzfd148E2sxqrmc sz2fcRPhsrlCmuIB2keIF+OVDnthdAThrONbyQcYtYqDmyYWeSSO7PYE7iA3nVWwJA5V WGxnemIJBWPSm82GfOvcYme5eCqtJ82TVHqMkHOh873qryrNWiLmnosd9nzBP8CN7K36 W5INk9tPGEqj68B5Yvk1pGmzJP3rSGlwarA++ywb7odnyKvlnvwPKiPjdcRK8QQyf7VE OLpA== X-Gm-Message-State: APjAAAUhfJ5B0n1qt2t/E9JPPtgGwWSZO1PH20/gG0ZQz5wrs3MVsAkM oEq13r/di2G6cGcxsxQDWqntB01Ve3M= X-Google-Smtp-Source: APXvYqw3Quxvlf+KoHLVh7anwxb+t9irTmm6KkeZ61Xt8zeaYnS3mfCBukLr9WAkhxEjgrti0Muaqw== X-Received: by 2002:a17:90a:858c:: with SMTP id m12mr18764534pjn.127.1580585394346; Sat, 01 Feb 2020 11:29:54 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 31/41] target/arm: Flush tlbs for E2&0 translation regime Date: Sat, 1 Feb 2020 11:29:06 -0800 Message-Id: <20200201192916.31796-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200201192916.31796-1-richard.henderson@linaro.org> References: <20200201192916.31796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- v5: Flush all EL2 regimes with TLBI ALLE2 (pmm). --- target/arm/helper.c | 34 +++++++++++++++++++++++++++------- 1 file changed, 27 insertions(+), 7 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index f9be6b052f..0e2278b5aa 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4174,8 +4174,12 @@ static CPAccessResult aa64_cacheop_access(CPUARMStat= e *env, =20 static int vae1_tlbmask(CPUARMState *env) { + /* Since we exclude secure first, we may read HCR_EL2 directly. */ if (arm_is_secure_below_el3(env)) { return ARMMMUIdxBit_SE10_1 | ARMMMUIdxBit_SE10_0; + } else if ((env->cp15.hcr_el2 & (HCR_E2H | HCR_TGE)) + =3D=3D (HCR_E2H | HCR_TGE)) { + return ARMMMUIdxBit_E20_2 | ARMMMUIdxBit_E20_0; } else { return ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_0; } @@ -4219,6 +4223,12 @@ static int alle1_tlbmask(CPUARMState *env) } } =20 +static int alle2_tlbmask(CPUARMState *env) +{ + /* TODO: ARMv8.4-SecEL2 */ + return ARMMMUIdxBit_E20_0 | ARMMMUIdxBit_E20_2 | ARMMMUIdxBit_E2; +} + static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -4231,10 +4241,10 @@ static void tlbi_aa64_alle1_write(CPUARMState *env,= const ARMCPRegInfo *ri, static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu =3D env_archcpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); + int mask =3D alle2_tlbmask(env); =20 - tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E2); + tlb_flush_by_mmuidx(cs, mask); } =20 static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -4259,8 +4269,9 @@ static void tlbi_aa64_alle2is_write(CPUARMState *env,= const ARMCPRegInfo *ri, uint64_t value) { CPUState *cs =3D env_cpu(env); + int mask =3D alle2_tlbmask(env); =20 - tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E2); + tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); } =20 static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *= ri, @@ -4271,6 +4282,15 @@ static void tlbi_aa64_alle3is_write(CPUARMState *env= , const ARMCPRegInfo *ri, tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_SE3); } =20 +static int vae2_tlbmask(CPUARMState *env) +{ + if (arm_hcr_el2_eff(env) & HCR_E2H) { + return ARMMMUIdxBit_E20_0 | ARMMMUIdxBit_E20_2; + } else { + return ARMMMUIdxBit_E2; + } +} + static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -4278,11 +4298,11 @@ static void tlbi_aa64_vae2_write(CPUARMState *env, = const ARMCPRegInfo *ri, * Currently handles both VAE2 and VALE2, since we don't support * flush-last-level-only. */ - ARMCPU *cpu =3D env_archcpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); + int mask =3D vae2_tlbmask(env); uint64_t pageaddr =3D sextract64(value << 12, 0, 56); =20 - tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E2); + tlb_flush_page_by_mmuidx(cs, pageaddr, mask); } =20 static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri, --=20 2.20.1 From nobody Mon Feb 9 12:19:52 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580585986137261.2781734100838; Sat, 1 Feb 2020 11:39:46 -0800 (PST) Received: from localhost ([::1]:49464 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixycH-0006Cq-WA for importer@patchew.org; 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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id l7sm3668509pga.27.2020.02.01.11.29.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Feb 2020 11:29:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6o/uTqZDgskKImMCIDRtOPtsiJkqQrRQkaycCllMO/w=; b=nDYWcW9qbUqnb9DTbtrc4hGb0pgHjRIT6uFUczq6Wcg559NmlA+ARDjPXVy184fIP7 7m6Ju7sGc1v1U0rLPtAV4whOQ49SovByILP/agSBY21caYg1uR/ypCvmzsYWNLDROejO +nlcWL+XuJY3v3YMLOLneJNqd4HF5dls3sbdbL4DZZZMODX4iZaH1mxb0zlKOu5U5vl2 iJplUhruQ57voy4Z9c+aLTJObPPi7bV+bwq5h09UdKjDQOPYchffjMkkU6yEQwk0MT2+ gY9Q+TP8BiVdbIIjwmyF50h2UvMJmfgxB2KYTe6YqTcnmafb5yS7ttCebD+2EfEY/h/t 36cw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6o/uTqZDgskKImMCIDRtOPtsiJkqQrRQkaycCllMO/w=; b=fXCSiOd340ZsLHef8brosolaOt6CByLQVbz9f4/hMoXVIIkgNbAkFt9mNApi8p5ams d42/Bo0UlDz45aI55/ZcDHkL9JZAUVK2psTxIo51Ikm+8COFh/Ue5REu2fK+BYfxUyxU UHE/gt5kseG6+QBNLPp3zyK2HGeXXd0S/Qi1Pa8zliwSXvlIsYS0vmIGAPcNBFv44U6D 5br04VTDIfMJemuxUvjzly546iMqBEAtfw8tQxnZxq6yjK+jEEoemE8b5lCn4+tA0ztn Izp3s5KLOeSFzWdAPq3he2MvbLLj2mWoFF298vFetdW1G78Q8i4Laea66M6RaKoF8T6m nbUw== X-Gm-Message-State: APjAAAVwozSz7CFIU01yeH2uJSGQ7mChz2lQMPQJl9JaTUMKFM03kuLm Gq4M0TODvIDCu8oia96aOYcR8YspkLM= X-Google-Smtp-Source: APXvYqy/1J+wgRC/8xLqd0OH8RbrboBYKxgBxyCL7IG07kEGGUqgCuCwDWbnbu7ggNb2TnfAe24+ew== X-Received: by 2002:a63:4b24:: with SMTP id y36mr16677131pga.176.1580585395499; Sat, 01 Feb 2020 11:29:55 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 32/41] target/arm: Update arm_phys_excp_target_el for TGE Date: Sat, 1 Feb 2020 11:29:07 -0800 Message-Id: <20200201192916.31796-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200201192916.31796-1-richard.henderson@linaro.org> References: <20200201192916.31796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The TGE bit routes all asynchronous exceptions to EL2. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- target/arm/helper.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 0e2278b5aa..c239711641 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8455,6 +8455,12 @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint3= 2_t excp_idx, break; }; =20 + /* + * For these purposes, TGE and AMO/IMO/FMO both force the + * interrupt to EL2. Fold TGE into the bit extracted above. + */ + hcr |=3D (hcr_el2 & HCR_TGE) !=3D 0; + /* Perform a table-lookup for the target EL given the current state */ target_el =3D target_el_table[is64][scr][rw][hcr][secure][cur_el]; =20 --=20 2.20.1 From nobody Mon Feb 9 12:19:52 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580586699115164.50128676497752; Sat, 1 Feb 2020 11:51:39 -0800 (PST) Received: from localhost ([::1]:50154 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixynq-0000xM-3v for importer@patchew.org; Sat, 01 Feb 2020 14:51:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58924) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixySt-0007s1-Oc for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:30:02 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ixySs-000748-A6 for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:59 -0500 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:33888) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ixySs-00073g-4S for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:58 -0500 Received: by mail-pg1-x541.google.com with SMTP id j4so5489935pgi.1 for ; Sat, 01 Feb 2020 11:29:58 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id l7sm3668509pga.27.2020.02.01.11.29.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Feb 2020 11:29:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pksT15NnMmE71deplHUWkkiaf3u2bzdhxWoWyV+vt64=; b=TbUDZ4zYBzixMyqtYQi31CiqcQdjidvoGxIISNrbLAxl0Ey0ZrUi0Hav4FgbUBaAXY Zb6ZrMkjyeIuzq7V1/pufwsk+oJY0undvJVwpoc1nfxoC6bPqxzlFZf/hqA2rmHuU9C5 h66f0RCoJKtA9dSsIRZd1Zu2FcZac6iwmerYUIKV5HpT/zC24Ebdx2pgSBjgahGPg0DS h1II7aOlCWnJn7NaJr6en4BbiUauSgoQdc5vol0mGvY6kEiPHwADENBKQVvXuamjs/K3 7ohuA9v1wDv294CqpXri3tBu4tr/Vz0JpOEpsLASW7fnyFQYypV+yhrAfpTuCyK3A0Jx kjNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pksT15NnMmE71deplHUWkkiaf3u2bzdhxWoWyV+vt64=; b=PXnqkjH1yUQH2EyWWg+oWbihbfpJJfjnCxEh5NalaJjcW1+VJKE3NpjB53fMn9yWXJ wa6hAUUvxZYSIF7T+I1qezTLDT7JYGkWwMRTHeTaWQ0zfE2OveZKiI8PK96iAgRn4007 FuL8ry8F1H91ZuAUa4AaHhtBxymsnzPnl32lGYQs0NhC20RabBYRuFCra5ehx9pmdcpe PGqmMBK1phXPnvJwSm4f3Lf1YviQ6SReGEpGcD1D57g/Nqv3mnRMfHkftidg69oPXbfX RIgtLdKRtwxsj8AA53Cbof667FMkw3VG/DV7iwX65N8tzKutvmt7+fXsGp37xVvrdF07 6nzg== X-Gm-Message-State: APjAAAXf65m93DdaGwoQi9kLsNaqvvpC+JPGzPO1C90qw+sTS551yb3v VQmf4Fokl1C4ALAjSfTTgvrqU3cksY4= X-Google-Smtp-Source: APXvYqwE+DIcGUMBFPYg+JEz1gx3SXZ8jZNwjEYBX4pfOKZ7I3CtMqZv2kG6elL5b61qxyLtbrVJiw== X-Received: by 2002:a62:e719:: with SMTP id s25mr15339208pfh.40.1580585396929; Sat, 01 Feb 2020 11:29:56 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 33/41] target/arm: Update {fp,sve}_exception_el for VHE Date: Sat, 1 Feb 2020 11:29:08 -0800 Message-Id: <20200201192916.31796-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200201192916.31796-1-richard.henderson@linaro.org> References: <20200201192916.31796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" When TGE+E2H are both set, CPACR_EL1 is ignored. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- target/arm/helper.c | 53 ++++++++++++++++++++++++--------------------- 1 file changed, 28 insertions(+), 25 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index c239711641..5b4e83adfd 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5800,7 +5800,9 @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] =3D= { int sve_exception_el(CPUARMState *env, int el) { #ifndef CONFIG_USER_ONLY - if (el <=3D 1) { + uint64_t hcr_el2 =3D arm_hcr_el2_eff(env); + + if (el <=3D 1 && (hcr_el2 & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HCR_T= GE)) { bool disabled =3D false; =20 /* The CPACR.ZEN controls traps to EL1: @@ -5815,8 +5817,7 @@ int sve_exception_el(CPUARMState *env, int el) } if (disabled) { /* route_to_el2 */ - return (arm_feature(env, ARM_FEATURE_EL2) - && (arm_hcr_el2_eff(env) & HCR_TGE) ? 2 : 1); + return hcr_el2 & HCR_TGE ? 2 : 1; } =20 /* Check CPACR.FPEN. */ @@ -11700,8 +11701,6 @@ uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val,= uint32_t bytes) int fp_exception_el(CPUARMState *env, int cur_el) { #ifndef CONFIG_USER_ONLY - int fpen; - /* CPACR and the CPTR registers don't exist before v6, so FP is * always accessible */ @@ -11729,30 +11728,34 @@ int fp_exception_el(CPUARMState *env, int cur_el) * 0, 2 : trap EL0 and EL1/PL1 accesses * 1 : trap only EL0 accesses * 3 : trap no accesses + * This register is ignored if E2H+TGE are both set. */ - fpen =3D extract32(env->cp15.cpacr_el1, 20, 2); - switch (fpen) { - case 0: - case 2: - if (cur_el =3D=3D 0 || cur_el =3D=3D 1) { - /* Trap to PL1, which might be EL1 or EL3 */ - if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { + if ((arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HCR_T= GE)) { + int fpen =3D extract32(env->cp15.cpacr_el1, 20, 2); + + switch (fpen) { + case 0: + case 2: + if (cur_el =3D=3D 0 || cur_el =3D=3D 1) { + /* Trap to PL1, which might be EL1 or EL3 */ + if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { + return 3; + } + return 1; + } + if (cur_el =3D=3D 3 && !is_a64(env)) { + /* Secure PL1 running at EL3 */ return 3; } - return 1; + break; + case 1: + if (cur_el =3D=3D 0) { + return 1; + } + break; + case 3: + break; } - if (cur_el =3D=3D 3 && !is_a64(env)) { - /* Secure PL1 running at EL3 */ - return 3; - } - break; - case 1: - if (cur_el =3D=3D 0) { - return 1; - } - break; - case 3: - break; } =20 /* --=20 2.20.1 From nobody Mon Feb 9 12:19:52 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580586672879108.20641540907741; Sat, 1 Feb 2020 11:51:12 -0800 (PST) Received: from localhost ([::1]:50150 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixynO-0000F8-Sd for importer@patchew.org; Sat, 01 Feb 2020 14:51:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58938) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixySw-0007tL-2u for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:30:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ixySt-00075K-TB for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:30:01 -0500 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:38107) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ixySt-00074j-NU for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:29:59 -0500 Received: by mail-pf1-x444.google.com with SMTP id x185so5269819pfc.5 for ; Sat, 01 Feb 2020 11:29:59 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id l7sm3668509pga.27.2020.02.01.11.29.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Feb 2020 11:29:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=47cVy0hqEAMv3Vw0sowdk1lwNWBNZcow7HnX+kqWQog=; b=nreHzP/AL6DR+QP+b96GKwlhvgqj9Cxv8YbY130AkFx8l/14bTJPQu2yABTz613UQ+ hDsb0my0hVLjHvjzZnwLDiI2DEIYH5Z6RVaPigj7trciHU5P7yWotSH+NZFCgtQ4D8f5 X5oAkl8IkSB3y4cNAWwbfWX9dnK+MuEYsCEY4bqq9G89N3GFOPV+KOSHpiRYTOLkYerM D/BJd8/tQnji1gog9Nw7+mt3teoidf9oti4HraBfloE6Qx1kD+phCfXqp/3rTJwL9K7x FiPG8w3/GSMVe5JPQnimPvS80CzmMTFk6gUUPALnH6KTKwWQueaK5+x+mwApYrzcbYLE l5/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=47cVy0hqEAMv3Vw0sowdk1lwNWBNZcow7HnX+kqWQog=; b=Zq4fDvoNUjB9O+jwldWNvc3uhaW2RzfPVHXO+jdnormEiEVfaITToqeZO0YQAryxYx EcG3cdx4PV2/Scuv5DUpnzPv2k+FXnD5oa9TbQEAQAcW4oHPc/jK+08Md6iGW60kT6O8 WrPN/BNNgASSePCvHhNo2N82HPN/lNC5WN1mHZghQQj2+yXtB1Yfum5p3xIx06A1gOPE +Lsxo0oaAAiLL4MV9RjRsM5x1BobledS1pF58MGA/D/a6bM8sygEj5JKyfBcNhLEFcQA DbhHVjT0NcbFM7gF7oxSxm8hmDh6yzoJql6fbav/6RpnN4d/2uArHSsaxbwkq09FOJVl yb0w== X-Gm-Message-State: APjAAAXpiovSpC/I9VnheyDAqD687amR0sSSGjWopq2oaRudjO9RYf+a ZdWv2IpESMCwbyDMZTNpfs+WCYbQeTs= X-Google-Smtp-Source: APXvYqzsFRL3zkE+0/MBuOz9nOXHlBT/I9bqDq3pIHLNjKU3cOEh3iG3wDVLb+JTjxNKDhpYyXe5ag== X-Received: by 2002:a62:1d1:: with SMTP id 200mr17257231pfb.184.1580585398151; Sat, 01 Feb 2020 11:29:58 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 34/41] target/arm: check TGE and E2H flags for EL0 pauth traps Date: Sat, 1 Feb 2020 11:29:09 -0800 Message-Id: <20200201192916.31796-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200201192916.31796-1-richard.henderson@linaro.org> References: <20200201192916.31796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Alex Benn=C3=A9e According to ARM ARM we should only trap from the EL1&0 regime. Reviewed-by: Peter Maydell Signed-off-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- target/arm/pauth_helper.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c index e0c401c4a9..9746e32bf8 100644 --- a/target/arm/pauth_helper.c +++ b/target/arm/pauth_helper.c @@ -371,7 +371,10 @@ static void pauth_check_trap(CPUARMState *env, int el,= uintptr_t ra) if (el < 2 && arm_feature(env, ARM_FEATURE_EL2)) { uint64_t hcr =3D arm_hcr_el2_eff(env); bool trap =3D !(hcr & HCR_API); - /* FIXME: ARMv8.1-VHE: trap only applies to EL1&0 regime. */ + if (el =3D=3D 0) { + /* Trap only applies to EL1&0 regime. */ + trap &=3D (hcr & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HCR_TGE); + } /* FIXME: ARMv8.3-NV: HCR_NV trap takes precedence for ERETA[AB]. = */ if (trap) { pauth_trap(env, 2, ra); --=20 2.20.1 From nobody Mon Feb 9 12:19:52 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580586266485757.1849030693089; Sat, 1 Feb 2020 11:44:26 -0800 (PST) Received: from localhost ([::1]:49954 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixygr-0005pz-Cp for importer@patchew.org; Sat, 01 Feb 2020 14:44:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58953) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixySx-0007wU-Ah for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:30:04 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ixySv-000761-Mr for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:30:03 -0500 Received: from mail-pf1-x443.google.com ([2607:f8b0:4864:20::443]:44602) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ixySv-00075W-GV for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:30:01 -0500 Received: by mail-pf1-x443.google.com with SMTP id y5so5250590pfb.11 for ; Sat, 01 Feb 2020 11:30:00 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id l7sm3668509pga.27.2020.02.01.11.29.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Feb 2020 11:29:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QA2XZyURdKBjhvISLZOjMU10Ll/7MveouJBYw/dCIfo=; b=sVAmQsVVJpZuqi6JkBXMYOew9YMQDjZ3qU3aQSdW8+3KDB4BC7HJMur7unJKPoRNmA xhvab/kC0W/BsAVC3L/NfocflVx7pF6hQbmK5Dwp9Yw7Kw1zXbFRJhSXzl1zHRrZd6cb Re/z5D4iWPmfN3W8tVatVCESYT7p9FLd81Bi/8mE/ZD6v1k/Ba12AXMcBG2Coazobr3k Fv640PDjQivpmAdy42DUAaAgrgiPJjDUv6xckQR70PkRImJtdf78EivvM8z0ojmy05aS CRIBvt647G5vemTWHN5waCHPjXhRipHemGkabCdRHOtDhOfGDfQUz4cTk+3qOSuygXM1 npIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QA2XZyURdKBjhvISLZOjMU10Ll/7MveouJBYw/dCIfo=; b=AI+0CVoWbaUv0w0CuHxwYj3lwqDoMjifD3Z/45LvsxNcer/e287HfE+0XtUQ/8yLtB +mDrnK/1c+LC3LYjpiu7obw2iSLJrCyyRY/s3p1U1GyjXJ45qH04gxOpyKY1w/nzOXu8 GgeH+8ECLbxCFleX/7iIGvnWzzJYIBWtgQ7+gjlOMlsNcCO9v5vLDPzzkvSyI4CiCSXB 0HZqyeqK8eoZwaCrG5nfNESdBTsMJYA+VHb5cSj2vOZBr5opxpjYVhsrfo/IW1BnUQuI A2n+Ita4qyOn1vaIQVRErWA9DY8pGbFXya09ecZnJx11FwYdHbvFJtgditV4B2/puEM/ LeOw== X-Gm-Message-State: APjAAAV7+OZG1u2gFkTGq38bOIkvzmlzK+vnkhqMYp5NroS7y0LcUEpG mFjnfb8Pj1BLSdqk57YZdcA8yyaSqSE= X-Google-Smtp-Source: APXvYqy6BC2meU+8gvRpQen7l8TWwxfBoRKeRBWNXqXw2ykjqTjhx2RJ0uLa0tJFIc2F8whqQmweTw== X-Received: by 2002:aa7:9edd:: with SMTP id r29mr16532029pfq.14.1580585399283; Sat, 01 Feb 2020 11:29:59 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 35/41] target/arm: Update get_a64_user_mem_index for VHE Date: Sat, 1 Feb 2020 11:29:10 -0800 Message-Id: <20200201192916.31796-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200201192916.31796-1-richard.henderson@linaro.org> References: <20200201192916.31796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The EL2&0 translation regime is affected by Load Register (unpriv). The code structure used here will facilitate later changes in this area for implementing UAO and NV. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- target/arm/cpu.h | 9 ++++---- target/arm/translate.h | 2 ++ target/arm/helper.c | 22 +++++++++++++++++++ target/arm/translate-a64.c | 44 ++++++++++++++++++++++++-------------- 4 files changed, 57 insertions(+), 20 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d091a7e2e8..2ed2667a17 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3214,10 +3214,10 @@ typedef ARMCPU ArchCPU; * | | | TBFLAG_A32 | | * | | +-----+----------+ TBFLAG_AM32 | * | TBFLAG_ANY | |TBFLAG_M32| | - * | | +-------------------------| - * | | | TBFLAG_A64 | - * +--------------+-----------+-------------------------+ - * 31 20 14 0 + * | | +-+----------+--------------| + * | | | TBFLAG_A64 | + * +--------------+---------+---------------------------+ + * 31 20 15 0 * * Unless otherwise noted, these bits are cached in env->hflags. */ @@ -3283,6 +3283,7 @@ FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) FIELD(TBFLAG_A64, BT, 9, 1) FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ FIELD(TBFLAG_A64, TBID, 12, 2) +FIELD(TBFLAG_A64, UNPRIV, 14, 1) =20 static inline bool bswap_code(bool sctlr_b) { diff --git a/target/arm/translate.h b/target/arm/translate.h index a32b6b1b3a..5b167c416a 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -73,6 +73,8 @@ typedef struct DisasContext { * ie A64 LDX*, LDAX*, A32/T32 LDREX*, LDAEX*. */ bool is_ldex; + /* True if AccType_UNPRIV should be used for LDTR et al */ + bool unpriv; /* True if v8.3-PAuth is active. */ bool pauth_active; /* True with v8.5-BTI and SCTLR_ELx.BT* set. */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 5b4e83adfd..576afd9c9e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12020,6 +12020,28 @@ static uint32_t rebuild_hflags_a64(CPUARMState *en= v, int el, int fp_el, } } =20 + /* Compute the condition for using AccType_UNPRIV for LDTR et al. */ + /* TODO: ARMv8.2-UAO */ + switch (mmu_idx) { + case ARMMMUIdx_E10_1: + case ARMMMUIdx_SE10_1: + /* TODO: ARMv8.3-NV */ + flags =3D FIELD_DP32(flags, TBFLAG_A64, UNPRIV, 1); + break; + case ARMMMUIdx_E20_2: + /* TODO: ARMv8.4-SecEL2 */ + /* + * Note that E20_2 is gated by HCR_EL2.E2H =3D=3D 1, but E20_0 is + * gated by HCR_EL2. =3D=3D '11', and so is LDTR. + */ + if (env->cp15.hcr_el2 & HCR_TGE) { + flags =3D FIELD_DP32(flags, TBFLAG_A64, UNPRIV, 1); + } + break; + default: + break; + } + return rebuild_hflags_common(env, fp_el, mmu_idx, flags); } =20 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 3982e1988d..6e82486884 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -105,25 +105,36 @@ void a64_translate_init(void) offsetof(CPUARMState, exclusive_high), "exclusive_high"); } =20 -static inline int get_a64_user_mem_index(DisasContext *s) +/* + * Return the core mmu_idx to use for A64 "unprivileged load/store" insns + */ +static int get_a64_user_mem_index(DisasContext *s) { - /* Return the core mmu_idx to use for A64 "unprivileged load/store" in= sns: - * if EL1, access as if EL0; otherwise access at current EL + /* + * If AccType_UNPRIV is not used, the insn uses AccType_NORMAL, + * which is the usual mmu_idx for this cpu state. */ - ARMMMUIdx useridx; + ARMMMUIdx useridx =3D s->mmu_idx; =20 - switch (s->mmu_idx) { - case ARMMMUIdx_E10_1: - useridx =3D ARMMMUIdx_E10_0; - break; - case ARMMMUIdx_SE10_1: - useridx =3D ARMMMUIdx_SE10_0; - break; - case ARMMMUIdx_Stage2: - g_assert_not_reached(); - default: - useridx =3D s->mmu_idx; - break; + if (s->unpriv) { + /* + * We have pre-computed the condition for AccType_UNPRIV. + * Therefore we should never get here with a mmu_idx for + * which we do not know the corresponding user mmu_idx. + */ + switch (useridx) { + case ARMMMUIdx_E10_1: + useridx =3D ARMMMUIdx_E10_0; + break; + case ARMMMUIdx_E20_2: + useridx =3D ARMMMUIdx_E20_0; + break; + case ARMMMUIdx_SE10_1: + useridx =3D ARMMMUIdx_SE10_0; + break; + default: + g_assert_not_reached(); + } } return arm_to_core_mmu_idx(useridx); } @@ -14171,6 +14182,7 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, dc->pauth_active =3D FIELD_EX32(tb_flags, TBFLAG_A64, PAUTH_ACTIVE); dc->bt =3D FIELD_EX32(tb_flags, TBFLAG_A64, BT); dc->btype =3D FIELD_EX32(tb_flags, TBFLAG_A64, BTYPE); + dc->unpriv =3D FIELD_EX32(tb_flags, TBFLAG_A64, UNPRIV); dc->vec_len =3D 0; dc->vec_stride =3D 0; dc->cp_regs =3D arm_cpu->cp_regs; --=20 2.20.1 From nobody Mon Feb 9 12:19:52 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id l7sm3668509pga.27.2020.02.01.11.29.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Feb 2020 11:29:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lOpt+tnic+DBm+8Ls3O8L5tH0MsUO+4UoXmIfqQorxk=; b=gIMVNOAMZvAeLm/G/EOxYs7gMFHuN1Gw+JwbNNFAmEQj3/p4zX8CHxgNnxT3jc982g BPTp9zeYkqloNH65FimNCBHCEXfwDQu/YJ/CvZWqlBb9QY++Wv3VXt0xOsuq1yAVj6lH VX+xPHRlpbgMa3o776H/h5hNkmtccpj5ovIPQ2i8S4/glwRrwYJqm3xVkHXr+tKeb4va MiF5uln82JS9hjF3nnOgfu0CIwB72n633qBobqzwz+W40JcRpaWbuwo+PuVokfotYkJG /C8YKhxzhBHcHY1oNpT5tGbaI95ZjPJWpW3cXk7wp5Z5ugBGPVgrS4TFtpcz9nlpLdHZ Pybg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lOpt+tnic+DBm+8Ls3O8L5tH0MsUO+4UoXmIfqQorxk=; b=kpmOal8Pf6/aeXahirdGG6ZHpzOXogBf5p0c4SY7sdZJ0d0f6HPv1jrmGDqsPCDsJz XAaQ3ZMsw7dUoaKPdbt3QmiOdkIuZMl6Mdmoc2Z5OAJqDsYbVKVfSqQqWQbJVUqbbfXW wYDeG88aUPrCEwEVAG98mwb91z6yhgi90qlyzUk8/gMJXXga+d9N0vOUZJ+EZHY7QlFK j2BSV4a81/fy/MiNN6H/GfNQDIWXGyq/rc5WzwGaqaCcnkS7adjGmeC+qHSXNcxYxSCl 7u7r/HUoIvUju8qJO2PRwWMV0DQhuf7oVWnljhi5si5CXO2IcbzKOvVD26RAQuDvuXgo q0AA== X-Gm-Message-State: APjAAAVOKQbb26F2SWKtTg4XE2LWlYvATv8F7O3UvkBgmGkJ3Z3AlotV rFlxVSO5Pzz28iR+sId5CyeAkkjhsf0= X-Google-Smtp-Source: APXvYqyFUSPZJ5IbI4cU0lt1AVIzys/mQGVk9m5nB44woO3pmQyMEoiuWIxK0UowSvv0MiIbyuiSDg== X-Received: by 2002:aa7:820d:: with SMTP id k13mr17393692pfi.10.1580585400429; Sat, 01 Feb 2020 11:30:00 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 36/41] target/arm: Update arm_cpu_do_interrupt_aarch64 for VHE Date: Sat, 1 Feb 2020 11:29:11 -0800 Message-Id: <20200201192916.31796-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200201192916.31796-1-richard.henderson@linaro.org> References: <20200201192916.31796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" When VHE is enabled, the exception level below EL2 is not EL1, but EL0, and so to identify the entry vector offset for exceptions targeting EL2 we need to look at the width of EL0, not of EL1. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- target/arm/helper.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 576afd9c9e..70b10428c5 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9026,14 +9026,19 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *= cs) * immediately lower than the target level is using AArch32 or AAr= ch64 */ bool is_aa64; + uint64_t hcr; =20 switch (new_el) { case 3: is_aa64 =3D (env->cp15.scr_el3 & SCR_RW) !=3D 0; break; case 2: - is_aa64 =3D (env->cp15.hcr_el2 & HCR_RW) !=3D 0; - break; + hcr =3D arm_hcr_el2_eff(env); + if ((hcr & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HCR_TGE)) { + is_aa64 =3D (hcr & HCR_RW) !=3D 0; + break; + } + /* fall through */ case 1: is_aa64 =3D is_a64(env); break; --=20 2.20.1 From nobody Mon Feb 9 12:19:52 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580586372573859.5951348537178; Sat, 1 Feb 2020 11:46:12 -0800 (PST) Received: from localhost ([::1]:50010 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixyiZ-0000Np-Hc for importer@patchew.org; Sat, 01 Feb 2020 14:46:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58967) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixySy-0007yh-5e for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:30:05 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ixySx-00079i-7v for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:30:04 -0500 Received: from mail-pl1-x643.google.com ([2607:f8b0:4864:20::643]:36988) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ixySx-00076n-1V for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:30:03 -0500 Received: by mail-pl1-x643.google.com with SMTP id c23so4182155plz.4 for ; Sat, 01 Feb 2020 11:30:02 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id l7sm3668509pga.27.2020.02.01.11.30.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Feb 2020 11:30:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=j8oEYEGJE/U9npgyXl/EoNuorLqJKdNjKvRjstMsLjY=; b=xMOVYksoAtkKs8TNkXMKO9UrZJIDEmUnydwZm8+q06TDK+7Cv5q1AjOlr94vaC/YnG 5UUAGhMTLuFmcWtM7EvyAfIWD1JCDuuwU10Fw6dlEzDLwr75S7udoKD9ruSXqm9ANXKp 8raoHUkK1jAFI6GbJWRT8UDdAYQD1HUYwOF2riA53/KpXiFDt0n7tCtQ1Ir7/d+1YwbJ Nz7O4n2JJLal7TnPmTJLbcXR6QD1kzWLkU5fmyzuX8miYAlYUwwOMLwsq93B2bFQ1dRN xT1HE78e9cUFXpCznEIfjaNdn3QAOPbS7eKS4fOB9N7gghDQWkNFvVxt9zO1xDP7pq2Y oaGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=j8oEYEGJE/U9npgyXl/EoNuorLqJKdNjKvRjstMsLjY=; b=TedDaicyshz2x8sHvkBUssJex2ri4fwRUlxXQud9noLmIPgAFcg2oTL/22YOOMXY6N yPNon90O8hPr98Y3o8+zZ9TB/kGZIN6pgNlkg6Dgg1OMLD2207jQkC1C+gNB24bkHjiL DAi/nkNyY4pan+jNPzrT5ynJyuBsGagwrVN9HkWQF978/edWaW97HQgw/sw6SyVRayBu CNooPgG0gIixWBsxM+Ce8DvfqkraLaVyYSlGUOyLn+dCVLBD7a6+5iJhqk1tn2wqH324 UN/Hi54T6TAHZI7Ic4L/Gbpmla5jh1yZ2Cml8miur+4hwLZWKzcod/xmcFF73xL0iB7m V3og== X-Gm-Message-State: APjAAAUEbJoudyBTJ1fX7WVtLRyCwnoxIm1aE/N6QBKbqJgFSQbP2iE3 e32d6RY4uqMJoXhRjlbI0VRu8M/grh0= X-Google-Smtp-Source: APXvYqzXu2+9x0AB09hItrPSx+76diIz6etxxO9hvlGehjrkvVhnoiXyHJsjJN7aP+Sj0/g5Ofvs+Q== X-Received: by 2002:a17:902:6809:: with SMTP id h9mr1780098plk.32.1580585401808; Sat, 01 Feb 2020 11:30:01 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 37/41] target/arm: Enable ARMv8.1-VHE in -cpu max Date: Sat, 1 Feb 2020 11:29:12 -0800 Message-Id: <20200201192916.31796-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200201192916.31796-1-richard.henderson@linaro.org> References: <20200201192916.31796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- target/arm/cpu64.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 2d97bf45e1..c80fb5fd43 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -672,6 +672,7 @@ static void aarch64_max_initfn(Object *obj) t =3D cpu->isar.id_aa64mmfr1; t =3D FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */ t =3D FIELD_DP64(t, ID_AA64MMFR1, LO, 1); + t =3D FIELD_DP64(t, ID_AA64MMFR1, VH, 1); cpu->isar.id_aa64mmfr1 =3D t; =20 /* Replicate the same data to the 32-bit id registers. */ --=20 2.20.1 From nobody Mon Feb 9 12:19:52 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580586497268686.5174288797348; Sat, 1 Feb 2020 11:48:17 -0800 (PST) Received: from localhost ([::1]:50050 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixyka-000303-49 for importer@patchew.org; Sat, 01 Feb 2020 14:48:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58992) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixyT0-00083h-DS for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:30:08 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ixySy-0007EO-Kk for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:30:06 -0500 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:43087) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ixySy-0007CI-C6 for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:30:04 -0500 Received: by mail-pf1-x444.google.com with SMTP id s1so5256271pfh.10 for ; Sat, 01 Feb 2020 11:30:04 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id l7sm3668509pga.27.2020.02.01.11.30.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Feb 2020 11:30:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lVzGvBb3SeRuII6HgwbD5FGxjB0/hye7YABhI1fpgk8=; b=Df7cjZg92RgIptZS9dHkCsrFIpcJ+xGOvxyVC9he1QdUStWiSaa5TTLqM6ScFPtDRr 4j5sEXIRLhQP9EUMGXfq7uymGtKN+YW8S53IYcMImMB6iYGNIm2wl6CKoLu6Jo81vMh3 XSnayQfmpL1umJgdhpj/4ZJ7prD+jl/k2NnrDqrEKHRaRm3mZntVd4yZkzGVL/esMS7T RoyC8of2MKvgWFK5JEEhdAm6FKrLme+txomYpHz9l1cdHYp6Yb9hjida6Zmcm/BpvAOm t7MW94QDXIZnWR8MY2T5rWgL2rHvkFmdz6j9qbRqLTO1cllNkGe5C6IF3JMqhYiztBxl pWTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lVzGvBb3SeRuII6HgwbD5FGxjB0/hye7YABhI1fpgk8=; b=ibV6pX4jo4wfl6T7QkWqHAtPPYtEcMO7fn3jECW/7WUCHOvT8rQP7OkhIyfHFCzLsw DiFIqUJNK5VfFfgi7qQ+d6fyeM92WoLRMIzEAMMXxR7ppwkQwYTrk4YHRu92y32lUXFX fIqe9lNSwYZGm6eqxnG1xdp617/0nl/dvVrwfyA8OaRwRrIByjN6mVJdKvC7ytrmA6Cd BxAqeQt5ktZ2UGKWfyo7Xx1IqBt2yAqIe4E4uqrsod/QQGrrer3XIdAsUSLIYP2mp/jQ wqIp/hhL9XAJqWN5Wh67lLDHda2E76gf/t+ZYdFqUVnYFUxSA/Z8u6bmeSZmnHNc67af mzHg== X-Gm-Message-State: APjAAAWhxGK6QY3nfw64q+UaVyvx8M9F7VGbhjT7P3e+6Pgb0on1H2eM MSPhKEzlDrGjwYGMpIOHCJpmtIVxD/0= X-Google-Smtp-Source: APXvYqzpFXcSTg3aQpFCD+F+uodfJVuODYuG2bjONaPJqABFhg9aNgzpUINhFk9YMt2rWtll4BvlGg== X-Received: by 2002:a63:f744:: with SMTP id f4mr4269609pgk.345.1580585403052; Sat, 01 Feb 2020 11:30:03 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 38/41] target/arm: Move arm_excp_unmasked to cpu.c Date: Sat, 1 Feb 2020 11:29:13 -0800 Message-Id: <20200201192916.31796-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200201192916.31796-1-richard.henderson@linaro.org> References: <20200201192916.31796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) This inline function has one user in cpu.c, and need not be exposed otherwise. Code movement only, with fixups for checkpatch. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- target/arm/cpu.h | 111 ------------------------------------------- target/arm/cpu.c | 119 +++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 119 insertions(+), 111 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 2ed2667a17..0b3036c484 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2709,117 +2709,6 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_s= ync); #define ARM_CPUID_TI915T 0x54029152 #define ARM_CPUID_TI925T 0x54029252 =20 -static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, - unsigned int target_el) -{ - CPUARMState *env =3D cs->env_ptr; - unsigned int cur_el =3D arm_current_el(env); - bool secure =3D arm_is_secure(env); - bool pstate_unmasked; - int8_t unmasked =3D 0; - uint64_t hcr_el2; - - /* Don't take exceptions if they target a lower EL. - * This check should catch any exceptions that would not be taken but = left - * pending. - */ - if (cur_el > target_el) { - return false; - } - - hcr_el2 =3D arm_hcr_el2_eff(env); - - switch (excp_idx) { - case EXCP_FIQ: - pstate_unmasked =3D !(env->daif & PSTATE_F); - break; - - case EXCP_IRQ: - pstate_unmasked =3D !(env->daif & PSTATE_I); - break; - - case EXCP_VFIQ: - if (secure || !(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { - /* VFIQs are only taken when hypervized and non-secure. */ - return false; - } - return !(env->daif & PSTATE_F); - case EXCP_VIRQ: - if (secure || !(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { - /* VIRQs are only taken when hypervized and non-secure. */ - return false; - } - return !(env->daif & PSTATE_I); - default: - g_assert_not_reached(); - } - - /* Use the target EL, current execution state and SCR/HCR settings to - * determine whether the corresponding CPSR bit is used to mask the - * interrupt. - */ - if ((target_el > cur_el) && (target_el !=3D 1)) { - /* Exceptions targeting a higher EL may not be maskable */ - if (arm_feature(env, ARM_FEATURE_AARCH64)) { - /* 64-bit masking rules are simple: exceptions to EL3 - * can't be masked, and exceptions to EL2 can only be - * masked from Secure state. The HCR and SCR settings - * don't affect the masking logic, only the interrupt routing. - */ - if (target_el =3D=3D 3 || !secure) { - unmasked =3D 1; - } - } else { - /* The old 32-bit-only environment has a more complicated - * masking setup. HCR and SCR bits not only affect interrupt - * routing but also change the behaviour of masking. - */ - bool hcr, scr; - - switch (excp_idx) { - case EXCP_FIQ: - /* If FIQs are routed to EL3 or EL2 then there are cases w= here - * we override the CPSR.F in determining if the exception = is - * masked or not. If neither of these are set then we fall= back - * to the CPSR.F setting otherwise we further assess the s= tate - * below. - */ - hcr =3D hcr_el2 & HCR_FMO; - scr =3D (env->cp15.scr_el3 & SCR_FIQ); - - /* When EL3 is 32-bit, the SCR.FW bit controls whether the - * CPSR.F bit masks FIQ interrupts when taken in non-secure - * state. If SCR.FW is set then FIQs can be masked by CPSR= .F - * when non-secure but only when FIQs are only routed to E= L3. - */ - scr =3D scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); - break; - case EXCP_IRQ: - /* When EL3 execution state is 32-bit, if HCR.IMO is set t= hen - * we may override the CPSR.I masking when in non-secure s= tate. - * The SCR.IRQ setting has already been taken into conside= ration - * when setting the target EL, so it does not have a furth= er - * affect here. - */ - hcr =3D hcr_el2 & HCR_IMO; - scr =3D false; - break; - default: - g_assert_not_reached(); - } - - if ((scr || hcr) && !secure) { - unmasked =3D 1; - } - } - } - - /* The PSTATE bits only mask the interrupt if we have not overriden the - * ability above. - */ - return unmasked || pstate_unmasked; -} - #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) #define CPU_RESOLVING_TYPE TYPE_ARM_CPU diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 1ecf2adb6a..b81ed44bd2 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -410,6 +410,125 @@ static void arm_cpu_reset(CPUState *s) arm_rebuild_hflags(env); } =20 +static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, + unsigned int target_el) +{ + CPUARMState *env =3D cs->env_ptr; + unsigned int cur_el =3D arm_current_el(env); + bool secure =3D arm_is_secure(env); + bool pstate_unmasked; + int8_t unmasked =3D 0; + uint64_t hcr_el2; + + /* + * Don't take exceptions if they target a lower EL. + * This check should catch any exceptions that would not be taken + * but left pending. + */ + if (cur_el > target_el) { + return false; + } + + hcr_el2 =3D arm_hcr_el2_eff(env); + + switch (excp_idx) { + case EXCP_FIQ: + pstate_unmasked =3D !(env->daif & PSTATE_F); + break; + + case EXCP_IRQ: + pstate_unmasked =3D !(env->daif & PSTATE_I); + break; + + case EXCP_VFIQ: + if (secure || !(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { + /* VFIQs are only taken when hypervized and non-secure. */ + return false; + } + return !(env->daif & PSTATE_F); + case EXCP_VIRQ: + if (secure || !(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { + /* VIRQs are only taken when hypervized and non-secure. */ + return false; + } + return !(env->daif & PSTATE_I); + default: + g_assert_not_reached(); + } + + /* + * Use the target EL, current execution state and SCR/HCR settings to + * determine whether the corresponding CPSR bit is used to mask the + * interrupt. + */ + if ((target_el > cur_el) && (target_el !=3D 1)) { + /* Exceptions targeting a higher EL may not be maskable */ + if (arm_feature(env, ARM_FEATURE_AARCH64)) { + /* + * 64-bit masking rules are simple: exceptions to EL3 + * can't be masked, and exceptions to EL2 can only be + * masked from Secure state. The HCR and SCR settings + * don't affect the masking logic, only the interrupt routing. + */ + if (target_el =3D=3D 3 || !secure) { + unmasked =3D 1; + } + } else { + /* + * The old 32-bit-only environment has a more complicated + * masking setup. HCR and SCR bits not only affect interrupt + * routing but also change the behaviour of masking. + */ + bool hcr, scr; + + switch (excp_idx) { + case EXCP_FIQ: + /* + * If FIQs are routed to EL3 or EL2 then there are cases w= here + * we override the CPSR.F in determining if the exception = is + * masked or not. If neither of these are set then we fall= back + * to the CPSR.F setting otherwise we further assess the s= tate + * below. + */ + hcr =3D hcr_el2 & HCR_FMO; + scr =3D (env->cp15.scr_el3 & SCR_FIQ); + + /* + * When EL3 is 32-bit, the SCR.FW bit controls whether the + * CPSR.F bit masks FIQ interrupts when taken in non-secure + * state. If SCR.FW is set then FIQs can be masked by CPSR= .F + * when non-secure but only when FIQs are only routed to E= L3. + */ + scr =3D scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); + break; + case EXCP_IRQ: + /* + * When EL3 execution state is 32-bit, if HCR.IMO is set t= hen + * we may override the CPSR.I masking when in non-secure s= tate. + * The SCR.IRQ setting has already been taken into conside= ration + * when setting the target EL, so it does not have a furth= er + * affect here. + */ + hcr =3D hcr_el2 & HCR_IMO; + scr =3D false; + break; + default: + g_assert_not_reached(); + } + + if ((scr || hcr) && !secure) { + unmasked =3D 1; + } + } + } + + /* + * The PSTATE bits only mask the interrupt if we have not overriden the + * ability above. + */ + return unmasked || pstate_unmasked; +} + bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { CPUClass *cc =3D CPU_GET_CLASS(cs); --=20 2.20.1 From nobody Mon Feb 9 12:19:52 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580586570123728.4932454331878; Sat, 1 Feb 2020 11:49:30 -0800 (PST) Received: from localhost ([::1]:50082 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixyll-0005XP-22 for importer@patchew.org; Sat, 01 Feb 2020 14:49:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58998) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixyT1-00084e-0c for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:30:08 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ixySz-0007Fx-LR for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:30:06 -0500 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:37119) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ixySz-0007Ec-FB for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:30:05 -0500 Received: by mail-pf1-x444.google.com with SMTP id p14so5273828pfn.4 for ; Sat, 01 Feb 2020 11:30:05 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id l7sm3668509pga.27.2020.02.01.11.30.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Feb 2020 11:30:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=u56IY+HRZxZx4lkNPaNYlhu3dFhpsHvask7g8ioRP78=; b=zZ9CvDnyU9pcbNVQ/2X1oYhkXancUwUOIa2ckxIXqiovtNPe5WyaacXv44bDPaiAsK xmhsp0UgCdf8PKjNAopAVTXpEcwvFlxgsY3twQUvsBgMqr6P2Qces3HetrW8z4HmbleK +2TvbaHH52RrGGlSATqtcOKmBtTXQ9o3Zmun2W7m8qGoy7upchTKie/6UeTrttsrkvcj rP/Gwsf7vg4iOdxEKJARhAp7fYNu8qS+3fir/QZdjkLO3twJJMfVcwcgY4NaW6CLQ8S0 vkkNj/U0Q24g/V0BPo5nb7ceuS9Vi41F64thfNwq9MyxSpJn9xPtuwvHnk/J/jT+jZe0 Z1TQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=u56IY+HRZxZx4lkNPaNYlhu3dFhpsHvask7g8ioRP78=; b=ZlHLc0epi/qPSCPX87AjugJxgKovgHT9dtFkmpMNAWqQh9zLR9IERLTLlNIyGLmAGU be0glCAP35U2FFeCg7fNsCXbbKvv9lHU2tFQTg5qOrxUYLLNgvB7PY8ZCtBcOEdAv3lL wMT/K0fNbzzBHU0ZwYIhgkRfkiYRXsjZ+DWOdF8/vg5OGHcGMs9n5KLGKR+yRf8cLi2P GBdhaJgS4bhyh43t4k7ppsse4wtKq1X5NldxcOSAnWRedbkomlL0FnUaWBzWWETGCtik DojDm3xSWyQ+YGS6eaP1zOpiXMYVaE4LzMiUW5ljmQhgNkhXMqz++ZOKNJlLwBo/2pLI gtJA== X-Gm-Message-State: APjAAAUVIYU7putClDG0h11HUd1xWu0DtvldDgxu1YLTTnIyS39Ct43k VlfzLDjgQWm8ukqK7s3h42j/9ADqPy4= X-Google-Smtp-Source: APXvYqwAAjgK5SXRedqTLx9P94fP4c2QVu+tKxxz2Bvq+pGU2f389ArMnDMXxyY969jiQk1TdmrDzw== X-Received: by 2002:a63:4641:: with SMTP id v1mr16547886pgk.389.1580585404268; Sat, 01 Feb 2020 11:30:04 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 39/41] target/arm: Pass more cpu state to arm_excp_unmasked Date: Sat, 1 Feb 2020 11:29:14 -0800 Message-Id: <20200201192916.31796-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200201192916.31796-1-richard.henderson@linaro.org> References: <20200201192916.31796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Avoid redundant computation of cpu state by passing it in from the caller, which has already computed it for itself. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- target/arm/cpu.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index b81ed44bd2..fcee0a2dd4 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -411,14 +411,13 @@ static void arm_cpu_reset(CPUState *s) } =20 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, - unsigned int target_el) + unsigned int target_el, + unsigned int cur_el, bool secure, + uint64_t hcr_el2) { CPUARMState *env =3D cs->env_ptr; - unsigned int cur_el =3D arm_current_el(env); - bool secure =3D arm_is_secure(env); bool pstate_unmasked; int8_t unmasked =3D 0; - uint64_t hcr_el2; =20 /* * Don't take exceptions if they target a lower EL. @@ -429,8 +428,6 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsi= gned int excp_idx, return false; } =20 - hcr_el2 =3D arm_hcr_el2_eff(env); - switch (excp_idx) { case EXCP_FIQ: pstate_unmasked =3D !(env->daif & PSTATE_F); @@ -535,6 +532,7 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt= _request) CPUARMState *env =3D cs->env_ptr; uint32_t cur_el =3D arm_current_el(env); bool secure =3D arm_is_secure(env); + uint64_t hcr_el2 =3D arm_hcr_el2_eff(env); uint32_t target_el; uint32_t excp_idx; bool ret =3D false; @@ -542,7 +540,8 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt= _request) if (interrupt_request & CPU_INTERRUPT_FIQ) { excp_idx =3D EXCP_FIQ; target_el =3D arm_phys_excp_target_el(cs, excp_idx, cur_el, secure= ); - if (arm_excp_unmasked(cs, excp_idx, target_el)) { + if (arm_excp_unmasked(cs, excp_idx, target_el, + cur_el, secure, hcr_el2)) { cs->exception_index =3D excp_idx; env->exception.target_el =3D target_el; cc->do_interrupt(cs); @@ -552,7 +551,8 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt= _request) if (interrupt_request & CPU_INTERRUPT_HARD) { excp_idx =3D EXCP_IRQ; target_el =3D arm_phys_excp_target_el(cs, excp_idx, cur_el, secure= ); - if (arm_excp_unmasked(cs, excp_idx, target_el)) { + if (arm_excp_unmasked(cs, excp_idx, target_el, + cur_el, secure, hcr_el2)) { cs->exception_index =3D excp_idx; env->exception.target_el =3D target_el; cc->do_interrupt(cs); @@ -562,7 +562,8 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt= _request) if (interrupt_request & CPU_INTERRUPT_VIRQ) { excp_idx =3D EXCP_VIRQ; target_el =3D 1; - if (arm_excp_unmasked(cs, excp_idx, target_el)) { + if (arm_excp_unmasked(cs, excp_idx, target_el, + cur_el, secure, hcr_el2)) { cs->exception_index =3D excp_idx; env->exception.target_el =3D target_el; cc->do_interrupt(cs); @@ -572,7 +573,8 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt= _request) if (interrupt_request & CPU_INTERRUPT_VFIQ) { excp_idx =3D EXCP_VFIQ; target_el =3D 1; - if (arm_excp_unmasked(cs, excp_idx, target_el)) { + if (arm_excp_unmasked(cs, excp_idx, target_el, + cur_el, secure, hcr_el2)) { cs->exception_index =3D excp_idx; env->exception.target_el =3D target_el; cc->do_interrupt(cs); --=20 2.20.1 From nobody Mon Feb 9 12:19:52 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580586731541319.6891343274568; Sat, 1 Feb 2020 11:52:11 -0800 (PST) Received: from localhost ([::1]:50172 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixyoM-00020r-CK for importer@patchew.org; Sat, 01 Feb 2020 14:52:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59008) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixyT1-000865-Lb for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:30:08 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ixyT0-0007It-Lm for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:30:07 -0500 Received: from mail-pl1-x643.google.com ([2607:f8b0:4864:20::643]:35109) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ixyT0-0007Gr-Ft for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:30:06 -0500 Received: by mail-pl1-x643.google.com with SMTP id g6so4182152plt.2 for ; Sat, 01 Feb 2020 11:30:06 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id l7sm3668509pga.27.2020.02.01.11.30.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Feb 2020 11:30:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=l3ss3qHmQ8iAPtkBg17Hc7UVaIr08fmUa1mIsHxPys4=; b=snbapzR93c+nOgp07cmfvM7TpZEP9qBWCi5Jr2t+dJSZCXORXgg9qqJobkaLHv1EcJ JA42+ro/jXeE+CsEJlTdTrAoY0tO7RdFvC0XsTUkiDinVgIqhDkNH5tPsF5xjaGE28nX PCImzSvAtJgPMI5itTg+k1xvpPFzkz0xh6AQUgkwdf5J64ITJmUkX/wWTeU82cT4IjWo ffW2ULNVRldeRQUAcLAbnyEVo/6FgmyGnCcDtPTjRtnzc9BWwj9rhDT9NrIxjcuG9WjD m9wG0JP0/oGm3e+fOenQAKBYP6TBAUHfOFmV4IKpgMfdDM++ZFif3WRx28g1U5KJpuG/ WlbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=l3ss3qHmQ8iAPtkBg17Hc7UVaIr08fmUa1mIsHxPys4=; b=CFF8cPUzNeFc8TgxsB0ACuzq2DHZ+F6CnUty1/sO0KN99yKHJW+hqk6tPTQBRQ/q5d 43sFYydPqgO1x0BIuDZ0nFjmURXrXPUZzhMXWxXiNBoMTKuOYKiHCnxDxy+ytGROV9PI mtS8KtoWNuBCKp13zaEJnDsL+DGH5d4pbxBj7d98rGCZT2LNfMNdHWrYO+pwDYEOb5ei 6Mr91lEHaQpJ6wngPDl1IFkR/NfbWtNp9LHUABD+krh4hwPNk8dOavJ7F7XcAhbO+P/w MamNleZ45aiu2V0Tj3MM92qcTT/cMPjg8aveEgUVLEaUl0X+yhD5OMiTlDdZ8gDzoG7i fuFA== X-Gm-Message-State: APjAAAVu2B0RkdA17gj9ZZXr9DB3+gstXctB1pjuZpvPbdkF0bbn1XM2 Iy6UoRK4dDzSYkaQf2DEI/iPI+mfwiE= X-Google-Smtp-Source: APXvYqzRiFozttOmApw3zawjkw+d51C3mWszY6crQaNCyyMZI4mtytccXSi8lud45WoD4IWY1nHF/A== X-Received: by 2002:a17:902:6ac2:: with SMTP id i2mr15953152plt.221.1580585405281; Sat, 01 Feb 2020 11:30:05 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 40/41] target/arm: Use bool for unmasked in arm_excp_unmasked Date: Sat, 1 Feb 2020 11:29:15 -0800 Message-Id: <20200201192916.31796-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200201192916.31796-1-richard.henderson@linaro.org> References: <20200201192916.31796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) The value computed is fully boolean; using int8_t is odd. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- target/arm/cpu.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index fcee0a2dd4..4ffc09909d 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -417,7 +417,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsi= gned int excp_idx, { CPUARMState *env =3D cs->env_ptr; bool pstate_unmasked; - int8_t unmasked =3D 0; + bool unmasked =3D false; =20 /* * Don't take exceptions if they target a lower EL. @@ -468,7 +468,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsi= gned int excp_idx, * don't affect the masking logic, only the interrupt routing. */ if (target_el =3D=3D 3 || !secure) { - unmasked =3D 1; + unmasked =3D true; } } else { /* @@ -514,7 +514,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsi= gned int excp_idx, } =20 if ((scr || hcr) && !secure) { - unmasked =3D 1; + unmasked =3D true; } } } --=20 2.20.1 From nobody Mon Feb 9 12:19:52 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580586235160331.74811790227477; Sat, 1 Feb 2020 11:43:55 -0800 (PST) Received: from localhost ([::1]:49938 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixygM-0004jL-4f for importer@patchew.org; Sat, 01 Feb 2020 14:43:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59024) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixyT2-00088D-P7 for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:30:09 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ixyT1-0007MK-N9 for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:30:08 -0500 Received: from mail-pj1-x1042.google.com ([2607:f8b0:4864:20::1042]:53390) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ixyT1-0007KD-Gy for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:30:07 -0500 Received: by mail-pj1-x1042.google.com with SMTP id n96so4463436pjc.3 for ; Sat, 01 Feb 2020 11:30:07 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id l7sm3668509pga.27.2020.02.01.11.30.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Feb 2020 11:30:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+p/P+yAizHAWC+Z0oIrQh7XKufbPcqsMPf7WqU6GqBM=; b=dO9fuf1/Od1i66tbh5lPsWxsNiLf0YyEsgCVnepPWUQSDc+98pS40l+6XHc+7/UiJ+ 19BgjsRCBMdxjEzKNLISwJXTGmAb/e0Hnd8AegNUUwZX51Ah7aRNNzAV8I/pUhzQk1je uMR35jdX6Cc4bMJkxzm8HEpf+wd/Ks+Woy91QL34SoqupGP1UcC4G4DZGrg20rvNNUBZ V+cWZ9DpGg8aBAorFg2EJG1LM37PeJ0+hoYiVqeblC4AtnI25Txr+X+zsrIGeXxN6yC2 zAemXsw0d9z+cAlLAKTInxJUeHmQVyRAx69AAKUOGY/jVwDQuFx+AmvVs23iBjxas5PB M/ag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+p/P+yAizHAWC+Z0oIrQh7XKufbPcqsMPf7WqU6GqBM=; b=QCIYUYx7X9cMEHU34FqE0ua1+mch6kgWMRKyYUBKVPSglBfEww583DUT8ux7H+QIGB TvfuJdECM4pwDtpsrvuv0unOKstTbFgc49MM7pV4isNS7b2vHp88zFlSH/tMfexQB2F7 uiSH2mks/WyeLcvKpjKHMt76jh+MaalN9OFpKfvmKotnyvnE9wJbr5/4tH7JYzXI+Kz0 9zJ95VVuqPkPTb7mx6pxLgZAlE8IvgOpelcPXp0nPXHZ+p0tERUZjmBaQyD9LKoa88wq bgUc80oBsCpDAbvGcSlw4a8s/MCE0EAbdNWDni8+5grn3YYbgsrOo6yYzzFWhhzbXC8j 0eBA== X-Gm-Message-State: APjAAAV06r42mw5USsBjtlRRBq8kYdMAKsSpr0PZuOqdCLMuGMDbmJHK hrWbVwNFlKOWCJ0fuDZRzmrHGgVDjA4= X-Google-Smtp-Source: APXvYqyjFM0Fqf/Z7WH/KylhZZBfJoliuKlH/ZKkEI/QV1r/qU1smAD4FgD13WnBcZesGELddGTIrw== X-Received: by 2002:a17:902:a608:: with SMTP id u8mr15598340plq.76.1580585406364; Sat, 01 Feb 2020 11:30:06 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 41/41] target/arm: Raise only one interrupt in arm_cpu_exec_interrupt Date: Sat, 1 Feb 2020 11:29:16 -0800 Message-Id: <20200201192916.31796-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200201192916.31796-1-richard.henderson@linaro.org> References: <20200201192916.31796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1042 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The fall through organization of this function meant that we would raise an interrupt, then might overwrite that with another. Since interrupt prioritization is IMPLEMENTATION DEFINED, we can recognize these in any order we choose. Unify the code to raise the interrupt in a block at the end. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e --- target/arm/cpu.c | 30 ++++++++++++------------------ 1 file changed, 12 insertions(+), 18 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 4ffc09909d..b0762a76c4 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -535,17 +535,15 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interru= pt_request) uint64_t hcr_el2 =3D arm_hcr_el2_eff(env); uint32_t target_el; uint32_t excp_idx; - bool ret =3D false; + + /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */ =20 if (interrupt_request & CPU_INTERRUPT_FIQ) { excp_idx =3D EXCP_FIQ; target_el =3D arm_phys_excp_target_el(cs, excp_idx, cur_el, secure= ); if (arm_excp_unmasked(cs, excp_idx, target_el, cur_el, secure, hcr_el2)) { - cs->exception_index =3D excp_idx; - env->exception.target_el =3D target_el; - cc->do_interrupt(cs); - ret =3D true; + goto found; } } if (interrupt_request & CPU_INTERRUPT_HARD) { @@ -553,10 +551,7 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrup= t_request) target_el =3D arm_phys_excp_target_el(cs, excp_idx, cur_el, secure= ); if (arm_excp_unmasked(cs, excp_idx, target_el, cur_el, secure, hcr_el2)) { - cs->exception_index =3D excp_idx; - env->exception.target_el =3D target_el; - cc->do_interrupt(cs); - ret =3D true; + goto found; } } if (interrupt_request & CPU_INTERRUPT_VIRQ) { @@ -564,10 +559,7 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrup= t_request) target_el =3D 1; if (arm_excp_unmasked(cs, excp_idx, target_el, cur_el, secure, hcr_el2)) { - cs->exception_index =3D excp_idx; - env->exception.target_el =3D target_el; - cc->do_interrupt(cs); - ret =3D true; + goto found; } } if (interrupt_request & CPU_INTERRUPT_VFIQ) { @@ -575,14 +567,16 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interru= pt_request) target_el =3D 1; if (arm_excp_unmasked(cs, excp_idx, target_el, cur_el, secure, hcr_el2)) { - cs->exception_index =3D excp_idx; - env->exception.target_el =3D target_el; - cc->do_interrupt(cs); - ret =3D true; + goto found; } } + return false; =20 - return ret; + found: + cs->exception_index =3D excp_idx; + env->exception.target_el =3D target_el; + cc->do_interrupt(cs); + return true; } =20 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) --=20 2.20.1