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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a22sm6994442wmd.20.2020.01.30.08.15.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2020 08:15:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=wkn1AOV8t66g8xUrVaEPWBIHxHvOo4ew4OLKGFBPagg=; b=Y92U3Vq/8+F9aaCQd5GObsJptMvtswkR9yHYa7lYaM9GvLQDeLATHv8WPdVJhu99xt NMoiMl7Y4GHheonndHRW4PzvQHwf9twdZcy0Z/VbJxmQXLDUJFz1wdwmTPIIt9Tn1S+i 3agmceM2+tJXoIakmPwN8neDy/STvzg6wSeC8kTchGhBYMy6Mo3ZxXaug08uWviCW3WB H5dSTlELhFBUeZ5mbN+oLDTibRPzxdsAJXwDZcd7rUeQkUT3TSAxsRBwnZ2heIMgRD7l nsGt2cOgVlP+WUxxMX0MgeFzOsLpqYBqJ/jxBEVOAKWUB4+N5HV3W650Di+ZLzqG9d8r p2KQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wkn1AOV8t66g8xUrVaEPWBIHxHvOo4ew4OLKGFBPagg=; b=C3FxozsFMm08YxJcJvuecjpR/3rlw5JoXtQkxuLOXF/xoMiY/pwIMekI9UkE4TMOGx ruzSU/sGEMq/VBCy+Ge0Eg1Qw4c+Me88TUnMmk57ZixwSVjYSkTgFa5nybk7lBZHOQ30 cA2UO6Hy5taLv+WQFVVGeJZK3ONcuYTHkv3CfbV9vVYJq2W9AGsGL23wRNRomFCQwDUH B68brXb4MmoIICeebwIVZdMiaUb9sfll9z8JqPU3ROSsDntblK5JDh8W0tcmZJ5jMHaZ gXp5sYLms3iwdT9rZ0hLyos3KCUtVR0w402CC/49YWqeRyHJVx1uI87DKWBtlH8motfz Mlaw== X-Gm-Message-State: APjAAAV+BnxWcvFBtgQce7vsLb6WI0SL9SHj0kvbqvtrgy98ROPgM55J rRnIHXguAkD/i1i8PIOfmZ0UywG5Bcn2Qw== X-Google-Smtp-Source: APXvYqz1pfazEfbhznFAQG6dJIenf/iz2evA69EAQm9QLdnpIkAdtScXDfsRhjqrup2YTnm1SAFYqg== X-Received: by 2002:a5d:6151:: with SMTP id y17mr6360451wrt.110.1580400939282; Thu, 30 Jan 2020 08:15:39 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/26] hw/sd: Configure number of slots exposed by the ASPEED SDHCI model Date: Thu, 30 Jan 2020 16:15:10 +0000 Message-Id: <20200130161533.8180-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200130161533.8180-1-peter.maydell@linaro.org> References: <20200130161533.8180-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::434 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Andrew Jeffery The AST2600 includes a second cut-down version of the SD/MMC controller found in the AST2500, named the eMMC controller. It's cut down in the sense that it only supports one slot rather than two, but it brings the total number of slots supported by the AST2600 to three. The existing code assumed that the SD controller always provided two slots. Rework the SDHCI object to expose the number of slots as a property to be set by the SoC configuration. Signed-off-by: Andrew Jeffery Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: C=C3=A9dric Le Goater Signed-off-by: C=C3=A9dric Le Goater Message-id: 20200114103433.30534-2-clg@kaod.org [PMM: fixed up to use device_class_set_props()] Signed-off-by: Peter Maydell --- include/hw/sd/aspeed_sdhci.h | 1 + hw/arm/aspeed.c | 2 +- hw/arm/aspeed_ast2600.c | 2 ++ hw/arm/aspeed_soc.c | 2 ++ hw/sd/aspeed_sdhci.c | 11 +++++++++-- 5 files changed, 15 insertions(+), 3 deletions(-) diff --git a/include/hw/sd/aspeed_sdhci.h b/include/hw/sd/aspeed_sdhci.h index dfdab437902..dffbb46946b 100644 --- a/include/hw/sd/aspeed_sdhci.h +++ b/include/hw/sd/aspeed_sdhci.h @@ -24,6 +24,7 @@ typedef struct AspeedSDHCIState { SysBusDevice parent; =20 SDHCIState slots[ASPEED_SDHCI_NUM_SLOTS]; + uint8_t num_slots; =20 MemoryRegion iomem; qemu_irq irq; diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index cc06af4fbb3..4174e313cae 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -263,7 +263,7 @@ static void aspeed_machine_init(MachineState *machine) amc->i2c_init(bmc); } =20 - for (i =3D 0; i < ARRAY_SIZE(bmc->soc.sdhci.slots); i++) { + for (i =3D 0; i < bmc->soc.sdhci.num_slots; i++) { SDHCIState *sdhci =3D &bmc->soc.sdhci.slots[i]; DriveInfo *dinfo =3D drive_get_next(IF_SD); BlockBackend *blk; diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index 89e4b009504..fb73c4043ea 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -199,6 +199,8 @@ static void aspeed_soc_ast2600_init(Object *obj) sysbus_init_child_obj(obj, "sdc", OBJECT(&s->sdhci), sizeof(s->sdhci), TYPE_ASPEED_SDHCI); =20 + object_property_set_int(OBJECT(&s->sdhci), 2, "num-slots", &error_abor= t); + /* Init sd card slot class here so that they're under the correct pare= nt */ for (i =3D 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[i]), diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index 99892cbae67..b5e809a1d3f 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -209,6 +209,8 @@ static void aspeed_soc_init(Object *obj) sysbus_init_child_obj(obj, "sdc", OBJECT(&s->sdhci), sizeof(s->sdhci), TYPE_ASPEED_SDHCI); =20 + object_property_set_int(OBJECT(&s->sdhci), 2, "num-slots", &error_abor= t); + /* Init sd card slot class here so that they're under the correct pare= nt */ for (i =3D 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[i]), diff --git a/hw/sd/aspeed_sdhci.c b/hw/sd/aspeed_sdhci.c index cff3eb7dd21..6a039a1d2f1 100644 --- a/hw/sd/aspeed_sdhci.c +++ b/hw/sd/aspeed_sdhci.c @@ -13,6 +13,7 @@ #include "qapi/error.h" #include "hw/irq.h" #include "migration/vmstate.h" +#include "hw/qdev-properties.h" =20 #define ASPEED_SDHCI_INFO 0x00 #define ASPEED_SDHCI_INFO_RESET 0x00030000 @@ -120,14 +121,14 @@ static void aspeed_sdhci_realize(DeviceState *dev, Er= ror **errp) =20 /* Create input irqs for the slots */ qdev_init_gpio_in_named_with_opaque(DEVICE(sbd), aspeed_sdhci_set_irq, - sdhci, NULL, ASPEED_SDHCI_NUM_SLOT= S); + sdhci, NULL, sdhci->num_slots); =20 sysbus_init_irq(sbd, &sdhci->irq); memory_region_init_io(&sdhci->iomem, OBJECT(sdhci), &aspeed_sdhci_ops, sdhci, TYPE_ASPEED_SDHCI, 0x1000); sysbus_init_mmio(sbd, &sdhci->iomem); =20 - for (int i =3D 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { + for (int i =3D 0; i < sdhci->num_slots; ++i) { Object *sdhci_slot =3D OBJECT(&sdhci->slots[i]); SysBusDevice *sbd_slot =3D SYS_BUS_DEVICE(&sdhci->slots[i]); =20 @@ -174,6 +175,11 @@ static const VMStateDescription vmstate_aspeed_sdhci = =3D { }, }; =20 +static Property aspeed_sdhci_properties[] =3D { + DEFINE_PROP_UINT8("num-slots", AspeedSDHCIState, num_slots, 0), + DEFINE_PROP_END_OF_LIST(), +}; + static void aspeed_sdhci_class_init(ObjectClass *classp, void *data) { DeviceClass *dc =3D DEVICE_CLASS(classp); @@ -181,6 +187,7 @@ static void aspeed_sdhci_class_init(ObjectClass *classp= , void *data) dc->realize =3D aspeed_sdhci_realize; dc->reset =3D aspeed_sdhci_reset; dc->vmsd =3D &vmstate_aspeed_sdhci; + device_class_set_props(dc, aspeed_sdhci_properties); } =20 static TypeInfo aspeed_sdhci_info =3D { --=20 2.20.1