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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id r3sm3953626pfg.145.2020.01.29.15.56.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jan 2020 15:56:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uqXtEboFX1Y8RculjLF7qqNO1NcFp6bsZn0DtNh5d9I=; b=tw/Tp0r15OTwDsSvZTTGVC79yeyD+fSxEhWWuzeBbukd3XYNjAGIo0sA73hRAgKF4P SJt0InbT62v2k+IlkoCA4uJKF2EMvsFD1oVR4hbzwi737Qv0F7n6zHy4jpALkjRn82Si Ivxc8YGcGi9fSaoGLbqaQqMSPNlpvCnGejkKQ/iVbLvlJm3RPJXBBHKLYitl1rwrdHtT kYOCR/dU7OM2uu5+gNbMaOr9I0id5XtKIzaUJZL8h27h7XwSoa1SShCi37KkjwcLRH70 NcWPosL/c+kw4dIeylvXFwzJZlc0Ix0Y7S5LmuzjH2cW/H4OpaznCM3hU+kl4PW7fGTQ 5X8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uqXtEboFX1Y8RculjLF7qqNO1NcFp6bsZn0DtNh5d9I=; b=pr3YegGVC/CCemlL00DsVSS/XcNwcMopHe9BjbAAX+46j2AwMNmuWg+k9ei2U9K//L ymK/sXcoahmTpVzvpzmnqJT6dhCONAgILskBEcmV0CAORM17tbOvUpOWyzZqVCQkAI/U TS/OsaN0yzW5U1F9Q2MZVLEHnCjBsvLVDbs5qxaAuOdZOw66hmRZu1sc0Im6xjT8pZH0 fTSwL2ngR6wvOkENpPvMW+uObyy0545WlL+w1Wu3K3JImOsbhTLIE0VDT8UlLAAcJ1to Cv3CVU5eZfmSi1jAsw59TltDXCtnhbufsCCdUGQFj+IKUy+PuJW9TXZmKE3OOCMPfA/p K5xQ== X-Gm-Message-State: APjAAAWQLOxaBKxnKnQC9TD0bUcCgN0NonAb7y5xOLSLwTQwOMjxqRxB 2RR0JpD5SOlRTFZZqr3REi6sCeZ+bi0= X-Google-Smtp-Source: APXvYqxjUAOsBLYj1VE+vu/rrUIgqWJNJ0Rzmi/vNAaU+jbtQjrOuipYkq48tdTUGYnsB9PlQLtcTA== X-Received: by 2002:a63:2ad8:: with SMTP id q207mr1683414pgq.45.1580342186273; Wed, 29 Jan 2020 15:56:26 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 08/41] target/arm: Simplify tlb_force_broadcast alternatives Date: Wed, 29 Jan 2020 15:55:41 -0800 Message-Id: <20200129235614.29829-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200129235614.29829-1-richard.henderson@linaro.org> References: <20200129235614.29829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Rather than call to a separate function and re-compute any parameters for the flush, simply use the correct flush function directly. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- target/arm/helper.c | 52 +++++++++++++++++++++------------------------ 1 file changed, 24 insertions(+), 28 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 00b770813f..d23d1dd6ef 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -614,56 +614,54 @@ static void tlbiall_write(CPUARMState *env, const ARM= CPRegInfo *ri, uint64_t value) { /* Invalidate all (TLBIALL) */ - ARMCPU *cpu =3D env_archcpu(env); + CPUState *cs =3D env_cpu(env); =20 if (tlb_force_broadcast(env)) { - tlbiall_is_write(env, NULL, value); - return; + tlb_flush_all_cpus_synced(cs); + } else { + tlb_flush(cs); } - - tlb_flush(CPU(cpu)); } =20 static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */ - ARMCPU *cpu =3D env_archcpu(env); + CPUState *cs =3D env_cpu(env); =20 + value &=3D TARGET_PAGE_MASK; if (tlb_force_broadcast(env)) { - tlbimva_is_write(env, NULL, value); - return; + tlb_flush_page_all_cpus_synced(cs, value); + } else { + tlb_flush_page(cs, value); } - - tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK); } =20 static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { /* Invalidate by ASID (TLBIASID) */ - ARMCPU *cpu =3D env_archcpu(env); + CPUState *cs =3D env_cpu(env); =20 if (tlb_force_broadcast(env)) { - tlbiasid_is_write(env, NULL, value); - return; + tlb_flush_all_cpus_synced(cs); + } else { + tlb_flush(cs); } - - tlb_flush(CPU(cpu)); } =20 static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */ - ARMCPU *cpu =3D env_archcpu(env); + CPUState *cs =3D env_cpu(env); =20 + value &=3D TARGET_PAGE_MASK; if (tlb_force_broadcast(env)) { - tlbimvaa_is_write(env, NULL, value); - return; + tlb_flush_page_all_cpus_synced(cs, value); + } else { + tlb_flush_page(cs, value); } - - tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK); } =20 static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -3965,11 +3963,10 @@ static void tlbi_aa64_vmalle1_write(CPUARMState *en= v, const ARMCPRegInfo *ri, int mask =3D vae1_tlbmask(env); =20 if (tlb_force_broadcast(env)) { - tlbi_aa64_vmalle1is_write(env, NULL, value); - return; + tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); + } else { + tlb_flush_by_mmuidx(cs, mask); } - - tlb_flush_by_mmuidx(cs, mask); } =20 static int alle1_tlbmask(CPUARMState *env) @@ -4091,11 +4088,10 @@ static void tlbi_aa64_vae1_write(CPUARMState *env, = const ARMCPRegInfo *ri, uint64_t pageaddr =3D sextract64(value << 12, 0, 56); =20 if (tlb_force_broadcast(env)) { - tlbi_aa64_vae1is_write(env, NULL, value); - return; + tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, mask); + } else { + tlb_flush_page_by_mmuidx(cs, pageaddr, mask); } - - tlb_flush_page_by_mmuidx(cs, pageaddr, mask); } =20 static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *r= i, --=20 2.20.1