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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id r3sm3953626pfg.145.2020.01.29.15.57.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jan 2020 15:57:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6zsJ+64yBL0aQurnYOJJKrMClJ7E0x3WeYfXxBCipH4=; b=R6Z2/Uh3qyJqgN5G1GXEY5OXmd8y/Kc8MJmNuPZ6fnbrOQicJ4e9LPiOa9ZnBLOsuO Z84TuIs26ZkCmp3ExsYNSEb1Hf33oSM9aKF6n92l10sdHCqIf+58c0QTBf1t2HLtqwXe L4dvASdYeoQiTBteNKMb8SsQMOuBWYs3i3z9lJ88adCbZ1oF/5yyuYrqHySd8gfpTkBJ mJGeMzu7km1Qr21nYf8IeMOBA/Y65PjyKUgTAqjqyDJHY7yLSORyV0XawI4xbduwSbzb B1Nkdbio5FtMQe2dqwoKCbF+NCRl8oH07VVpzXaIBmZSqIBtDPCqzdyLDMqIe5rwx0eN 0gYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6zsJ+64yBL0aQurnYOJJKrMClJ7E0x3WeYfXxBCipH4=; b=Kkg9aW1ydbs/x5fKUFw6DAPTB3BLHp+rtUXv6emAHhJpf2eGceda5m/YCDkR6am9NF wILcZqUjAxyb/QSAIS2K9Ode1GzO3dUCvlA73NONxRC/+Iz54XpbtBwiTZC+9zkCOuW3 AcYZN20Sn1+WdH4roaiHYbsemwQ+x/0oyw5PVooHHe/E18wrJ6qG2CQ04OFOYgIpDcPI 934l1kw+HS8Bs/p6vTrLtABIqrt4qAOK/Rq16+CPShcKKQDlEq7lPD92bRFCUj3g+IcZ yu9aWOngBDR0/BCpirAdUdQLUAjUm2FsIrBEM0mKdWPHMX7zbvkyRkJePCpdG4B5clyq ttLg== X-Gm-Message-State: APjAAAXPSuCOLcsN+2svpCnRKjnRkeqYj/YdZj54YyHxoInmdwMz56Ev rWj36dbgLNzpn0ktAJTvmiz7SxNq3pU= X-Google-Smtp-Source: APXvYqyrPx3oTfb42A9UUE45BO6bLXABZgJ/UYtASHZmJOhA2FgYVWQWNHEEC7JgyJy8Ed7uF9a6ZQ== X-Received: by 2002:a17:90b:30c9:: with SMTP id hi9mr1481025pjb.81.1580342225758; Wed, 29 Jan 2020 15:57:05 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 39/41] target/arm: Pass more cpu state to arm_excp_unmasked Date: Wed, 29 Jan 2020 15:56:12 -0800 Message-Id: <20200129235614.29829-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200129235614.29829-1-richard.henderson@linaro.org> References: <20200129235614.29829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1044 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Avoid redundant computation of cpu state by passing it in from the caller, which has already computed it for itself. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/arm/cpu.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 114833bdba..d9cf625073 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -411,14 +411,13 @@ static void arm_cpu_reset(CPUState *s) } =20 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, - unsigned int target_el) + unsigned int target_el, + unsigned int cur_el, bool secure, + uint64_t hcr_el2) { CPUARMState *env =3D cs->env_ptr; - unsigned int cur_el =3D arm_current_el(env); - bool secure =3D arm_is_secure(env); bool pstate_unmasked; int8_t unmasked =3D 0; - uint64_t hcr_el2; =20 /* * Don't take exceptions if they target a lower EL. @@ -429,8 +428,6 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsi= gned int excp_idx, return false; } =20 - hcr_el2 =3D arm_hcr_el2_eff(env); - switch (excp_idx) { case EXCP_FIQ: pstate_unmasked =3D !(env->daif & PSTATE_F); @@ -535,6 +532,7 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt= _request) CPUARMState *env =3D cs->env_ptr; uint32_t cur_el =3D arm_current_el(env); bool secure =3D arm_is_secure(env); + uint64_t hcr_el2 =3D arm_hcr_el2_eff(env); uint32_t target_el; uint32_t excp_idx; bool ret =3D false; @@ -542,7 +540,8 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt= _request) if (interrupt_request & CPU_INTERRUPT_FIQ) { excp_idx =3D EXCP_FIQ; target_el =3D arm_phys_excp_target_el(cs, excp_idx, cur_el, secure= ); - if (arm_excp_unmasked(cs, excp_idx, target_el)) { + if (arm_excp_unmasked(cs, excp_idx, target_el, + cur_el, secure, hcr_el2)) { cs->exception_index =3D excp_idx; env->exception.target_el =3D target_el; cc->do_interrupt(cs); @@ -552,7 +551,8 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt= _request) if (interrupt_request & CPU_INTERRUPT_HARD) { excp_idx =3D EXCP_IRQ; target_el =3D arm_phys_excp_target_el(cs, excp_idx, cur_el, secure= ); - if (arm_excp_unmasked(cs, excp_idx, target_el)) { + if (arm_excp_unmasked(cs, excp_idx, target_el, + cur_el, secure, hcr_el2)) { cs->exception_index =3D excp_idx; env->exception.target_el =3D target_el; cc->do_interrupt(cs); @@ -562,7 +562,8 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt= _request) if (interrupt_request & CPU_INTERRUPT_VIRQ) { excp_idx =3D EXCP_VIRQ; target_el =3D 1; - if (arm_excp_unmasked(cs, excp_idx, target_el)) { + if (arm_excp_unmasked(cs, excp_idx, target_el, + cur_el, secure, hcr_el2)) { cs->exception_index =3D excp_idx; env->exception.target_el =3D target_el; cc->do_interrupt(cs); @@ -572,7 +573,8 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt= _request) if (interrupt_request & CPU_INTERRUPT_VFIQ) { excp_idx =3D EXCP_VFIQ; target_el =3D 1; - if (arm_excp_unmasked(cs, excp_idx, target_el)) { + if (arm_excp_unmasked(cs, excp_idx, target_el, + cur_el, secure, hcr_el2)) { cs->exception_index =3D excp_idx; env->exception.target_el =3D target_el; cc->do_interrupt(cs); --=20 2.20.1