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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id r3sm3953626pfg.145.2020.01.29.15.56.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jan 2020 15:56:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+Rtwbd7ZF0YwQZEeUwLrz8KTLHPwY1TqRVqYzEpCzAM=; b=Jx8/tReS9+s+XgVVQcV0xtPeJwR80CP/AvLn829GQUlmovioxg8uLyn2pHE9y1oSbJ kxTvolsz50ag9Gt3kiuufk0Gety1UAjXUuth6x3yI4lCldy/rE8VslKoIrXkSS640pId TmetpVi6qWiSYGytgmmiJav74CVNACk9OznYyGoYel9wZZTDHsnMgCqJzzB8Xvu17cRX P9lHK5eaJ/iqXciuwPHw7BKFkjSd7D+1jasF8fmuCfgm0/OF5/5w+5RkkrG5vni3Ck/N o92Bg76Yc1A2vrzZ3FhNN5B1e+cwvV5ZSoFh1GZxTb7Iqcl8Hfd9mxZKwe4J1PTyI3DA 6Aug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+Rtwbd7ZF0YwQZEeUwLrz8KTLHPwY1TqRVqYzEpCzAM=; b=lUmBeNfTrCytnIqV2KYPZb7WsMuRnY9w+EaZtqPLbcGeyR7954EUPsnooy+JyE2kqu yXkygaYnN8GL9KYJF+dIpfX7TTnVyKcyz+oPDJqvUXMOeCCjPUucegT4i0wOK4NYau0e g1bNxgQPvyk9YJLuMthN+8whQVjeWe10DqhJlOWJ6cMPSuiMNIWaxm+MPkZ6BuIs2fcb HQJBjoQxATnL/l/CbE5i3/+FSFiTsRXNskhmlVNl3m4EKGa4uS/X+S2fdxeg+qAcFvj+ +pMpcu8/QaU+MuUIjLMwd29suIprAdZa6nusMTm62JuF+4/N0Yb5uNlKf0dLcd11TEPD e0BQ== X-Gm-Message-State: APjAAAXZGQyoRaBlRLPF1OdUJKPtZ0JMjDhzodiMqWWo0uKHrCtaimI3 dak/7I69sKsSzlHfcinkQD6hhSmcp7s= X-Google-Smtp-Source: APXvYqwjcxma4rQedOlhKqjfkJ437GedW9h24xkSXGe2wiGHckgTGfYQD6Gfs8fwqYBDfazkmoL+iw== X-Received: by 2002:a17:90a:109:: with SMTP id b9mr2509177pjb.77.1580342215960; Wed, 29 Jan 2020 15:56:55 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 31/41] target/arm: Flush tlbs for E2&0 translation regime Date: Wed, 29 Jan 2020 15:56:04 -0800 Message-Id: <20200129235614.29829-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200129235614.29829-1-richard.henderson@linaro.org> References: <20200129235614.29829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1044 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- v5: Flush all EL2 regimes with TLBI ALLE2 (pmm). --- target/arm/helper.c | 34 +++++++++++++++++++++++++++------- 1 file changed, 27 insertions(+), 7 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 708a2ecf91..9b12ff0ef0 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4174,8 +4174,12 @@ static CPAccessResult aa64_cacheop_access(CPUARMStat= e *env, =20 static int vae1_tlbmask(CPUARMState *env) { + /* Since we exclude secure first, we may read HCR_EL2 directly. */ if (arm_is_secure_below_el3(env)) { return ARMMMUIdxBit_SE10_1 | ARMMMUIdxBit_SE10_0; + } else if ((env->cp15.hcr_el2 & (HCR_E2H | HCR_TGE)) + =3D=3D (HCR_E2H | HCR_TGE)) { + return ARMMMUIdxBit_E20_2 | ARMMMUIdxBit_E20_0; } else { return ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_0; } @@ -4219,6 +4223,12 @@ static int alle1_tlbmask(CPUARMState *env) } } =20 +static int alle2_tlbmask(CPUARMState *env) +{ + /* TODO: ARMv8.4-SecEL2 */ + return ARMMMUIdxBit_E20_0 | ARMMMUIdxBit_E20_2 | ARMMMUIdxBit_E2; +} + static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -4231,10 +4241,10 @@ static void tlbi_aa64_alle1_write(CPUARMState *env,= const ARMCPRegInfo *ri, static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu =3D env_archcpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); + int mask =3D alle2_tlbmask(env); =20 - tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E2); + tlb_flush_by_mmuidx(cs, mask); } =20 static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -4259,8 +4269,9 @@ static void tlbi_aa64_alle2is_write(CPUARMState *env,= const ARMCPRegInfo *ri, uint64_t value) { CPUState *cs =3D env_cpu(env); + int mask =3D alle2_tlbmask(env); =20 - tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E2); + tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); } =20 static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *= ri, @@ -4271,6 +4282,15 @@ static void tlbi_aa64_alle3is_write(CPUARMState *env= , const ARMCPRegInfo *ri, tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_SE3); } =20 +static int vae2_tlbmask(CPUARMState *env) +{ + if (arm_hcr_el2_eff(env) & HCR_E2H) { + return ARMMMUIdxBit_E20_0 | ARMMMUIdxBit_E20_2; + } else { + return ARMMMUIdxBit_E2; + } +} + static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -4278,11 +4298,11 @@ static void tlbi_aa64_vae2_write(CPUARMState *env, = const ARMCPRegInfo *ri, * Currently handles both VAE2 and VALE2, since we don't support * flush-last-level-only. */ - ARMCPU *cpu =3D env_archcpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); + int mask =3D vae2_tlbmask(env); uint64_t pageaddr =3D sextract64(value << 12, 0, 56); =20 - tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E2); + tlb_flush_page_by_mmuidx(cs, pageaddr, mask); } =20 static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri, --=20 2.20.1