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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id r3sm3953626pfg.145.2020.01.29.15.56.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jan 2020 15:56:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZB06Shgv2j1FRBq5HjNXTeQOLhUJt6Hevx1CrdU4jBA=; b=buj+sgy+Z53/A6qYagSYIqcfl4lhr7T1L56tlEYDi3LkFnf99tr6J+VLDNxriyd2Gd 4eZzrm3n1UUkwQXzYul87HYq6FwLySD4vTsdEwsLUq/TQfw6y4uOXvz2fneL4UKdUnyk IgDgQVJ5PzU4WshXuTaE/W5OIuKDWR/DSbMpQWx2TJUXMCBf9ZV4QmEpiicfL9cYZim1 GhwIBKrUOolVy2/wcwNo3lRw7tSm2ERzgZqTiVrw3Dihfu+2Wxja8g0dIhU4Ux8ouH7Z vY/sEUDQPOdR37/zhPZ69Glx5Wb0+iS/O7DKv0H18MbqLd3NpluhdMGgafnj2QemieBU 53nQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZB06Shgv2j1FRBq5HjNXTeQOLhUJt6Hevx1CrdU4jBA=; b=uHqEp6g9HUcM1IzTbbdyK3JKqI9RA8+8Xb4bLG1uv3x5nl/Z7BHF4aNUisCXX9bS5x y9dP+T+TWz4GINPXVPaobXAqpvUZc5DU8lch9yYgtonhWFz0JWzE2w7Cilvw5qJQM0Df Otja5Rd3BOccslVg5IUhylijKBMfykqOf956iMydvTsvE5eayoADj/VomQDViLdE9oT1 9NoYeIqiJKsTUKLdhhOmez8LTZ5wjZByqR/AlG8P9AUBWovyj8kmqzDP8TluK/mGsT1M +HaulfamYJKz5cz+ZNgIXRYV87ab54r9X9zu+1/xXf67CFF4XfC9GMMTsKDEn8AFR5B1 HpOg== X-Gm-Message-State: APjAAAVVTmaL/j7IYWftPS6ZT6vMim2FFhUz9lsHZcCmipTq+qWVnXNN vmulRYXVgXamp6hD0aBsC6zbPdLIQ9Y= X-Google-Smtp-Source: APXvYqzjJ4q5kOmH1EEvM5GfN3x3pvUlf428pagJzzrKsHqDqhd/AaiCQeheJmWWtHMoO0+Q1T8T5A== X-Received: by 2002:a17:90a:8d81:: with SMTP id d1mr2532857pjo.63.1580342214417; Wed, 29 Jan 2020 15:56:54 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 30/41] target/arm: Flush tlb for ASID changes in EL2&0 translation regime Date: Wed, 29 Jan 2020 15:56:03 -0800 Message-Id: <20200129235614.29829-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200129235614.29829-1-richard.henderson@linaro.org> References: <20200129235614.29829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Since we only support a single ASID, flush the tlb when it changes. Note that TCR_EL2, like TCR_EL1, has the A1 bit that chooses between the two TTBR* registers for the location of the ASID. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.c | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 0b67cefcbb..708a2ecf91 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3763,7 +3763,7 @@ static void vmsa_ttbcr_reset(CPUARMState *env, const = ARMCPRegInfo *ri) tcr->base_mask =3D 0xffffc000u; } =20 -static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, +static void vmsa_tcr_el12_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { ARMCPU *cpu =3D env_archcpu(env); @@ -3789,7 +3789,17 @@ static void vmsa_ttbr_write(CPUARMState *env, const = ARMCPRegInfo *ri, static void vmsa_tcr_ttbr_el2_write(CPUARMState *env, const ARMCPRegInfo *= ri, uint64_t value) { - /* TODO: There are ASID fields in here with HCR_EL2.E2H */ + /* + * If we are running with E2&0 regime, then an ASID is active. + * Flush if that might be changing. Note we're not checking + * TCR_EL2.A1 to know if this is really the TTBRx_EL2 that + * holds the active ASID, only checking the field that might. + */ + if (extract64(raw_read(env, ri) ^ value, 48, 16) && + (arm_hcr_el2_eff(env) & HCR_E2H)) { + tlb_flush_by_mmuidx(env_cpu(env), + ARMMMUIdxBit_E20_2 | ARMMMUIdxBit_E20_0); + } raw_write(env, ri, value); } =20 @@ -3849,7 +3859,7 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] =3D { offsetof(CPUARMState, cp15.ttbr1_ns) } }, { .name =3D "TCR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .crn =3D 2, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 2, - .access =3D PL1_RW, .writefn =3D vmsa_tcr_el1_write, + .access =3D PL1_RW, .writefn =3D vmsa_tcr_el12_write, .resetfn =3D vmsa_ttbcr_reset, .raw_writefn =3D raw_write, .fieldoffset =3D offsetof(CPUARMState, cp15.tcr_el[1]) }, { .name =3D "TTBCR", .cp =3D 15, .crn =3D 2, .crm =3D 0, .opc1 =3D 0, = .opc2 =3D 2, @@ -5175,10 +5185,8 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { .resetvalue =3D 0 }, { .name =3D "TCR_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 2, - .access =3D PL2_RW, - /* no .writefn needed as this can't cause an ASID change; - * no .raw_writefn or .resetfn needed as we never use mask/base_mask - */ + .access =3D PL2_RW, .writefn =3D vmsa_tcr_el12_write, + /* no .raw_writefn or .resetfn needed as we never use mask/base_mask= */ .fieldoffset =3D offsetof(CPUARMState, cp15.tcr_el[2]) }, { .name =3D "VTCR", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 4, .crn =3D 2, .crm =3D 1, .opc2 =3D 2, --=20 2.20.1