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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id r3sm3953626pfg.145.2020.01.29.15.56.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jan 2020 15:56:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rTQU923fsMMcx9+LorcmqOCU1SgJ9njP17/lCw46c9M=; b=apKe758o243LhK53nTuGC6pehIvt5b8F40bu31M6disFBX3YKI4TYlgm89Ph7yxl3U ZWy7vPMqVl16Gs2wNLZY3DEmcCSNuDXI47WY/0hblvD2WeqwkmWKDZi2bXgRRihKRlEr Q941w1jKfx2zNnfRGUKuGhSaPoJguv53jy+/DA2yEcYaI8ja70ODtSeC5/JHS7+Hqhji Pam/6ZfXmxyFaWyW7qwX8K1vunWOG9alF2Sr91LWj5/350iqAB5VhVVmkx+JcKOM1cJf Q46UgxgVUF2N0fN8ipKEXWF/147n/FsMLzAwQZ8ym/kD+G/NBGVnifKO2tLa2HILC4+z uiEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rTQU923fsMMcx9+LorcmqOCU1SgJ9njP17/lCw46c9M=; b=C1m6sb8geMlNwRVySybDPdyod0z8c3auTMui+Z1BiDmHN7C1r8UIZVOQc4A0htrHbg ryo7m19WOUpkfGOem+y5TdOKvXKHh/8EfkyFT5yPSVhjMNu6+5tfJe8FOIik6dEPAdEl E6dj5L+lh2GZH642lettppMOI/uquFr2HfkvllxOccJYu6do/eoXrG/M7F6/wOy5n5v3 mfqAwe1Vtr3H/hRpUaZid1xwbp1yCaeHTcTEOjXL5YslcwKz6lrAgNHtx4Xc363F5STn wx8VR2UNQhvRZ7eWIB/WYWYyV0/GVVuhZt6I45oPesBcHDcwhE1gakQEG/5GmuGSn/aM QeOg== X-Gm-Message-State: APjAAAVoAs2+1UdABt4ekehD2EoaXAy76na2eyCEEgSrsDZ3rtpfo788 nZ8I62TjxQNUWw6c4e+JFRhAIhbiTv4= X-Google-Smtp-Source: APXvYqwkgqYNgJgCsvzjiIIinw/Fe0CwIs7Y9Ln/djELn1zMxNVxYx6kV3q0HDpnK8JssNnyOqETUw== X-Received: by 2002:a17:902:7e4b:: with SMTP id a11mr1913208pln.61.1580342178678; Wed, 29 Jan 2020 15:56:18 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 02/41] target/arm: Enable HCR_E2H for VHE Date: Wed, 29 Jan 2020 15:55:35 -0800 Message-Id: <20200129235614.29829-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200129235614.29829-1-richard.henderson@linaro.org> References: <20200129235614.29829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- target/arm/cpu.h | 7 ------- target/arm/helper.c | 6 +++++- 2 files changed, 5 insertions(+), 8 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0477cef1ea..239c9eb783 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1417,13 +1417,6 @@ static inline void xpsr_write(CPUARMState *env, uint= 32_t val, uint32_t mask) #define HCR_ATA (1ULL << 56) #define HCR_DCT (1ULL << 57) =20 -/* - * When we actually implement ARMv8.1-VHE we should add HCR_E2H to - * HCR_MASK and then clear it again if the feature bit is not set in - * hcr_write(). - */ -#define HCR_MASK ((1ULL << 34) - 1) - #define SCR_NS (1U << 0) #define SCR_IRQ (1U << 1) #define SCR_FIQ (1U << 2) diff --git a/target/arm/helper.c b/target/arm/helper.c index 19a57a17da..f5ce05fdf3 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4721,7 +4721,8 @@ static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = =3D { static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= alue) { ARMCPU *cpu =3D env_archcpu(env); - uint64_t valid_mask =3D HCR_MASK; + /* Begin with bits defined in base ARMv8.0. */ + uint64_t valid_mask =3D MAKE_64BIT_MASK(0, 34); =20 if (arm_feature(env, ARM_FEATURE_EL3)) { valid_mask &=3D ~HCR_HCD; @@ -4735,6 +4736,9 @@ static void hcr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) */ valid_mask &=3D ~HCR_TSC; } + if (cpu_isar_feature(aa64_vh, cpu)) { + valid_mask |=3D HCR_E2H; + } if (cpu_isar_feature(aa64_lor, cpu)) { valid_mask |=3D HCR_TLOR; } --=20 2.20.1