From nobody Thu Nov 13 13:39:30 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580343438391785.7483408142614; Wed, 29 Jan 2020 16:17:18 -0800 (PST) Received: from localhost ([::1]:53984 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iwxWH-0003ze-Bm for importer@patchew.org; Wed, 29 Jan 2020 19:17:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45497) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iwxCV-0004D6-7R for qemu-devel@nongnu.org; Wed, 29 Jan 2020 18:56:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iwxCT-0008HH-MW for qemu-devel@nongnu.org; Wed, 29 Jan 2020 18:56:51 -0500 Received: from mail-pl1-x641.google.com ([2607:f8b0:4864:20::641]:45634) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iwxCT-0008Dg-ER for qemu-devel@nongnu.org; Wed, 29 Jan 2020 18:56:49 -0500 Received: by mail-pl1-x641.google.com with SMTP id b22so580445pls.12 for ; Wed, 29 Jan 2020 15:56:48 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id r3sm3953626pfg.145.2020.01.29.15.56.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jan 2020 15:56:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2bVSVEcKWqGNSiv8cYG9G0D1xK1dE0+YUqhMthCnato=; b=OcphJvJo+v9dBdSv5QUhghUR1bkoo5dY91VN0K/Ayem42CS2LMmC2EFIh6136OsMzJ 7fk+LbAhZ6D9ji/pdAarCERTpKmZTH2hLxg8p/o+/nsB2/w412uP7E1q5nAB2N/uP4XP EgY0F9COxMki/MTrBNMNhChfUB8syk1ryvDBLCacAussSHLQ3z5Ow3p8U9ateK9NVRLv slaVfDQTu5WmFTj/NIzKSWeA+/JWLzt/E+5Dtm8wlZ7i0I2YX1biTf+kRk2pG8LJe2zU LidXq3DYPiAEPFo20nXaDOrDyKNZmt08VvHZDjXd6/rvKFlJ0lH0QHnKJlx3C2AVxYC5 0EYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2bVSVEcKWqGNSiv8cYG9G0D1xK1dE0+YUqhMthCnato=; b=kTpzIjghBAGz6E1xVa95kxYsuYZTTEtTuQLod8QmzRG4+VX1BZ/y6OAKevv6Caw+9/ YB31KCtvJcU5ue9PS7LZtZc9qi0Ai92jeOGB6RE2RIWRVIebDlY6fCylF5mnvlZP/FAh TNA0IzbR/xJaSYeZ4l1NeRo46riMv6uZnxK/4xk5PgObvTWmya8ShTsD5Mvaxo0ogK2A FjWf8yzKu/7HeabYUZ8l3b85pj9WsGow9F9hucNuCxcXtykBiKvSgnkOtgLKM+ekVrJE WUmzQQOZjmhib50kkNAnaBWmh8TKcowTltLttMs9YJlDVy7a1UnieDOK5fi04EzkmF+3 89pQ== X-Gm-Message-State: APjAAAXUTBpH+xB41Y9NHLtCa3f+ibnsaLs9eq5+ZNGBVU/JowbLQ3hg 0WMW6oEjRh/P9NDTXUTv++rJevks2wI= X-Google-Smtp-Source: APXvYqwLGA+oTJQbU7qYKhMacW86oNg/CDYEg4Q105PDczjBUal3wo7xL0OFELzzBm+4BWQC0vvJ/Q== X-Received: by 2002:a17:902:e789:: with SMTP id cp9mr1906497plb.85.1580342207536; Wed, 29 Jan 2020 15:56:47 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 25/41] target/arm: Add the hypervisor virtual counter Date: Wed, 29 Jan 2020 15:55:58 -0800 Message-Id: <20200129235614.29829-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200129235614.29829-1-richard.henderson@linaro.org> References: <20200129235614.29829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- target/arm/cpu-qom.h | 1 + target/arm/cpu.h | 11 +++++---- target/arm/cpu.c | 3 ++- target/arm/helper.c | 57 ++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 66 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index 7f5b244bde..3a9d31ea9d 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -76,6 +76,7 @@ void arm_gt_ptimer_cb(void *opaque); void arm_gt_vtimer_cb(void *opaque); void arm_gt_htimer_cb(void *opaque); void arm_gt_stimer_cb(void *opaque); +void arm_gt_hvtimer_cb(void *opaque); =20 #define ARM_AFF0_SHIFT 0 #define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 703071bada..48a4603520 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -144,11 +144,12 @@ typedef struct ARMGenericTimer { uint64_t ctl; /* Timer Control register */ } ARMGenericTimer; =20 -#define GTIMER_PHYS 0 -#define GTIMER_VIRT 1 -#define GTIMER_HYP 2 -#define GTIMER_SEC 3 -#define NUM_GTIMERS 4 +#define GTIMER_PHYS 0 +#define GTIMER_VIRT 1 +#define GTIMER_HYP 2 +#define GTIMER_SEC 3 +#define GTIMER_HYPVIRT 4 +#define NUM_GTIMERS 5 =20 typedef struct { uint64_t raw_tcr; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 06907b36d7..0c530ffd29 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1272,7 +1272,6 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) } } =20 - { uint64_t scale; =20 @@ -1295,6 +1294,8 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) arm_gt_htimer_cb, cpu); cpu->gt_timer[GTIMER_SEC] =3D timer_new(QEMU_CLOCK_VIRTUAL, scale, arm_gt_stimer_cb, cpu); + cpu->gt_timer[GTIMER_HYPVIRT] =3D timer_new(QEMU_CLOCK_VIRTUAL, sc= ale, + arm_gt_hvtimer_cb, cpu); } #endif =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index e79237ea12..f633554678 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2556,6 +2556,7 @@ static uint64_t gt_tval_read(CPUARMState *env, const = ARMCPRegInfo *ri, =20 switch (timeridx) { case GTIMER_VIRT: + case GTIMER_HYPVIRT: offset =3D gt_virt_cnt_offset(env); break; } @@ -2572,6 +2573,7 @@ static void gt_tval_write(CPUARMState *env, const ARM= CPRegInfo *ri, =20 switch (timeridx) { case GTIMER_VIRT: + case GTIMER_HYPVIRT: offset =3D gt_virt_cnt_offset(env); break; } @@ -2727,6 +2729,34 @@ static void gt_sec_ctl_write(CPUARMState *env, const= ARMCPRegInfo *ri, gt_ctl_write(env, ri, GTIMER_SEC, value); } =20 +static void gt_hv_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) +{ + gt_timer_reset(env, ri, GTIMER_HYPVIRT); +} + +static void gt_hv_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + gt_cval_write(env, ri, GTIMER_HYPVIRT, value); +} + +static uint64_t gt_hv_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return gt_tval_read(env, ri, GTIMER_HYPVIRT); +} + +static void gt_hv_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + gt_tval_write(env, ri, GTIMER_HYPVIRT, value); +} + +static void gt_hv_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + gt_ctl_write(env, ri, GTIMER_HYPVIRT, value); +} + void arm_gt_ptimer_cb(void *opaque) { ARMCPU *cpu =3D opaque; @@ -2755,6 +2785,13 @@ void arm_gt_stimer_cb(void *opaque) gt_recalc_timer(cpu, GTIMER_SEC); } =20 +void arm_gt_hvtimer_cb(void *opaque) +{ + ARMCPU *cpu =3D opaque; + + gt_recalc_timer(cpu, GTIMER_HYPVIRT); +} + static void arm_gt_cntfrq_reset(CPUARMState *env, const ARMCPRegInfo *opaq= ue) { ARMCPU *cpu =3D env_archcpu(env); @@ -7128,6 +7165,26 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D = 1, .access =3D PL2_RW, .writefn =3D vmsa_tcr_ttbr_el2_write, .fieldoffset =3D offsetof(CPUARMState, cp15.ttbr1_el[2]) }, +#ifndef CONFIG_USER_ONLY + { .name =3D "CNTHV_CVAL_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 3, .opc2 =3D= 2, + .fieldoffset =3D + offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYPVIRT].cval), + .type =3D ARM_CP_IO, .access =3D PL2_RW, + .writefn =3D gt_hv_cval_write, .raw_writefn =3D raw_write }, + { .name =3D "CNTHV_TVAL_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 3, .opc2 =3D= 0, + .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL2_RW, + .resetfn =3D gt_hv_timer_reset, + .readfn =3D gt_hv_tval_read, .writefn =3D gt_hv_tval_write }, + { .name =3D "CNTHV_CTL_EL2", .state =3D ARM_CP_STATE_BOTH, + .type =3D ARM_CP_IO, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 3, .opc2 =3D= 1, + .access =3D PL2_RW, + .fieldoffset =3D + offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYPVIRT].ctl), + .writefn =3D gt_hv_ctl_write, .raw_writefn =3D raw_write }, +#endif REGINFO_SENTINEL }; define_arm_cp_regs(cpu, vhe_reginfo); --=20 2.20.1