From nobody Mon Feb 9 15:38:30 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580342396007925.6967219609439; Wed, 29 Jan 2020 15:59:56 -0800 (PST) Received: from localhost ([::1]:53502 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iwxFS-0000eP-S0 for importer@patchew.org; Wed, 29 Jan 2020 18:59:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45367) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iwxCK-0003uL-JZ for qemu-devel@nongnu.org; Wed, 29 Jan 2020 18:56:41 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iwxCJ-0007pZ-Hn for qemu-devel@nongnu.org; Wed, 29 Jan 2020 18:56:40 -0500 Received: from mail-pj1-x1041.google.com ([2607:f8b0:4864:20::1041]:34915) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iwxCI-0007gy-Ai for qemu-devel@nongnu.org; Wed, 29 Jan 2020 18:56:39 -0500 Received: by mail-pj1-x1041.google.com with SMTP id q39so534405pjc.0 for ; Wed, 29 Jan 2020 15:56:38 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id r3sm3953626pfg.145.2020.01.29.15.56.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jan 2020 15:56:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gVIYBMmIalIMw01cTrDxho+UQPcwIYSJMS1wimlyU34=; b=wDnyDihT0BV04GYS8nOcVnM1RqkHEPRLZhZonacVEvlIxdPqnTI5jVu1DxZmUEQSX6 iSN4xNvw6htbHf6GBhYKen9+eLaMwUcHamWpiPCoDbs3rjE53EDeNFAkpzCfrkMR8Ob2 +lsE2V4D5wUkI+TzKk/esFrMZb13NFf+bkAfE7v/xuzdVpV4aEj79MglHQi8tq8aEfju WbkIhHceQRgMxnqJ3PwDbH5eCN+Zfobv4w0oxX8/75Jd++S+2RDGckw5tVJVnKE5djP/ zsmETe3Cobzm6PmQtAKdPQq0KGzESraMwtC+MuemoK/8nBDrm/PA8Yxs98xkTaBT1MK/ ESfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gVIYBMmIalIMw01cTrDxho+UQPcwIYSJMS1wimlyU34=; b=sIk/ElOxu60ZElzJ4QR0Gwl5qEQlUL7KNHXG8mSNWaLw5f0QcpT/qkMaOqLbRk18Nc ZKr3B0KmfUI2035dapYQaGsdZsz4f1e51JCkFKoMg+XgpGnTLfNWcsAHOBx/kpUAcimF +IG2SbmXixdgb5Uc4Q8xw3zPJhYnXXrtfFSOP7oXrIfa7me8rHo3uYvuIleWX+QF4uY1 gytFJrwcf6/xNne4qgcT4i4iCp3aqwg53m2vBaO+dQDzVTeJx3HiEk/tmj88SZnDhvG2 5hFZKmy5hNv0wjxG+ar8sU6s/a4apuO/9jXOI3WCbNrdP9Ay+NBGECF4W/qGUdlcnTrQ FADQ== X-Gm-Message-State: APjAAAVAy+iLVCw4ciO7R4BppScphiLd8YzTc+GjpYz8aY1yM4T8Lz3N 3+QzwpESNvGKnAxPsDu7OFIeY97oxnI= X-Google-Smtp-Source: APXvYqxBwF48M4UXN60D9jPnMd4+6hWf/Hc7QDER95JJPxyo/vQmWX55SeDI9h9he1Ed3YGRSQ7AEA== X-Received: by 2002:a17:90b:3cc:: with SMTP id go12mr2478285pjb.89.1580342197105; Wed, 29 Jan 2020 15:56:37 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 17/41] target/arm: Rearrange ARMMMUIdxBit Date: Wed, 29 Jan 2020 15:55:50 -0800 Message-Id: <20200129235614.29829-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200129235614.29829-1-richard.henderson@linaro.org> References: <20200129235614.29829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1041 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Define via macro expansion, so that renumbering of the base ARMMMUIdx symbols is automatically reflected in the bit definitions. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/arm/cpu.h | 39 +++++++++++++++++++++++---------------- 1 file changed, 23 insertions(+), 16 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 893b1f1918..68ad96f8e8 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2920,27 +2920,34 @@ typedef enum ARMMMUIdx { ARMMMUIdx_Stage1_E1 =3D 1 | ARM_MMU_IDX_NOTLB, } ARMMMUIdx; =20 -/* Bit macros for the core-mmu-index values for each index, +/* + * Bit macros for the core-mmu-index values for each index, * for use when calling tlb_flush_by_mmuidx() and friends. */ +#define TO_CORE_BIT(NAME) \ + ARMMMUIdxBit_##NAME =3D 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_M= ASK) + typedef enum ARMMMUIdxBit { - ARMMMUIdxBit_E10_0 =3D 1 << 0, - ARMMMUIdxBit_E10_1 =3D 1 << 1, - ARMMMUIdxBit_E2 =3D 1 << 2, - ARMMMUIdxBit_SE3 =3D 1 << 3, - ARMMMUIdxBit_SE10_0 =3D 1 << 4, - ARMMMUIdxBit_SE10_1 =3D 1 << 5, - ARMMMUIdxBit_Stage2 =3D 1 << 6, - ARMMMUIdxBit_MUser =3D 1 << 0, - ARMMMUIdxBit_MPriv =3D 1 << 1, - ARMMMUIdxBit_MUserNegPri =3D 1 << 2, - ARMMMUIdxBit_MPrivNegPri =3D 1 << 3, - ARMMMUIdxBit_MSUser =3D 1 << 4, - ARMMMUIdxBit_MSPriv =3D 1 << 5, - ARMMMUIdxBit_MSUserNegPri =3D 1 << 6, - ARMMMUIdxBit_MSPrivNegPri =3D 1 << 7, + TO_CORE_BIT(E10_0), + TO_CORE_BIT(E10_1), + TO_CORE_BIT(E2), + TO_CORE_BIT(SE10_0), + TO_CORE_BIT(SE10_1), + TO_CORE_BIT(SE3), + TO_CORE_BIT(Stage2), + + TO_CORE_BIT(MUser), + TO_CORE_BIT(MPriv), + TO_CORE_BIT(MUserNegPri), + TO_CORE_BIT(MPrivNegPri), + TO_CORE_BIT(MSUser), + TO_CORE_BIT(MSPriv), + TO_CORE_BIT(MSUserNegPri), + TO_CORE_BIT(MSPrivNegPri), } ARMMMUIdxBit; =20 +#undef TO_CORE_BIT + #define MMU_USER_IDX 0 =20 static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx) --=20 2.20.1