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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id r3sm3953626pfg.145.2020.01.29.15.56.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jan 2020 15:56:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LeDolfSi5Vjl2C4cW823Vc6DsS16GoB8z85mdd7RN0c=; b=WTPLwx8k6slnkJZD8obFNswh9IKR5Ouj1qlPJ2jq2CgbJ/GMtOCtXLl/K9Nla32aD/ RsSj9OAulkkcKPaLPGuvIZhwv/omcBhBRB7dfXUfVDQ2W0vmdudSqJv5GnD1/2jMBoT2 8yyDsV9ArXitnHgrBiznLhPM/Ax2J8vCHBtL/2woOPAEfLzpKTAi/ytUFK9ITUDBatZz fPOhn880VdaYVCoavKzgoOnoESVJlrdsk5eccvQ+jAXX/OyuvmcsRZtbgixtwE9AuwHF EGHHpUlfaRgfHBH2l4z7ekncS6L+6uwZsgu4iSBK/LC+Z/ZxC8Eyt0HtFOqBPDsHpvGd 1EWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LeDolfSi5Vjl2C4cW823Vc6DsS16GoB8z85mdd7RN0c=; b=IvdnHStB3tiW1HaX8X3PTalYX/Bt/j4pDPNwCpd6RgDCVdI5UVjAqh805PQtrPNbhn a/4pyjSjxRVyrQ+7Iqju7TUfoiw+iJDa/z/ZF6QqJbiADy5T7zOcD0MMFDzULvk89nzt ZiOZnYBvXvFhTK4VlHYwh8jNDD/FQcuksBLiptOO+0DK49N2OaQyNgB/39JOVY0f0p4R l+pGaMtOG3Qp1qLfdFFETGa4KOvci5ricHIQAg/EZTzZioxd0FkLSUc8+jTL/4zOcyph o2A9BGjosdDuloa61vFYiCTRtGkzZKSWHi2az+ylVA+sv9cIfEAoxwAN6BDbw0qF6pQw 4uHg== X-Gm-Message-State: APjAAAXGSnpNpO81NuBlQU1tAPeana4Ug0sFdzkKk9fUENr/rugYell+ XrCzhBLXw+LKbNxaZcArWQuVis8cFq0= X-Google-Smtp-Source: APXvYqyhtWSyvyNSkDi24DNxVNqe5U3ZYr/YH8lXHwG9MvP8MdhAKfbEWZqzPDXlRZFL1cqbFdNFfA== X-Received: by 2002:a17:902:b215:: with SMTP id t21mr1940163plr.190.1580342195952; Wed, 29 Jan 2020 15:56:35 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 16/41] target/arm: Expand TBFLAG_ANY.MMUIDX to 4 bits Date: Wed, 29 Jan 2020 15:55:49 -0800 Message-Id: <20200129235614.29829-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200129235614.29829-1-richard.henderson@linaro.org> References: <20200129235614.29829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) We are about to expand the number of mmuidx to 10, and so need 4 bits. For the benefit of reading the number out of -d exec, align it to the penultimate nibble. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- target/arm/cpu.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 11f54556c9..893b1f1918 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3207,7 +3207,7 @@ typedef ARMCPU ArchCPU; * We put flags which are shared between 32 and 64 bit mode at the top * of the word, and flags which apply to only one mode at the bottom. * - * 31 21 18 14 9 0 + * 31 20 18 14 9 0 * +--------------+-----+-----+----------+--------------+ * | | | TBFLAG_A32 | | * | | +-----+----------+ TBFLAG_AM32 | @@ -3215,19 +3215,19 @@ typedef ARMCPU ArchCPU; * | | +-------------------------| * | | | TBFLAG_A64 | * +--------------+-----------+-------------------------+ - * 31 21 14 0 + * 31 20 14 0 * * Unless otherwise noted, these bits are cached in env->hflags. */ FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1) -FIELD(TBFLAG_ANY, MMUIDX, 28, 3) -FIELD(TBFLAG_ANY, SS_ACTIVE, 27, 1) -FIELD(TBFLAG_ANY, PSTATE_SS, 26, 1) /* Not cached. */ +FIELD(TBFLAG_ANY, SS_ACTIVE, 30, 1) +FIELD(TBFLAG_ANY, PSTATE_SS, 29, 1) /* Not cached. */ +FIELD(TBFLAG_ANY, BE_DATA, 28, 1) +FIELD(TBFLAG_ANY, MMUIDX, 24, 4) /* Target EL if we take a floating-point-disabled exception */ -FIELD(TBFLAG_ANY, FPEXC_EL, 24, 2) -FIELD(TBFLAG_ANY, BE_DATA, 23, 1) +FIELD(TBFLAG_ANY, FPEXC_EL, 22, 2) /* For A-profile only, target EL for debug exceptions. */ -FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 21, 2) +FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 20, 2) =20 /* * Bit usage when in AArch32 state, both A- and M-profile. --=20 2.20.1