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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id r3sm3953626pfg.145.2020.01.29.15.56.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jan 2020 15:56:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ADhqJD/UWaaZKMTyWOQebpJEaLJ90sszFty30wWd3+k=; b=Rf7efZNLEI8cpWsume7HytrKooNBaX+X9KREpj5lwyFvxq9c8aRL1xsUauWxDdJuWd faUNPfhVdDhwIwjaJiHemvsetaNqqPdAKtm3FNOJV9JpU7mQ+HZvmtMBxwhf7Lc3vLJI tLXwUxUKuZ0mHiIffT2JYyDRMONpxt/WMOEcaH7pd0PsTyYARTT5jzEB7lxjAn7lRFRP m6/ygdxZotma3DfJ1k3B4L0ydgMe5nNIaN1TyL2rOUFyJgPx5dvIf6KsBNVTD03qCI/q yL7CcWJzdztt7zYPuS9G9davwmovKGKnDNeWRM6zYnYJDfv3ZthjQQS8BM35lDgFcQX/ Arag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ADhqJD/UWaaZKMTyWOQebpJEaLJ90sszFty30wWd3+k=; b=keOMOwoMVZmgsUk3LcLMOEv2S/bC9TGTbRlIPZByxJYrb7ofT1FnwYpv8HTl+qpPk+ pfy8ynHhELuIgIrMyLK0VGvGcKaPcapjzEK1v8VxxNbTdZWypFXZgh41C7jR6rGvPdFr GCAvacoyB4xQ1INN+krJMMHNY5FW7L4Cxz3TQmxozBvxB2qwRKovVyAnht5duz+M+5ve lPkdu0GIEw8yX5a3QiI+2RHrHw2NMg6dXBtMPD7A0Kk+C4tyOJZhPGhmt6dr9Zaqp/vH lCtn36AlzwlPeEU5zsKYKUr3BModYPLuH1hMLgQ/Edye/G7Ub9V7Ui1oQbwxyAMLufrj PJvQ== X-Gm-Message-State: APjAAAXLIu4oGeEaOHMBIFwuToCff54YUZpvJnLMgld3iu4hIr5NSJCM yzxP1nF9hlnqVbu3s73jrvPWF8f5njA= X-Google-Smtp-Source: APXvYqybfqF34RXATgh4JVHiteM2hHM28KfWVs9C0NU/Ct3nd+FdLZE7s0bNWLKzxdL2JE3qj3m2mA== X-Received: by 2002:a17:902:8303:: with SMTP id bd3mr1967048plb.171.1580342194895; Wed, 29 Jan 2020 15:56:34 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 15/41] target/arm: Recover 4 bits from TBFLAGs Date: Wed, 29 Jan 2020 15:55:48 -0800 Message-Id: <20200129235614.29829-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200129235614.29829-1-richard.henderson@linaro.org> References: <20200129235614.29829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) We had completely run out of TBFLAG bits. Split A- and M-profile bits into two overlapping buckets. This results in 4 free bits. We used to initialize all of the a32 and m32 fields in DisasContext by assignment, in arm_tr_init_disas_context. Now we only initialize either the a32 or m32 by assignment, because the bits overlap in tbflags. So zero the entire structure in gen_intermediate_code. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- target/arm/cpu.h | 68 ++++++++++++++++++++++++++---------------- target/arm/helper.c | 17 +++++------ target/arm/translate.c | 57 +++++++++++++++++++---------------- 3 files changed, 82 insertions(+), 60 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index f984585225..11f54556c9 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3207,6 +3207,16 @@ typedef ARMCPU ArchCPU; * We put flags which are shared between 32 and 64 bit mode at the top * of the word, and flags which apply to only one mode at the bottom. * + * 31 21 18 14 9 0 + * +--------------+-----+-----+----------+--------------+ + * | | | TBFLAG_A32 | | + * | | +-----+----------+ TBFLAG_AM32 | + * | TBFLAG_ANY | |TBFLAG_M32| | + * | | +-------------------------| + * | | | TBFLAG_A64 | + * +--------------+-----------+-------------------------+ + * 31 21 14 0 + * * Unless otherwise noted, these bits are cached in env->hflags. */ FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1) @@ -3216,46 +3226,54 @@ FIELD(TBFLAG_ANY, PSTATE_SS, 26, 1) /* Not cach= ed. */ /* Target EL if we take a floating-point-disabled exception */ FIELD(TBFLAG_ANY, FPEXC_EL, 24, 2) FIELD(TBFLAG_ANY, BE_DATA, 23, 1) -/* - * For A-profile only, target EL for debug exceptions. - * Note that this overlaps with the M-profile-only HANDLER and STACKCHECK = bits. - */ +/* For A-profile only, target EL for debug exceptions. */ FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 21, 2) =20 -/* Bit usage when in AArch32 state: */ -FIELD(TBFLAG_A32, THUMB, 0, 1) /* Not cached. */ -FIELD(TBFLAG_A32, VECLEN, 1, 3) /* Not cached. */ -FIELD(TBFLAG_A32, VECSTRIDE, 4, 2) /* Not cached. */ +/* + * Bit usage when in AArch32 state, both A- and M-profile. + */ +FIELD(TBFLAG_AM32, CONDEXEC, 0, 8) /* Not cached. */ +FIELD(TBFLAG_AM32, THUMB, 8, 1) /* Not cached. */ + +/* + * Bit usage when in AArch32 state, for A-profile only. + */ +FIELD(TBFLAG_A32, VECLEN, 9, 3) /* Not cached. */ +FIELD(TBFLAG_A32, VECSTRIDE, 12, 2) /* Not cached. */ /* * We store the bottom two bits of the CPAR as TB flags and handle * checks on the other bits at runtime. This shares the same bits as * VECSTRIDE, which is OK as no XScale CPU has VFP. * Not cached, because VECLEN+VECSTRIDE are not cached. */ -FIELD(TBFLAG_A32, XSCALE_CPAR, 4, 2) +FIELD(TBFLAG_A32, XSCALE_CPAR, 12, 2) +FIELD(TBFLAG_A32, VFPEN, 14, 1) /* Partially cached, minus FPEXC. = */ +FIELD(TBFLAG_A32, SCTLR_B, 15, 1) +FIELD(TBFLAG_A32, HSTR_ACTIVE, 16, 1) /* * Indicates whether cp register reads and writes by guest code should acc= ess * the secure or nonsecure bank of banked registers; note that this is not * the same thing as the current security state of the processor! */ -FIELD(TBFLAG_A32, NS, 6, 1) -FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. = */ -FIELD(TBFLAG_A32, CONDEXEC, 8, 8) /* Not cached. */ -FIELD(TBFLAG_A32, SCTLR_B, 16, 1) -FIELD(TBFLAG_A32, HSTR_ACTIVE, 17, 1) +FIELD(TBFLAG_A32, NS, 17, 1) =20 -/* For M profile only, set if FPCCR.LSPACT is set */ -FIELD(TBFLAG_A32, LSPACT, 18, 1) /* Not cached. */ -/* For M profile only, set if we must create a new FP context */ -FIELD(TBFLAG_A32, NEW_FP_CTXT_NEEDED, 19, 1) /* Not cached. */ -/* For M profile only, set if FPCCR.S does not match current security stat= e */ -FIELD(TBFLAG_A32, FPCCR_S_WRONG, 20, 1) /* Not cached. */ -/* For M profile only, Handler (ie not Thread) mode */ -FIELD(TBFLAG_A32, HANDLER, 21, 1) -/* For M profile only, whether we should generate stack-limit checks */ -FIELD(TBFLAG_A32, STACKCHECK, 22, 1) +/* + * Bit usage when in AArch32 state, for M-profile only. + */ +/* Handler (ie not Thread) mode */ +FIELD(TBFLAG_M32, HANDLER, 9, 1) +/* Whether we should generate stack-limit checks */ +FIELD(TBFLAG_M32, STACKCHECK, 10, 1) +/* Set if FPCCR.LSPACT is set */ +FIELD(TBFLAG_M32, LSPACT, 11, 1) /* Not cached. */ +/* Set if we must create a new FP context */ +FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 12, 1) /* Not cached. */ +/* Set if FPCCR.S does not match current security state */ +FIELD(TBFLAG_M32, FPCCR_S_WRONG, 13, 1) /* Not cached. */ =20 -/* Bit usage when in AArch64 state */ +/* + * Bit usage when in AArch64 state + */ FIELD(TBFLAG_A64, TBII, 0, 2) FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) diff --git a/target/arm/helper.c b/target/arm/helper.c index a06a3a187d..53b75fd04e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11352,11 +11352,8 @@ static uint32_t rebuild_hflags_m32(CPUARMState *en= v, int fp_el, { uint32_t flags =3D 0; =20 - /* v8M always enables the fpu. */ - flags =3D FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); - if (arm_v7m_is_handler_mode(env)) { - flags =3D FIELD_DP32(flags, TBFLAG_A32, HANDLER, 1); + flags =3D FIELD_DP32(flags, TBFLAG_M32, HANDLER, 1); } =20 /* @@ -11367,7 +11364,7 @@ static uint32_t rebuild_hflags_m32(CPUARMState *env= , int fp_el, if (arm_feature(env, ARM_FEATURE_V8) && !((mmu_idx & ARM_MMU_IDX_M_NEGPRI) && (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_STKOFHFNMIGN_MASK))) { - flags =3D FIELD_DP32(flags, TBFLAG_A32, STACKCHECK, 1); + flags =3D FIELD_DP32(flags, TBFLAG_M32, STACKCHECK, 1); } =20 return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); @@ -11560,7 +11557,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_= ulong *pc, if (arm_feature(env, ARM_FEATURE_M_SECURITY) && FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S) !=3D env->v7m.secure) { - flags =3D FIELD_DP32(flags, TBFLAG_A32, FPCCR_S_WRONG, 1); + flags =3D FIELD_DP32(flags, TBFLAG_M32, FPCCR_S_WRONG, 1); } =20 if ((env->v7m.fpccr[env->v7m.secure] & R_V7M_FPCCR_ASPEN_MASK)= && @@ -11572,12 +11569,12 @@ void cpu_get_tb_cpu_state(CPUARMState *env, targe= t_ulong *pc, * active FP context; we must create a new FP context befo= re * executing any FP insn. */ - flags =3D FIELD_DP32(flags, TBFLAG_A32, NEW_FP_CTXT_NEEDED= , 1); + flags =3D FIELD_DP32(flags, TBFLAG_M32, NEW_FP_CTXT_NEEDED= , 1); } =20 bool is_secure =3D env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MAS= K; if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) { - flags =3D FIELD_DP32(flags, TBFLAG_A32, LSPACT, 1); + flags =3D FIELD_DP32(flags, TBFLAG_M32, LSPACT, 1); } } else { /* @@ -11598,8 +11595,8 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_= ulong *pc, } } =20 - flags =3D FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); - flags =3D FIELD_DP32(flags, TBFLAG_A32, CONDEXEC, env->condexec_bi= ts); + flags =3D FIELD_DP32(flags, TBFLAG_AM32, THUMB, env->thumb); + flags =3D FIELD_DP32(flags, TBFLAG_AM32, CONDEXEC, env->condexec_b= its); pstate_for_ss =3D env->uncached_cpsr; } =20 diff --git a/target/arm/translate.c b/target/arm/translate.c index 91e2ca5515..c169984374 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10848,38 +10848,48 @@ static void arm_tr_init_disas_context(DisasContex= tBase *dcbase, CPUState *cs) */ dc->secure_routed_to_el3 =3D arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3); - dc->thumb =3D FIELD_EX32(tb_flags, TBFLAG_A32, THUMB); - dc->sctlr_b =3D FIELD_EX32(tb_flags, TBFLAG_A32, SCTLR_B); - dc->hstr_active =3D FIELD_EX32(tb_flags, TBFLAG_A32, HSTR_ACTIVE); + dc->thumb =3D FIELD_EX32(tb_flags, TBFLAG_AM32, THUMB); dc->be_data =3D FIELD_EX32(tb_flags, TBFLAG_ANY, BE_DATA) ? MO_BE : MO= _LE; - condexec =3D FIELD_EX32(tb_flags, TBFLAG_A32, CONDEXEC); + condexec =3D FIELD_EX32(tb_flags, TBFLAG_AM32, CONDEXEC); dc->condexec_mask =3D (condexec & 0xf) << 1; dc->condexec_cond =3D condexec >> 4; + core_mmu_idx =3D FIELD_EX32(tb_flags, TBFLAG_ANY, MMUIDX); dc->mmu_idx =3D core_to_arm_mmu_idx(env, core_mmu_idx); dc->current_el =3D arm_mmu_idx_to_el(dc->mmu_idx); #if !defined(CONFIG_USER_ONLY) dc->user =3D (dc->current_el =3D=3D 0); #endif - dc->ns =3D FIELD_EX32(tb_flags, TBFLAG_A32, NS); dc->fp_excp_el =3D FIELD_EX32(tb_flags, TBFLAG_ANY, FPEXC_EL); - dc->vfp_enabled =3D FIELD_EX32(tb_flags, TBFLAG_A32, VFPEN); - dc->vec_len =3D FIELD_EX32(tb_flags, TBFLAG_A32, VECLEN); - if (arm_feature(env, ARM_FEATURE_XSCALE)) { - dc->c15_cpar =3D FIELD_EX32(tb_flags, TBFLAG_A32, XSCALE_CPAR); - dc->vec_stride =3D 0; + + if (arm_feature(env, ARM_FEATURE_M)) { + dc->vfp_enabled =3D 1; + dc->be_data =3D MO_TE; + dc->v7m_handler_mode =3D FIELD_EX32(tb_flags, TBFLAG_M32, HANDLER); + dc->v8m_secure =3D arm_feature(env, ARM_FEATURE_M_SECURITY) && + regime_is_secure(env, dc->mmu_idx); + dc->v8m_stackcheck =3D FIELD_EX32(tb_flags, TBFLAG_M32, STACKCHECK= ); + dc->v8m_fpccr_s_wrong =3D + FIELD_EX32(tb_flags, TBFLAG_M32, FPCCR_S_WRONG); + dc->v7m_new_fp_ctxt_needed =3D + FIELD_EX32(tb_flags, TBFLAG_M32, NEW_FP_CTXT_NEEDED); + dc->v7m_lspact =3D FIELD_EX32(tb_flags, TBFLAG_M32, LSPACT); } else { - dc->vec_stride =3D FIELD_EX32(tb_flags, TBFLAG_A32, VECSTRIDE); - dc->c15_cpar =3D 0; + dc->be_data =3D + FIELD_EX32(tb_flags, TBFLAG_ANY, BE_DATA) ? MO_BE : MO_LE; + dc->debug_target_el =3D + FIELD_EX32(tb_flags, TBFLAG_ANY, DEBUG_TARGET_EL); + dc->sctlr_b =3D FIELD_EX32(tb_flags, TBFLAG_A32, SCTLR_B); + dc->hstr_active =3D FIELD_EX32(tb_flags, TBFLAG_A32, HSTR_ACTIVE); + dc->ns =3D FIELD_EX32(tb_flags, TBFLAG_A32, NS); + dc->vfp_enabled =3D FIELD_EX32(tb_flags, TBFLAG_A32, VFPEN); + if (arm_feature(env, ARM_FEATURE_XSCALE)) { + dc->c15_cpar =3D FIELD_EX32(tb_flags, TBFLAG_A32, XSCALE_CPAR); + } else { + dc->vec_len =3D FIELD_EX32(tb_flags, TBFLAG_A32, VECLEN); + dc->vec_stride =3D FIELD_EX32(tb_flags, TBFLAG_A32, VECSTRIDE); + } } - dc->v7m_handler_mode =3D FIELD_EX32(tb_flags, TBFLAG_A32, HANDLER); - dc->v8m_secure =3D arm_feature(env, ARM_FEATURE_M_SECURITY) && - regime_is_secure(env, dc->mmu_idx); - dc->v8m_stackcheck =3D FIELD_EX32(tb_flags, TBFLAG_A32, STACKCHECK); - dc->v8m_fpccr_s_wrong =3D FIELD_EX32(tb_flags, TBFLAG_A32, FPCCR_S_WRO= NG); - dc->v7m_new_fp_ctxt_needed =3D - FIELD_EX32(tb_flags, TBFLAG_A32, NEW_FP_CTXT_NEEDED); - dc->v7m_lspact =3D FIELD_EX32(tb_flags, TBFLAG_A32, LSPACT); dc->cp_regs =3D cpu->cp_regs; dc->features =3D env->features; =20 @@ -10901,9 +10911,6 @@ static void arm_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) dc->ss_active =3D FIELD_EX32(tb_flags, TBFLAG_ANY, SS_ACTIVE); dc->pstate_ss =3D FIELD_EX32(tb_flags, TBFLAG_ANY, PSTATE_SS); dc->is_ldex =3D false; - if (!arm_feature(env, ARM_FEATURE_M)) { - dc->debug_target_el =3D FIELD_EX32(tb_flags, TBFLAG_ANY, DEBUG_TAR= GET_EL); - } =20 dc->page_start =3D dc->base.pc_first & TARGET_PAGE_MASK; =20 @@ -11340,10 +11347,10 @@ static const TranslatorOps thumb_translator_ops = =3D { /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_in= sns) { - DisasContext dc; + DisasContext dc =3D { }; const TranslatorOps *ops =3D &arm_translator_ops; =20 - if (FIELD_EX32(tb->flags, TBFLAG_A32, THUMB)) { + if (FIELD_EX32(tb->flags, TBFLAG_AM32, THUMB)) { ops =3D &thumb_translator_ops; } #ifdef TARGET_AARCH64 --=20 2.20.1